For certain parts and some versions of TZ, TZ will reset the chip
when a BARK is triggered even though it was not configured here. So
by default let's configure this BARK time as well.
Signed-off-by: Matthew McClintock <[email protected]>
---
drivers/watchdog/qcom-wdt.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c
index e46f18d..53f57c3 100644
--- a/drivers/watchdog/qcom-wdt.c
+++ b/drivers/watchdog/qcom-wdt.c
@@ -22,18 +22,21 @@
enum wdt_reg {
WDT_RST,
WDT_EN,
+ WDT_BARK_TIME,
WDT_BITE_TIME,
};
static const u32 reg_offset_data_apcs_tmr[] = {
[WDT_RST] = 0x38,
[WDT_EN] = 0x40,
+ [WDT_BARK_TIME] = 0x4C,
[WDT_BITE_TIME] = 0x5C,
};
static const u32 reg_offset_data_kpss[] = {
[WDT_RST] = 0x4,
[WDT_EN] = 0x8,
+ [WDT_BARK_TIME] = 0x10,
[WDT_BITE_TIME] = 0x14,
};
@@ -62,6 +65,7 @@ static int qcom_wdt_start(struct watchdog_device *wdd)
writel(0, wdt_addr(wdt, WDT_EN));
writel(1, wdt_addr(wdt, WDT_RST));
+ writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
writel(1, wdt_addr(wdt, WDT_EN));
return 0;
@@ -104,6 +108,7 @@ static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
writel(0, wdt_addr(wdt, WDT_EN));
writel(1, wdt_addr(wdt, WDT_RST));
+ writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
writel(1, wdt_addr(wdt, WDT_EN));
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
On 03/23, Matthew McClintock wrote:
> For certain parts and some versions of TZ, TZ will reset the chip
> when a BARK is triggered even though it was not configured here. So
> by default let's configure this BARK time as well.
>
Why isn't TZ configuring the bark time to what it wants? I'm lost
why we have to do this for them.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On Mar 23, 2016, at 5:42 PM, Stephen Boyd <[email protected]> wrote:
>
> On 03/23, Matthew McClintock wrote:
>> For certain parts and some versions of TZ, TZ will reset the chip
>> when a BARK is triggered even though it was not configured here. So
>> by default let's configure this BARK time as well.
>>
>
> Why isn't TZ configuring the bark time to what it wants? I'm lost
> why we have to do this for them.
So it was done like this to ensure we had a valid upgrade. The bootloader is using the watchdog to ensure the system is bootable and if not it will revert back to the working images.
Bottom line is, for some versions of TZ out there, if we enable watchdog coming out of boot the bark time is already configured by the boot loader and TZ is configured to intercept this interrupt and do some register saving (for crashdump) and we end up getting a watchdog reset during boot.
It’s even a little more complex, because in order for the TZ to save the registers you need to pad the BITE time a bit higher than the BARK time, but I was leaving that for another day.
-M
On Thu, Mar 24, 2016 at 10:46:42AM -0500, Matthew McClintock wrote:
> On Mar 23, 2016, at 5:42 PM, Stephen Boyd <[email protected]> wrote:
> >
> > On 03/23, Matthew McClintock wrote:
> >> For certain parts and some versions of TZ, TZ will reset the chip
> >> when a BARK is triggered even though it was not configured here. So
> >> by default let's configure this BARK time as well.
> >>
> >
> > Why isn't TZ configuring the bark time to what it wants? I'm lost
> > why we have to do this for them.
>
> So it was done like this to ensure we had a valid upgrade. The bootloader is using the watchdog to ensure the system is bootable and if not it will revert back to the working images.
>
> Bottom line is, for some versions of TZ out there, if we enable watchdog coming out of boot the bark time is already configured by the boot loader and TZ is configured to intercept this interrupt and do some register saving (for crashdump) and we end up getting a watchdog reset during boot.
>
> It’s even a little more complex, because in order for the TZ to save the registers you need to pad the BITE time a bit higher than the BARK time, but I was leaving that for another day.
>
Sounds like an op[timal target for using pretimeout ?
Guenter
On Mar 24, 2016, at 11:17 AM, Guenter Roeck <[email protected]> wrote:
>
>>> Why isn't TZ configuring the bark time to what it wants? I'm lost
>>> why we have to do this for them.
>>
>> So it was done like this to ensure we had a valid upgrade. The bootloader is using the watchdog to ensure the system is bootable and if not it will revert back to the working images.
>>
>> Bottom line is, for some versions of TZ out there, if we enable watchdog coming out of boot the bark time is already configured by the boot loader and TZ is configured to intercept this interrupt and do some register saving (for crashdump) and we end up getting a watchdog reset during boot.
>>
>> It’s even a little more complex, because in order for the TZ to save the registers you need to pad the BITE time a bit higher than the BARK time, but I was leaving that for another day.
>>
> Sounds like an op[timal target for using pretimeout ?
So the bark is basically a pretimeout, sure I think that will work. We can configure it to be off by default.
Thanks for the heads up, I’ll take a look.
-M
On 03/23/2016 03:05 PM, Matthew McClintock wrote:
> For certain parts and some versions of TZ, TZ will reset the chip
> when a BARK is triggered even though it was not configured here. So
> by default let's configure this BARK time as well.
>
> Signed-off-by: Matthew McClintock <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
> ---
> drivers/watchdog/qcom-wdt.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c
> index e46f18d..53f57c3 100644
> --- a/drivers/watchdog/qcom-wdt.c
> +++ b/drivers/watchdog/qcom-wdt.c
> @@ -22,18 +22,21 @@
> enum wdt_reg {
> WDT_RST,
> WDT_EN,
> + WDT_BARK_TIME,
> WDT_BITE_TIME,
> };
>
> static const u32 reg_offset_data_apcs_tmr[] = {
> [WDT_RST] = 0x38,
> [WDT_EN] = 0x40,
> + [WDT_BARK_TIME] = 0x4C,
> [WDT_BITE_TIME] = 0x5C,
> };
>
> static const u32 reg_offset_data_kpss[] = {
> [WDT_RST] = 0x4,
> [WDT_EN] = 0x8,
> + [WDT_BARK_TIME] = 0x10,
> [WDT_BITE_TIME] = 0x14,
> };
>
> @@ -62,6 +65,7 @@ static int qcom_wdt_start(struct watchdog_device *wdd)
>
> writel(0, wdt_addr(wdt, WDT_EN));
> writel(1, wdt_addr(wdt, WDT_RST));
> + writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
> writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
> writel(1, wdt_addr(wdt, WDT_EN));
> return 0;
> @@ -104,6 +108,7 @@ static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
>
> writel(0, wdt_addr(wdt, WDT_EN));
> writel(1, wdt_addr(wdt, WDT_RST));
> + writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
> writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
> writel(1, wdt_addr(wdt, WDT_EN));
>
>