This patch adds missing LPASS smmu clks which are required by the audio driver.
Signed-off-by: Srinivas Kandagatla <[email protected]>
---
drivers/clk/qcom/gcc-msm8996.c | 26 ++++++++++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-msm8996.h | 2 ++
2 files changed, 28 insertions(+)
diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index 56e0a295c74e..6290ce551505 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -2644,6 +2644,30 @@ static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
},
};
+static struct clk_branch gcc_hlos1_vote_lpass_core_smmu_clk = {
+ .halt_reg = 0x7d010,
+ .clkr = {
+ .enable_reg = 0x7d010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "hlos1_vote_lpass_core_smmu_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_hlos1_vote_lpass_adsp_smmu_clk = {
+ .halt_reg = 0x7d014,
+ .clkr = {
+ .enable_reg = 0x7d014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "hlos1_vote_lpass_adsp_smmu_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch gcc_ufs_rx_cfg_clk = {
.halt_reg = 0x75014,
.clkr = {
@@ -3217,6 +3241,8 @@ static struct clk_regmap *gcc_msm8996_clocks[] = {
[GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
[GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
[GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
+ [GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK] = &gcc_hlos1_vote_lpass_core_smmu_clk.clkr,
+ [GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &gcc_hlos1_vote_lpass_adsp_smmu_clk.clkr,
[GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
[GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
[GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h
index 1847e130f5a0..4df1898d71b2 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8996.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8996.h
@@ -229,6 +229,8 @@
#define GCC_PCIE_CLKREF_CLK 216
#define GCC_RX2_USB2_CLKREF_CLK 217
#define GCC_RX1_USB2_CLKREF_CLK 218
+#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 219
+#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 220
#define GCC_SYSTEM_NOC_BCR 0
#define GCC_CONFIG_NOC_BCR 1
--
2.11.0
On 06/12, Srinivas Kandagatla wrote:
> This patch adds missing LPASS smmu clks which are required by the audio driver.
>
> Signed-off-by: Srinivas Kandagatla <[email protected]>
> ---
> drivers/clk/qcom/gcc-msm8996.c | 26 ++++++++++++++++++++++++++
> include/dt-bindings/clock/qcom,gcc-msm8996.h | 2 ++
> 2 files changed, 28 insertions(+)
>
> diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
> index 56e0a295c74e..6290ce551505 100644
> --- a/drivers/clk/qcom/gcc-msm8996.c
> +++ b/drivers/clk/qcom/gcc-msm8996.c
> @@ -2644,6 +2644,30 @@ static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
> },
> };
>
> +static struct clk_branch gcc_hlos1_vote_lpass_core_smmu_clk = {
> + .halt_reg = 0x7d010,
Don't we need .halt_check = BRANCH_HALT_VOTED for these?
> + .clkr = {
> + .enable_reg = 0x7d010,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "hlos1_vote_lpass_core_smmu_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_hlos1_vote_lpass_adsp_smmu_clk = {
> + .halt_reg = 0x7d014,
> + .clkr = {
> + .enable_reg = 0x7d014,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "hlos1_vote_lpass_adsp_smmu_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 20/06/17 01:47, Stephen Boyd wrote:
> On 06/12, Srinivas Kandagatla wrote:
>> This patch adds missing LPASS smmu clks which are required by the audio driver.
>>
>> Signed-off-by: Srinivas Kandagatla <[email protected]>
>> ---
>> drivers/clk/qcom/gcc-msm8996.c | 26 ++++++++++++++++++++++++++
>> include/dt-bindings/clock/qcom,gcc-msm8996.h | 2 ++
>> 2 files changed, 28 insertions(+)
>>
>> diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
>> index 56e0a295c74e..6290ce551505 100644
>> --- a/drivers/clk/qcom/gcc-msm8996.c
>> +++ b/drivers/clk/qcom/gcc-msm8996.c
>> @@ -2644,6 +2644,30 @@ static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
>> },
>> };
>>
>> +static struct clk_branch gcc_hlos1_vote_lpass_core_smmu_clk = {
>> + .halt_reg = 0x7d010,
>
> Don't we need .halt_check = BRANCH_HALT_VOTED for these?
>
I don't think we need it for these clks, Downstream driver has
no_halt_check_on_disable = true for both these clks.
thanks,
srini
>> + .clkr = {
>> + .enable_reg = 0x7d010,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "hlos1_vote_lpass_core_smmu_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_hlos1_vote_lpass_adsp_smmu_clk = {
>> + .halt_reg = 0x7d014,
>> + .clkr = {
>> + .enable_reg = 0x7d014,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "hlos1_vote_lpass_adsp_smmu_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>
On 06/23, Srinivas Kandagatla wrote:
>
>
> On 20/06/17 01:47, Stephen Boyd wrote:
> >On 06/12, Srinivas Kandagatla wrote:
> >>This patch adds missing LPASS smmu clks which are required by the audio driver.
> >>
> >>Signed-off-by: Srinivas Kandagatla <[email protected]>
> >>---
> >> drivers/clk/qcom/gcc-msm8996.c | 26 ++++++++++++++++++++++++++
> >> include/dt-bindings/clock/qcom,gcc-msm8996.h | 2 ++
> >> 2 files changed, 28 insertions(+)
> >>
> >>diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
> >>index 56e0a295c74e..6290ce551505 100644
> >>--- a/drivers/clk/qcom/gcc-msm8996.c
> >>+++ b/drivers/clk/qcom/gcc-msm8996.c
> >>@@ -2644,6 +2644,30 @@ static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
> >> },
> >> };
> >>+static struct clk_branch gcc_hlos1_vote_lpass_core_smmu_clk = {
> >>+ .halt_reg = 0x7d010,
> >
> >Don't we need .halt_check = BRANCH_HALT_VOTED for these?
> >
> I don't think we need it for these clks, Downstream driver has
> no_halt_check_on_disable = true for both these clks.
>
>
Right, no_halt_check_on_disable means we don't check the halt bit
when disabling the clk, but we _do_ check the halt bit when
enabling. In upstream clk driver that would be indicated with
BRANCH_HALT_VOTED, where we check the halt bit when enabling and
it's voted and do a small udelay() if we're disabling and it's
voted. I suppose that small udelay() could be removed because it
doesn't really matter that it turns off or not when we're
disabling a voted clk.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project