The ethsys registers a reset controller, so we need to specify a
reset cell. This patch fixes the documentation.
Signed-off-by: Matthias Brugger <[email protected]>
---
Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
index 7aa3fa167668..6cc7840ff37a 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
@@ -20,4 +20,5 @@ ethsys: clock-controller@1b000000 {
compatible = "mediatek,mt2701-ethsys", "syscon";
reg = <0 0x1b000000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
--
2.12.3
The hifsys and ethsys needs the definition of the reset-cells
property. Fix this.
Signed-off-by: Matthias Brugger <[email protected]>
---
arch/arm/boot/dts/mt2701.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 965ddfbc9953..05557fce0f1d 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -604,6 +604,7 @@
compatible = "mediatek,mt2701-hifsys", "syscon";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
usb0: usb@1a1c0000 {
@@ -688,6 +689,7 @@
compatible = "mediatek,mt2701-ethsys", "syscon";
reg = <0 0x1b000000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
eth: ethernet@1b100000 {
--
2.12.3
The ethsys binding misses the reset-cells, this patch
adds this property.
Signed-off-by: Matthias Brugger <[email protected]>
---
arch/arm/boot/dts/mt7623.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index 343d3b1a4448..b750da5362f7 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -758,6 +758,7 @@
"syscon";
reg = <0 0x1b000000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
eth: ethernet@1b100000 {
--
2.12.3
On Fri, Dec 01, 2017 at 01:07:06PM +0100, Matthias Brugger wrote:
> The ethsys registers a reset controller, so we need to specify a
> reset cell. This patch fixes the documentation.
>
> Signed-off-by: Matthias Brugger <[email protected]>
> ---
> Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 +
> 1 file changed, 1 insertion(+)
For all 3,
Reviewed-by: Rob Herring <[email protected]>
Hi Stephen, Michael,
On 12/01/2017 01:07 PM, Matthias Brugger wrote:
> The ethsys registers a reset controller, so we need to specify a
> reset cell. This patch fixes the documentation.
>
> Signed-off-by: Matthias Brugger <[email protected]>
> ---
> Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
> index 7aa3fa167668..6cc7840ff37a 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
> @@ -20,4 +20,5 @@ ethsys: clock-controller@1b000000 {
> compatible = "mediatek,mt2701-ethsys", "syscon";
> reg = <0 0x1b000000 0 0x1000>;
> #clock-cells = <1>;
> + #reset-cells = <1>;
> };
>
Will you take this patch through the clk tree, or shall I take it through my SoC
tree?
Regards,
Matthias
On 12/01/2017 01:07 PM, Matthias Brugger wrote:
> The hifsys and ethsys needs the definition of the reset-cells
> property. Fix this.
>
> Signed-off-by: Matthias Brugger <[email protected]>
> ---
> arch/arm/boot/dts/mt2701.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index 965ddfbc9953..05557fce0f1d 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -604,6 +604,7 @@
> compatible = "mediatek,mt2701-hifsys", "syscon";
> reg = <0 0x1a000000 0 0x1000>;
> #clock-cells = <1>;
> + #reset-cells = <1>;
> };
>
> usb0: usb@1a1c0000 {
> @@ -688,6 +689,7 @@
> compatible = "mediatek,mt2701-ethsys", "syscon";
> reg = <0 0x1b000000 0 0x1000>;
> #clock-cells = <1>;
> + #reset-cells = <1>;
> };
>
> eth: ethernet@1b100000 {
>
2 and 3 pushed to v4.15-next/dts32
Thanks!
On 12/14, Matthias Brugger wrote:
> Hi Stephen, Michael,
>
> On 12/01/2017 01:07 PM, Matthias Brugger wrote:
> > The ethsys registers a reset controller, so we need to specify a
> > reset cell. This patch fixes the documentation.
> >
> > Signed-off-by: Matthias Brugger <[email protected]>
> > ---
> > Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
> > index 7aa3fa167668..6cc7840ff37a 100644
> > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
> > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
> > @@ -20,4 +20,5 @@ ethsys: clock-controller@1b000000 {
> > compatible = "mediatek,mt2701-ethsys", "syscon";
> > reg = <0 0x1b000000 0 0x1000>;
> > #clock-cells = <1>;
> > + #reset-cells = <1>;
> > };
> >
>
> Will you take this patch through the clk tree, or shall I take it through my SoC
> tree?
>
It's resets, we are clk maintainers. I'm clkfused.
You can take it, along with my
Acked-by: Stephen Boyd <[email protected]>
if you like/expect conflicts.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 12/19/2017 02:32 AM, Stephen Boyd wrote:
> On 12/14, Matthias Brugger wrote:
>> Hi Stephen, Michael,
>>
>> On 12/01/2017 01:07 PM, Matthias Brugger wrote:
>>> The ethsys registers a reset controller, so we need to specify a
>>> reset cell. This patch fixes the documentation.
>>>
>>> Signed-off-by: Matthias Brugger <[email protected]>
>>> ---
>>> Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 +
>>> 1 file changed, 1 insertion(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
>>> index 7aa3fa167668..6cc7840ff37a 100644
>>> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
>>> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
>>> @@ -20,4 +20,5 @@ ethsys: clock-controller@1b000000 {
>>> compatible = "mediatek,mt2701-ethsys", "syscon";
>>> reg = <0 0x1b000000 0 0x1000>;
>>> #clock-cells = <1>;
>>> + #reset-cells = <1>;
>>> };
>>>
>>
>> Will you take this patch through the clk tree, or shall I take it through my SoC
>> tree?
>>
>
> It's resets, we are clk maintainers. I'm clkfused.
>
> You can take it, along with my
>
> Acked-by: Stephen Boyd <[email protected]>
>
> if you like/expect conflicts.
>
These are resets in the clock IP-block. I'll take it through my branch, I don't
expect any conflicts.
Regards,
Matthias
Quoting Matthias Brugger (2017-12-20 09:13:12)
>
>
> On 12/19/2017 02:32 AM, Stephen Boyd wrote:
> > On 12/14, Matthias Brugger wrote:
> >> Hi Stephen, Michael,
> >>
> >> On 12/01/2017 01:07 PM, Matthias Brugger wrote:
> >>> The ethsys registers a reset controller, so we need to specify a
> >>> reset cell. This patch fixes the documentation.
> >>>
> >>> Signed-off-by: Matthias Brugger <[email protected]>
> >>> ---
> >>> Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 +
> >>> 1 file changed, 1 insertion(+)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
> >>> index 7aa3fa167668..6cc7840ff37a 100644
> >>> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
> >>> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
> >>> @@ -20,4 +20,5 @@ ethsys: clock-controller@1b000000 {
> >>> compatible = "mediatek,mt2701-ethsys", "syscon";
> >>> reg = <0 0x1b000000 0 0x1000>;
> >>> #clock-cells = <1>;
> >>> + #reset-cells = <1>;
> >>> };
> >>>
> >>
> >> Will you take this patch through the clk tree, or shall I take it through my SoC
> >> tree?
> >>
> >
> > It's resets, we are clk maintainers. I'm clkfused.
> >
> > You can take it, along with my
> >
> > Acked-by: Stephen Boyd <[email protected]>
> >
> > if you like/expect conflicts.
> >
>
> These are resets in the clock IP-block. I'll take it through my branch, I don't
> expect any conflicts.
Sounds good to me.
Best regards,
Mike
>
> Regards,
> Matthias