by kernel test robot

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Subject: Re: [PATCH v4 03/10] PCI: Update xxx_pcie_ep_raise_irq() and pci_epc_raise_irq() signatures

Hi Gustavo,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on pci/next]
[also build test ERROR on v4.18-rc1 next-20180618]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url: https://github.com/0day-ci/linux/commits/Gustavo-Pimentel/Add-MSI-X-support-on-pcitest-tool/20180619-004625
base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: ia64-allmodconfig (attached as .config)
compiler: ia64-linux-gcc (GCC) 8.1.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=8.1.0 make.cross ARCH=ia64

All errors (new ones prefixed by >>):

>> drivers/pci/controller/pcie-rockchip-ep.c:516:15: error: initialization of 'int (*)(struct pci_epc *, u8, enum pci_epc_irq_type, u16)' {aka 'int (*)(struct pci_epc *, unsigned char, enum pci_epc_irq_type, short unsigned int)'} from incompatible pointer type 'int (*)(struct pci_epc *, u8, enum pci_epc_irq_type, u8)' {aka 'int (*)(struct pci_epc *, unsigned char, enum pci_epc_irq_type, unsigned char)'} [-Werror=incompatible-pointer-types]
.raise_irq = rockchip_pcie_ep_raise_irq,
^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/pci/controller/pcie-rockchip-ep.c:516:15: note: (near initialization for 'rockchip_pcie_epc_ops.raise_irq')
cc1: some warnings being treated as errors

vim +516 drivers/pci/controller/pcie-rockchip-ep.c

cf590b07 drivers/pci/host/pcie-rockchip-ep.c Shawn Lin 2018-05-09 507
cf590b07 drivers/pci/host/pcie-rockchip-ep.c Shawn Lin 2018-05-09 508 static const struct pci_epc_ops rockchip_pcie_epc_ops = {
cf590b07 drivers/pci/host/pcie-rockchip-ep.c Shawn Lin 2018-05-09 509 .write_header = rockchip_pcie_ep_write_header,
cf590b07 drivers/pci/host/pcie-rockchip-ep.c Shawn Lin 2018-05-09 510 .set_bar = rockchip_pcie_ep_set_bar,
cf590b07 drivers/pci/host/pcie-rockchip-ep.c Shawn Lin 2018-05-09 511 .clear_bar = rockchip_pcie_ep_clear_bar,
cf590b07 drivers/pci/host/pcie-rockchip-ep.c Shawn Lin 2018-05-09 512 .map_addr = rockchip_pcie_ep_map_addr,
cf590b07 drivers/pci/host/pcie-rockchip-ep.c Shawn Lin 2018-05-09 513 .unmap_addr = rockchip_pcie_ep_unmap_addr,
cf590b07 drivers/pci/host/pcie-rockchip-ep.c Shawn Lin 2018-05-09 514 .set_msi = rockchip_pcie_ep_set_msi,
cf590b07 drivers/pci/host/pcie-rockchip-ep.c Shawn Lin 2018-05-09 515 .get_msi = rockchip_pcie_ep_get_msi,
cf590b07 drivers/pci/host/pcie-rockchip-ep.c Shawn Lin 2018-05-09 @516 .raise_irq = rockchip_pcie_ep_raise_irq,
cf590b07 drivers/pci/host/pcie-rockchip-ep.c Shawn Lin 2018-05-09 517 .start = rockchip_pcie_ep_start,
cf590b07 drivers/pci/host/pcie-rockchip-ep.c Shawn Lin 2018-05-09 518 };
cf590b07 drivers/pci/host/pcie-rockchip-ep.c Shawn Lin 2018-05-09 519

:::::: The code at line 516 was first introduced by commit
:::::: cf590b07839133146842d2d3d9a68f804c2edc4b PCI: rockchip: Add EP driver for Rockchip PCIe controller

:::::: TO: Shawn Lin <[email protected]>
:::::: CC: Lorenzo Pieralisi <[email protected]>

---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation

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2018-06-18 18:58:39

Hi,

On 20/06/2018 08:53, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Monday 18 June 2018 08:30 PM, Gustavo Pimentel wrote:
>> Cleanup PCI_ENDPOINT_TEST memspace (by moving the interrupt number away
>> from command section).
>>
>> Signed-off-by: Gustavo Pimentel <[email protected]>
>> ---
>> Change v2->v3:
>> - New patch file created base on the previous patch
>> "misc: pci_endpoint_test: Add MSI-X support" patch file following
>> Kishon's suggestion.
>> Change v3->v4:
>> - Rebased to Lorenzo's master branch v4.18-rc1.
>>
>> drivers/misc/pci_endpoint_test.c | 84 ++++++++++++++++-----------
>> drivers/pci/endpoint/functions/pci-epf-test.c | 60 ++++++++++++-------
>> 2 files changed, 91 insertions(+), 53 deletions(-)
>>
>> diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
>> index 7b37046..56be808 100644
>> --- a/drivers/misc/pci_endpoint_test.c
>> +++ b/drivers/misc/pci_endpoint_test.c
>> @@ -35,38 +35,42 @@
>>
>> #include <uapi/linux/pcitest.h>
>>
>> -#define DRV_MODULE_NAME "pci-endpoint-test"
>> -
>> -#define PCI_ENDPOINT_TEST_MAGIC 0x0
>> -
>> -#define PCI_ENDPOINT_TEST_COMMAND 0x4
>> -#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
>> -#define COMMAND_RAISE_MSI_IRQ BIT(1)
>> -#define MSI_NUMBER_SHIFT 2
>> -/* 6 bits for MSI number */
>> -#define COMMAND_READ BIT(8)
>> -#define COMMAND_WRITE BIT(9)
>> -#define COMMAND_COPY BIT(10)
>> -
>> -#define PCI_ENDPOINT_TEST_STATUS 0x8
>> -#define STATUS_READ_SUCCESS BIT(0)
>> -#define STATUS_READ_FAIL BIT(1)
>> -#define STATUS_WRITE_SUCCESS BIT(2)
>> -#define STATUS_WRITE_FAIL BIT(3)
>> -#define STATUS_COPY_SUCCESS BIT(4)
>> -#define STATUS_COPY_FAIL BIT(5)
>> -#define STATUS_IRQ_RAISED BIT(6)
>> -#define STATUS_SRC_ADDR_INVALID BIT(7)
>> -#define STATUS_DST_ADDR_INVALID BIT(8)
>> -
>> -#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0xc
>> +#define DRV_MODULE_NAME "pci-endpoint-test"
>> +
>> +#define IRQ_TYPE_LEGACY 0
>> +#define IRQ_TYPE_MSI 1
>> +
>> +#define PCI_ENDPOINT_TEST_MAGIC 0x0
>> +
>> +#define PCI_ENDPOINT_TEST_COMMAND 0x4
>> +#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
>> +#define COMMAND_RAISE_MSI_IRQ BIT(1)
>
> Maybe you can add a comment here that BIT(2) is reserved for MSIX support

Sure.

>> +#define COMMAND_READ BIT(3)
>> +#define COMMAND_WRITE BIT(4)
>> +#define COMMAND_COPY BIT(5)
>> +
>> +#define PCI_ENDPOINT_TEST_STATUS 0x8
>> +#define STATUS_READ_SUCCESS BIT(0)
>> +#define STATUS_READ_FAIL BIT(1)
>> +#define STATUS_WRITE_SUCCESS BIT(2)
>> +#define STATUS_WRITE_FAIL BIT(3)
>> +#define STATUS_COPY_SUCCESS BIT(4)
>> +#define STATUS_COPY_FAIL BIT(5)
>> +#define STATUS_IRQ_RAISED BIT(6)
>> +#define STATUS_SRC_ADDR_INVALID BIT(7)
>> +#define STATUS_DST_ADDR_INVALID BIT(8)
>> +
>> +#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0x0c
>> #define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10
>>
>> #define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14
>> #define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18
>>
>> -#define PCI_ENDPOINT_TEST_SIZE 0x1c
>> -#define PCI_ENDPOINT_TEST_CHECKSUM 0x20
>> +#define PCI_ENDPOINT_TEST_SIZE 0x1c
>> +#define PCI_ENDPOINT_TEST_CHECKSUM 0x20
>> +
>> +#define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24
>
> Is this not redundant? COMMAND_RAISE_LEGACY_IRQ, COMMAND_RAISE_MSI_IRQ already
> indicates the irq type to be used.

In previous implementation the distinction between interrupt types was simpler,
basically legacy *number* always set as zero and the MSI *number* always
non-zero. However by introducing the MSI-X this simple mechanism is no longer
valid, because the MSI-X *number* is also always non-zero like as MSI.
Therefore is necessary to distinguish which interrupt type was been triggered
(MSI or MSI-X) especially for the Write/Read/Copy tests.

>> +#define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28
>>
>> static DEFINE_IDA(pci_endpoint_test_ida);
>>
>> @@ -179,6 +183,9 @@ static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)
>> {
>> u32 val;
>>
>> + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
>> + IRQ_TYPE_LEGACY);
>> + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0);
>
> Not sure if the above writes are really required.

Is not required, but I added those write for keeping the code coherency between
pci_endpoint_test_legacy_irq() and pci_endpoint_test_msi_irq(), basically both
functions write on the same registers. I think it doesn't cause any harm.

>> pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
>> COMMAND_RAISE_LEGACY_IRQ);
>> val = wait_for_completion_timeout(&test->irq_raised,
>> @@ -190,20 +197,22 @@ static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)
>> }
>>
>> static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
>> - u8 msi_num)
>> + u8 irq_num)
>
> why do you want to rename this?

Initially this patch file contained the changes related to MSI-X support and by
that time I had changed the name of this variable so that its name had a broader
meaning that contemplated these two types. Now that I see this, I think the
original name may also be valid, I will revert this name change.

Regards,
Gustavo

>
> Thanks
> Kishon
>

2018-06-20 14:32:30

by Gustavo Pimentel

[permalink] [raw]

Subject: Re: [PATCH v4 09/10] pci_endpoint_test: Add 2 ioctl commands

Hi,

On 20/06/2018 08:58, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Monday 18 June 2018 08:30 PM, Gustavo Pimentel wrote:
>> Add MSI-X support and update driver documentation accordingly.
>>
>> Add 2 new IOCTL commands:
>> - Allow to reconfigure driver IRQ type in runtime.
>> - Allow to retrieve current driver IRQ type configured.
>>
>> Signed-off-by: Gustavo Pimentel <[email protected]>
>> ---
>> Change v2->v3:
>> - New patch file created base on the previous patch
>> "misc: pci_endpoint_test: Add MSI-X support" patch file following
>> Kishon's suggestion.
>> Change v3->v4:
>> - Rebased to Lorenzo's master branch v4.18-rc1.
>>
>> Documentation/misc-devices/pci-endpoint-test.txt | 3 +
>> drivers/misc/pci_endpoint_test.c | 177 +++++++++++++++++------
>> 2 files changed, 132 insertions(+), 48 deletions(-)
>>
>> diff --git a/Documentation/misc-devices/pci-endpoint-test.txt b/Documentation/misc-devices/pci-endpoint-test.txt
>> index fdfa0f6..58ccca4 100644
>> --- a/Documentation/misc-devices/pci-endpoint-test.txt
>> +++ b/Documentation/misc-devices/pci-endpoint-test.txt
>> @@ -28,6 +28,9 @@ ioctl
>> to be tested should be passed as argument.
>> PCITEST_MSIX: Tests message signalled interrupts. The MSI-X number
>> to be tested should be passed as argument.
>> + PCITEST_SET_IRQTYPE: Changes driver IRQ type configuration. The IRQ type
>> + should be passed as argument (0: Legacy, 1:MSI, 2:MSI-X).
>> + PCITEST_GET_IRQTYPE: Gets driver IRQ type configuration.
>> PCITEST_WRITE: Perform write tests. The size of the buffer should be passed
>> as argument.
>> PCITEST_READ: Perform read tests. The size of the buffer should be passed
>> diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
>> index 8d15dbe..df2017f 100644
>> --- a/drivers/misc/pci_endpoint_test.c
>> +++ b/drivers/misc/pci_endpoint_test.c
>> @@ -157,6 +157,87 @@ static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id)
>> return IRQ_HANDLED;
>> }
>>
>> +static void pci_endpoint_test_free_irq_vectors(struct pci_endpoint_test *test)
>> +{
>> + int i;
>> + struct pci_dev *pdev = test->pdev;
>> + struct device *dev = &pdev->dev;
>> +
>> + for (i = 0; i < test->num_irqs; i++)
>> + devm_free_irq(dev, pci_irq_vector(pdev, i), test);
>> +
>> + test->num_irqs = 0;
>> +}
>> +
>> +static bool pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test *test)
>> +{
>> + int irq = -1;
>> + struct pci_dev *pdev = test->pdev;
>> + struct device *dev = &pdev->dev;
>> + bool res = true;
>> +
>> + switch (irq_type) {
>> + case IRQ_TYPE_LEGACY:
>> + irq = 0;
>> + break;
>> + case IRQ_TYPE_MSI:
>> + irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
>> + if (irq < 0)
>> + dev_err(dev, "Failed to get MSI interrupts\n");
>> + break;
>> + case IRQ_TYPE_MSIX:
>> + irq = pci_alloc_irq_vectors(pdev, 1, 2048, PCI_IRQ_MSIX);
>> + if (irq < 0)
>> + dev_err(dev, "Failed to get MSI-X interrupts\n");
>> + break;
>> + default:
>> + dev_err(dev, "Invalid IRQ type selected\n");
>> + }
>> +
>> + if (irq < 0) {
>> + irq = 0;
>> + res = false;
>> + }
>> + test->num_irqs = irq;
>> +
>> + return res;
>> +}
>> +
>> +static void pci_endpoint_test_release_irq(struct pci_endpoint_test *test)
>> +{
>> + struct pci_dev *pdev = test->pdev;
>> +
>> + pci_disable_msi(pdev);
>> + pci_disable_msix(pdev);
>> +}
>> +
>> +static bool pci_endpoint_test_request_irq(struct pci_endpoint_test *test)
>> +{
>> + int i;
>> + int err;
>> + struct pci_dev *pdev = test->pdev;
>> + struct device *dev = &pdev->dev;
>> +
>> + err = devm_request_irq(dev, pdev->irq, pci_endpoint_test_irqhandler,
>> + IRQF_SHARED, DRV_MODULE_NAME, test);
>> + if (err) {
>> + dev_err(dev, "Failed to request IRQ %d\n", pdev->irq);
>> + return false;
>> + }
>> +
>> + for (i = 1; i < test->num_irqs; i++) {
>> + err = devm_request_irq(dev, pci_irq_vector(pdev, i),
>> + pci_endpoint_test_irqhandler,
>> + IRQF_SHARED, DRV_MODULE_NAME, test);
>> + if (err)
>> + dev_err(dev, "Failed to request IRQ %d for MSI%s %d\n",
>> + pci_irq_vector(pdev, i),
>> + irq_type == IRQ_TYPE_MSIX ? "-X" : "", i + 1);
>> + }
>> +
>> + return true;
>> +}
>> +
>> static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
>> enum pci_barno barno)
>> {
>> @@ -440,6 +521,38 @@ static bool pci_endpoint_test_read(struct pci_endpoint_test *test, size_t size)
>> return ret;
>> }
>>
>> +static bool pci_endpoint_test_set_irq(struct pci_endpoint_test *test,
>> + int req_irq_type)
>> +{
>> + struct pci_dev *pdev = test->pdev;
>> + struct device *dev = &pdev->dev;
>> +
>> + if (req_irq_type < IRQ_TYPE_LEGACY || req_irq_type > IRQ_TYPE_MSIX) {
>> + dev_err(dev, "Invalid IRQ type option\n");
>> + return false;
>> + }
>> +
>> + if (irq_type == req_irq_type)
>> + return true;
>> +
>> + irq_type = req_irq_type;
>> +
>> + pci_endpoint_test_free_irq_vectors(test);
>> + pci_endpoint_test_release_irq(test);
>> +
>> + if (!pci_endpoint_test_alloc_irq_vectors(test)) {
>> + pci_endpoint_test_release_irq(test);
>> + return false;
>> + }
>> +
>> + if (!pci_endpoint_test_request_irq(test)) {
>> + pci_endpoint_test_release_irq(test);
>> + return false;
>> + }
>> +
>> + return true;
>> +}
>> +
>> static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
>> unsigned long arg)
>> {
>> @@ -471,6 +584,12 @@ static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
>> case PCITEST_COPY:
>> ret = pci_endpoint_test_copy(test, arg);
>> break;
>> + case PCITEST_SET_IRQTYPE:
>> + ret = pci_endpoint_test_set_irq(test, arg);
>> + break;
>> + case PCITEST_GET_IRQTYPE:
>> + ret = irq_type;
>
> Can't the set_irq be done as part of raise irq itself?

That could work for the legacy/MSI/MSI-X tests, but not for the Write/Read/Copy
tests... From what I saw, it was possible to perform Write/Read/Copy tests with
either legacy or MSI on the previous version. I'm assuming that you don't wanna
to lose that functionalities, right?

Regards,
Gustavo

>
> Thanks
> Kishon
>