Add initial dtsi file for Synaptics AS370 SoC.
patch1 moves berlin binding to syna.txt.
patch2 add dt-binding for the AS370 SoC.
patch3 add the initial dtsi file for the SoC.
Jisheng Zhang (3):
dt-bindings: arm: move berlin binding documentation to syna.txt
dt-bindings: arm: syna: add support for the AS370 SoC
arm64: dts: synaptics: add dtsi file for Synaptics AS370 SoC
.../{marvell/marvell,berlin.txt => syna.txt} | 6 +-
arch/arm64/boot/dts/synaptics/as370.dtsi | 177 ++++++++++++++++++
2 files changed, 182 insertions(+), 1 deletion(-)
rename Documentation/devicetree/bindings/arm/{marvell/marvell,berlin.txt => syna.txt} (94%)
create mode 100644 arch/arm64/boot/dts/synaptics/as370.dtsi
--
2.18.0
Move berlin binding documentation as part of transition from Marvell
berlin to Synaptics SoC.
Signed-off-by: Jisheng Zhang <[email protected]>
---
.../bindings/arm/{marvell/marvell,berlin.txt => syna.txt} | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/arm/{marvell/marvell,berlin.txt => syna.txt} (100%)
diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/syna.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/marvell/marvell,berlin.txt
rename to Documentation/devicetree/bindings/arm/syna.txt
--
2.18.0
The AS370 SoC is a new derivative of the berlin family. The only
difference is the SoC isn't named as berlin*.
Signed-off-by: Jisheng Zhang <[email protected]>
---
Documentation/devicetree/bindings/arm/syna.txt | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/syna.txt b/Documentation/devicetree/bindings/arm/syna.txt
index 3bab18409b7a..3ba1d7b5ee74 100644
--- a/Documentation/devicetree/bindings/arm/syna.txt
+++ b/Documentation/devicetree/bindings/arm/syna.txt
@@ -1,4 +1,4 @@
-Marvell Berlin SoC Family Device Tree Bindings
+Synaptics SoC Device Tree Bindings
---------------------------------------------------------------
Work in progress statement:
@@ -13,6 +13,10 @@ stable binding/ABI.
---------------------------------------------------------------
+Boards with the Synaptics AS370 SoC shall have the following properties:
+ Required root node property:
+ compatible: "syna,as370"
+
Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
shall have the following properties:
--
2.18.0
Add initial dtsi file to support Synaptics AS370 SoC with quad
Cortex-A53 CPUs.
Signed-off-by: Jisheng Zhang <[email protected]>
---
arch/arm64/boot/dts/synaptics/as370.dtsi | 177 +++++++++++++++++++++++
1 file changed, 177 insertions(+)
create mode 100644 arch/arm64/boot/dts/synaptics/as370.dtsi
diff --git a/arch/arm64/boot/dts/synaptics/as370.dtsi b/arch/arm64/boot/dts/synaptics/as370.dtsi
new file mode 100644
index 000000000000..20f3d658c566
--- /dev/null
+++ b/arch/arm64/boot/dts/synaptics/as370.dtsi
@@ -0,0 +1,177 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2018 Synaptics Incorporated
+ *
+ * Author: Jisheng Zhang <[email protected]>
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "syna,as370";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x1>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x2>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x3>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ };
+
+ l2: cache {
+ compatible = "cache";
+ };
+
+ idle-states {
+ entry-method = "psci";
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <75>;
+ exit-latency-us = <155>;
+ min-residency-us = <1000>;
+ };
+ };
+ };
+
+ osc: osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>,
+ <&cpu1>,
+ <&cpu2>,
+ <&cpu3>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ soc@f7000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xf7000000 0x1000000>;
+
+ gic: interrupt-controller@901000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x901000 0x1000>,
+ <0x902000 0x2000>,
+ <0x904000 0x2000>,
+ <0x906000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ apb@e80000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xe80000 0x10000>;
+
+ uart0: uart@0c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0c00 0x100>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ gpio0: gpio@1800 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x1800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ porta: gpio-port@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpio1: gpio@2000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x2000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ portb: gpio-port@1 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ };
+ };
+};
--
2.18.0
On Fri, Jul 13, 2018 at 05:18:59PM +0800, Jisheng Zhang wrote:
> Move berlin binding documentation as part of transition from Marvell
> berlin to Synaptics SoC.
>
> Signed-off-by: Jisheng Zhang <[email protected]>
> ---
> .../bindings/arm/{marvell/marvell,berlin.txt => syna.txt} | 0
> 1 file changed, 0 insertions(+), 0 deletions(-)
> rename Documentation/devicetree/bindings/arm/{marvell/marvell,berlin.txt => syna.txt} (100%)
Acked-by: Rob Herring <[email protected]>
On Fri, Jul 13, 2018 at 05:24:57PM +0800, Jisheng Zhang wrote:
> The AS370 SoC is a new derivative of the berlin family. The only
> difference is the SoC isn't named as berlin*.
So is it a derivative or just rebranded?
> Signed-off-by: Jisheng Zhang <[email protected]>
> ---
> Documentation/devicetree/bindings/arm/syna.txt | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/syna.txt b/Documentation/devicetree/bindings/arm/syna.txt
> index 3bab18409b7a..3ba1d7b5ee74 100644
> --- a/Documentation/devicetree/bindings/arm/syna.txt
> +++ b/Documentation/devicetree/bindings/arm/syna.txt
> @@ -1,4 +1,4 @@
> -Marvell Berlin SoC Family Device Tree Bindings
> +Synaptics SoC Device Tree Bindings
Perhaps some note about what has happened here. Otherwise it looks
strange having "Marvell Berlin" in the document when the title says
Synaptics SoC.
> ---------------------------------------------------------------
>
> Work in progress statement:
> @@ -13,6 +13,10 @@ stable binding/ABI.
>
> ---------------------------------------------------------------
>
> +Boards with the Synaptics AS370 SoC shall have the following properties:
> + Required root node property:
> + compatible: "syna,as370"
> +
> Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
> shall have the following properties:
>
> --
> 2.18.0
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to [email protected]
> More majordomo info at http://vger.kernel.org/majordomo-info.html
On Fri, Jul 13, 2018 at 05:26:26PM +0800, Jisheng Zhang wrote:
> Add initial dtsi file to support Synaptics AS370 SoC with quad
> Cortex-A53 CPUs.
>
> Signed-off-by: Jisheng Zhang <[email protected]>
> ---
> arch/arm64/boot/dts/synaptics/as370.dtsi | 177 +++++++++++++++++++++++
> 1 file changed, 177 insertions(+)
> create mode 100644 arch/arm64/boot/dts/synaptics/as370.dtsi
>
> diff --git a/arch/arm64/boot/dts/synaptics/as370.dtsi b/arch/arm64/boot/dts/synaptics/as370.dtsi
> new file mode 100644
> index 000000000000..20f3d658c566
> --- /dev/null
> +++ b/arch/arm64/boot/dts/synaptics/as370.dtsi
> @@ -0,0 +1,177 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2018 Synaptics Incorporated
> + *
> + * Author: Jisheng Zhang <[email protected]>
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + compatible = "syna,as370";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + serial0 = &uart0;
This normally goes in the board file. All boards will use this?
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + compatible = "arm,cortex-a53", "arm,armv8";
> + device_type = "cpu";
> + reg = <0x0>;
> + enable-method = "psci";
> + next-level-cache = <&l2>;
> + cpu-idle-states = <&CPU_SLEEP_0>;
> + };
> +
> + cpu1: cpu@1 {
> + compatible = "arm,cortex-a53", "arm,armv8";
> + device_type = "cpu";
> + reg = <0x1>;
> + enable-method = "psci";
> + next-level-cache = <&l2>;
> + cpu-idle-states = <&CPU_SLEEP_0>;
> + };
> +
> + cpu2: cpu@2 {
> + compatible = "arm,cortex-a53", "arm,armv8";
> + device_type = "cpu";
> + reg = <0x2>;
> + enable-method = "psci";
> + next-level-cache = <&l2>;
> + cpu-idle-states = <&CPU_SLEEP_0>;
> + };
> +
> + cpu3: cpu@3 {
> + compatible = "arm,cortex-a53", "arm,armv8";
> + device_type = "cpu";
> + reg = <0x3>;
> + enable-method = "psci";
> + next-level-cache = <&l2>;
> + cpu-idle-states = <&CPU_SLEEP_0>;
> + };
> +
> + l2: cache {
> + compatible = "cache";
Why do you need this node? Doesn't define
> + };
> +
> + idle-states {
> + entry-method = "psci";
> + CPU_SLEEP_0: cpu-sleep-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <75>;
> + exit-latency-us = <155>;
> + min-residency-us = <1000>;
> + };
> + };
> + };
> +
> + osc: osc {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&cpu0>,
> + <&cpu1>,
> + <&cpu2>,
> + <&cpu3>;
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + soc@f7000000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0xf7000000 0x1000000>;
> +
> + gic: interrupt-controller@901000 {
> + compatible = "arm,gic-400";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x901000 0x1000>,
> + <0x902000 0x2000>,
> + <0x904000 0x2000>,
> + <0x906000 0x2000>;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + apb@e80000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0xe80000 0x10000>;
> +
> + uart0: uart@0c00 {
serial@c00
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0c00 0x100>;
> + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + gpio0: gpio@1800 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0x1800 0x400>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + porta: gpio-port@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + snps,nr-gpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + gpio1: gpio@2000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0x2000 0x400>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + portb: gpio-port@1 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + snps,nr-gpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> + };
> + };
> +};
> --
> 2.18.0
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to [email protected]
> More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Rob
On Fri, 20 Jul 2018 09:15:29 -0600 Rob Herring wrote:
> On Fri, Jul 13, 2018 at 05:24:57PM +0800, Jisheng Zhang wrote:
> > The AS370 SoC is a new derivative of the berlin family. The only
> > difference is the SoC isn't named as berlin*.
>
> So is it a derivative or just rebranded?
A derivative new generation SoC.
>
> > Signed-off-by: Jisheng Zhang <[email protected]>
> > ---
> > Documentation/devicetree/bindings/arm/syna.txt | 6 +++++-
> > 1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/syna.txt b/Documentation/devicetree/bindings/arm/syna.txt
> > index 3bab18409b7a..3ba1d7b5ee74 100644
> > --- a/Documentation/devicetree/bindings/arm/syna.txt
> > +++ b/Documentation/devicetree/bindings/arm/syna.txt
> > @@ -1,4 +1,4 @@
> > -Marvell Berlin SoC Family Device Tree Bindings
> > +Synaptics SoC Device Tree Bindings
>
> Perhaps some note about what has happened here. Otherwise it looks
> strange having "Marvell Berlin" in the document when the title says
> Synaptics SoC.
Good idea. will do in v2
>
> > ---------------------------------------------------------------
> >
> > Work in progress statement:
> > @@ -13,6 +13,10 @@ stable binding/ABI.
> >
> > ---------------------------------------------------------------
> >
> > +Boards with the Synaptics AS370 SoC shall have the following properties:
> > + Required root node property:
> > + compatible: "syna,as370"
> > +
> > Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
> > shall have the following properties:
> >
> > --
> > 2.18.0
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe devicetree" in
> > the body of a message to [email protected]
> > More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Rob,
On Fri, 20 Jul 2018 09:21:17 -0600 Rob Herring wrote:
> On Fri, Jul 13, 2018 at 05:26:26PM +0800, Jisheng Zhang wrote:
> > Add initial dtsi file to support Synaptics AS370 SoC with quad
> > Cortex-A53 CPUs.
> >
> > Signed-off-by: Jisheng Zhang <[email protected]>
> > ---
> > arch/arm64/boot/dts/synaptics/as370.dtsi | 177 +++++++++++++++++++++++
> > 1 file changed, 177 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/synaptics/as370.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/synaptics/as370.dtsi b/arch/arm64/boot/dts/synaptics/as370.dtsi
> > new file mode 100644
> > index 000000000000..20f3d658c566
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/synaptics/as370.dtsi
> > @@ -0,0 +1,177 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2018 Synaptics Incorporated
> > + *
> > + * Author: Jisheng Zhang <[email protected]>
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > + compatible = "syna,as370";
> > + interrupt-parent = <&gic>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + aliases {
> > + serial0 = &uart0;
>
> This normally goes in the board file. All boards will use this?
Yes. AFAIK, all boards will use uart0 as the serial console. But I could
move it to the board file.
>
> > + };
> > +
> > + psci {
> > + compatible = "arm,psci-1.0";
> > + method = "smc";
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu0: cpu@0 {
> > + compatible = "arm,cortex-a53", "arm,armv8";
> > + device_type = "cpu";
> > + reg = <0x0>;
> > + enable-method = "psci";
> > + next-level-cache = <&l2>;
> > + cpu-idle-states = <&CPU_SLEEP_0>;
> > + };
> > +
> > + cpu1: cpu@1 {
> > + compatible = "arm,cortex-a53", "arm,armv8";
> > + device_type = "cpu";
> > + reg = <0x1>;
> > + enable-method = "psci";
> > + next-level-cache = <&l2>;
> > + cpu-idle-states = <&CPU_SLEEP_0>;
> > + };
> > +
> > + cpu2: cpu@2 {
> > + compatible = "arm,cortex-a53", "arm,armv8";
> > + device_type = "cpu";
> > + reg = <0x2>;
> > + enable-method = "psci";
> > + next-level-cache = <&l2>;
> > + cpu-idle-states = <&CPU_SLEEP_0>;
> > + };
> > +
> > + cpu3: cpu@3 {
> > + compatible = "arm,cortex-a53", "arm,armv8";
> > + device_type = "cpu";
> > + reg = <0x3>;
> > + enable-method = "psci";
> > + next-level-cache = <&l2>;
> > + cpu-idle-states = <&CPU_SLEEP_0>;
> > + };
> > +
> > + l2: cache {
> > + compatible = "cache";
>
> Why do you need this node? Doesn't define
If the l2 node is missing, I will get below warning:
[ 1.364795] Unable to detect cache hierarchy for CPU 0
reported by drivers/base/cacheinfo.c
>
> > + };
> > +
> > + idle-states {
> > + entry-method = "psci";
> > + CPU_SLEEP_0: cpu-sleep-0 {
> > + compatible = "arm,idle-state";
> > + local-timer-stop;
> > + arm,psci-suspend-param = <0x0010000>;
> > + entry-latency-us = <75>;
> > + exit-latency-us = <155>;
> > + min-residency-us = <1000>;
> > + };
> > + };
> > + };
> > +
> > + osc: osc {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <25000000>;
> > + };
> > +
> > + pmu {
> > + compatible = "arm,cortex-a53-pmu";
> > + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-affinity = <&cpu0>,
> > + <&cpu1>,
> > + <&cpu2>,
> > + <&cpu3>;
> > + };
> > +
> > + timer {
> > + compatible = "arm,armv8-timer";
> > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> > + };
> > +
> > + soc@f7000000 {
> > + compatible = "simple-bus";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0 0 0xf7000000 0x1000000>;
> > +
> > + gic: interrupt-controller@901000 {
> > + compatible = "arm,gic-400";
> > + #interrupt-cells = <3>;
> > + interrupt-controller;
> > + reg = <0x901000 0x1000>,
> > + <0x902000 0x2000>,
> > + <0x904000 0x2000>,
> > + <0x906000 0x2000>;
> > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> > + };
> > +
> > + apb@e80000 {
> > + compatible = "simple-bus";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0 0xe80000 0x10000>;
> > +
> > + uart0: uart@0c00 {
>
> serial@c00
will do in v2
Thanks a lot