Add support for building flattened DT files from DT source files under
arch/riscv/boot/dts. Follow existing kernel precedent from other SoC
architectures.
Start by adding initial support for the SiFive FU540 SoC, and the
development board that uses it, the SiFive HiFive Unleashed A00.
Applies on v4.20-rc6.
- Paul
Paul Walmsley (7):
arch: riscv: add support for building DTB files from DT source data
dt-bindings: riscv: sifive: add documentation for the SiFive FU540
dt-bindings: riscv: cpus: add E51 cores to the list of documented CPUs
dt-bindings: riscv: cpus: add U54 cores to the list of documented CPUs
riscv: dts: add initial support for the SiFive FU540-C000 SoC
dt-binding: riscv: sifive: add documentation for FU540-based boards
riscv: dts: add initial board data for the SiFive HiFive Unleashed
.../devicetree/bindings/riscv/cpus.txt | 6 +-
.../bindings/riscv/sifive/fu540.txt | 24 +++
MAINTAINERS | 9 +
arch/riscv/Kconfig | 2 +
arch/riscv/Kconfig.platforms | 8 +
arch/riscv/boot/dts/Makefile | 2 +
arch/riscv/boot/dts/sifive/Makefile | 4 +
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 182 ++++++++++++++++++
.../dts/sifive/hifive-unleashed-a00-fu540.dts | 39 ++++
9 files changed, 274 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/riscv/sifive/fu540.txt
create mode 100644 arch/riscv/Kconfig.platforms
create mode 100644 arch/riscv/boot/dts/Makefile
create mode 100644 arch/riscv/boot/dts/sifive/Makefile
create mode 100644 arch/riscv/boot/dts/sifive/fu540-c000.dtsi
create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts
--
2.20.0
Add initial board data for the SiFive HiFive Unleashed A00.
Currently the data populated in this DT file describes the board
DRAM configuration and the external clock sources that supply the
PRCI.
Cc: Rob Herring <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
Cc: Albert Ou <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Paul Walmsley <[email protected]>
Signed-off-by: Paul Walmsley <[email protected]>
---
arch/riscv/boot/dts/Makefile | 2 +
arch/riscv/boot/dts/sifive/Makefile | 4 ++
.../dts/sifive/hifive-unleashed-a00-fu540.dts | 39 +++++++++++++++++++
3 files changed, 45 insertions(+)
create mode 100644 arch/riscv/boot/dts/Makefile
create mode 100644 arch/riscv/boot/dts/sifive/Makefile
create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
new file mode 100644
index 000000000000..dcc3ada78455
--- /dev/null
+++ b/arch/riscv/boot/dts/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+subdir-y += sifive
diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile
new file mode 100644
index 000000000000..e120ccf5649c
--- /dev/null
+++ b/arch/riscv/boot/dts/sifive/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_SIFIVE) += hifive-unleashed-a00-fu540.dtb
+
+
diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts
new file mode 100644
index 000000000000..0c6afabe69e3
--- /dev/null
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-License-Identifier: GPL-2.0-or-later
+/* Copyright (c) 2018 SiFive, Inc */
+/* See the file LICENSE for further information */
+
+/dts-v1/;
+
+#include "fu540-c000.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "SiFive HiFive Unleashed A00 (FU540-C000)"
+ compatible = "sifive,hifive-unleashed-a00-fu540",
+ "sifive,hifive-unleashed-fu540";
+
+ chosen {
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x1f 0x80000000>;
+ };
+
+ soc {
+ hfclk: hfclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <33333333>;
+ clock-output-names = "hfclk";
+ };
+ rtcclk: rtcclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1000000>;
+ clock-output-names = "rtcclk";
+ };
+ };
+};
--
2.20.0
Add DT binding documentation for boards based on the SiFive FU540 SoC.
The first board, the HiFive Unleashed A00 (FU540), is described here:
https://static.dev.sifive.com/HiFive-Unleashed-Getting-Started-Guide-v1p1.pdf
Cc: Rob Herring <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
Cc: Albert Ou <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Paul Walmsley <[email protected]>
Signed-off-by: Paul Walmsley <[email protected]>
---
.../devicetree/bindings/riscv/sifive/fu540.txt | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/sifive/fu540.txt b/Documentation/devicetree/bindings/riscv/sifive/fu540.txt
index b5cf2b9f9a75..20119cc54964 100644
--- a/Documentation/devicetree/bindings/riscv/sifive/fu540.txt
+++ b/Documentation/devicetree/bindings/riscv/sifive/fu540.txt
@@ -12,3 +12,13 @@ compatible-string values:
- Freedom Unleashed 540 rev. C000, or "FU540"
compatible = "sifive,fu540-c000", "sifive,fu540"
+
+Boards
+------
+
+Boards based on the FU540 SoC should specify the following
+compatible-string values:
+
+- HiFive-Unleashed rev. A00 board
+ compatible = "sifive,hifive-unleashed-a00-fu540",
+ "sifive,hifive-unleashed-fu540"
--
2.20.0
Add DT binding documentation for the SiFive FU540 SoC. This
SoC is documented at:
https://static.dev.sifive.com/FU540-C000-v1.0.pdf
This file is originally based on
Documentation/devicetree/bindings/arm/ti/k3.txt.
Cc: Rob Herring <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
Cc: Albert Ou <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Paul Walmsley <[email protected]>
Signed-off-by: Paul Walmsley <[email protected]>
---
.../devicetree/bindings/riscv/sifive/fu540.txt | 14 ++++++++++++++
MAINTAINERS | 9 +++++++++
2 files changed, 23 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/sifive/fu540.txt
diff --git a/Documentation/devicetree/bindings/riscv/sifive/fu540.txt b/Documentation/devicetree/bindings/riscv/sifive/fu540.txt
new file mode 100644
index 000000000000..b5cf2b9f9a75
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/sifive/fu540.txt
@@ -0,0 +1,14 @@
+SiFive FU540 SoC architecture device tree bindings
+--------------------------------------------------
+
+Platforms based on the SiFive FU540 RISC-V SoC should follow the
+scheme described below:
+
+SoCs
+----
+
+Each device tree root node must specify one of the following
+compatible-string values:
+
+- Freedom Unleashed 540 rev. C000, or "FU540"
+ compatible = "sifive,fu540-c000", "sifive,fu540"
diff --git a/MAINTAINERS b/MAINTAINERS
index 8119141a926f..dee555ceb175 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13626,6 +13626,15 @@ S: Supported
K: sifive
N: sifive
+SIFIVE FU540 SYSTEM-ON-CHIP
+M: Paul Walmsley <[email protected]>
+M: Palmer Dabbelt <[email protected]>
+L: [email protected]
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/pjw/sifive.git
+S: Supported
+K: fu540
+N: fu540
+
SILEAD TOUCHSCREEN DRIVER
M: Hans de Goede <[email protected]>
L: [email protected]
--
2.20.0
Similar to what's implemented for ARM64, add support for building
DTB files from DT source data for RISC-V boards.
This patch starts with the infrastructure needed for SiFive boards.
Cc: Palmer Dabbelt <[email protected]>
Cc: Albert Ou <[email protected]>
Signed-off-by: Paul Walmsley <[email protected]>
Signed-off-by: Paul Walmsley <[email protected]>
---
arch/riscv/Kconfig | 2 ++
arch/riscv/Kconfig.platforms | 8 ++++++++
2 files changed, 10 insertions(+)
create mode 100644 arch/riscv/Kconfig.platforms
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 55da93f4e818..dc9f1afa4ad9 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -121,6 +121,8 @@ config ARCH_RV64I
endchoice
+source "arch/riscv/Kconfig.platforms"
+
# We must be able to map all physical memory into the kernel, but the compiler
# is still a bit more efficient when generating code if it's setup in a manner
# such that it can only map 2GiB of memory.
diff --git a/arch/riscv/Kconfig.platforms b/arch/riscv/Kconfig.platforms
new file mode 100644
index 000000000000..bd3d2642bcff
--- /dev/null
+++ b/arch/riscv/Kconfig.platforms
@@ -0,0 +1,8 @@
+menu "Platform selection"
+
+config ARCH_SIFIVE
+ bool "SiFive platforms"
+ help
+ This enables direct support for SiFive SoC platform hardware.
+
+endmenu
--
2.20.0
Add initial support for the SiFive FU540-C000 SoC. This is a 28nm SoC
based around the SiFive U54-MC core complex and a TileLink
interconnect.
This file is expected to grow considerably as more device drivers are
added to the kernel.
Cc: Rob Herring <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
Cc: Albert Ou <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Paul Walmsley <[email protected]>
Signed-off-by: Paul Walmsley <[email protected]>
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 182 +++++++++++++++++++++
1 file changed, 182 insertions(+)
create mode 100644 arch/riscv/boot/dts/sifive/fu540-c000.dtsi
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
new file mode 100644
index 000000000000..0ef314cf17b6
--- /dev/null
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-License-Identifier: GPL-2.0-or-later
+/* Copyright (c) 2018 SiFive, Inc */
+/* See the file LICENSE for further information */
+
+/dts-v1/;
+
+#include <linux/clk/sifive-fu540-prci.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "sifive,fu540-c000", "sifive,fu540";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <1000000>;
+ cpu0: cpu@0 {
+ clock-frequency = <0>;
+ compatible = "sifive,e51", "sifive,rocket0";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ reg = <0>;
+ riscv,isa = "rv64imac";
+ status = "okay";
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu1: cpu@1 {
+ clock-frequency = <0>;
+ compatible = "sifive,u54-mc", "sifive,rocket0";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <1>;
+ riscv,isa = "rv64imafdc";
+ status = "okay";
+ tlb-split;
+ cpu1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu2: cpu@2 {
+ clock-frequency = <0>;
+ compatible = "sifive,u54-mc", "sifive,rocket0";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <2>;
+ riscv,isa = "rv64imafdc";
+ status = "okay";
+ tlb-split;
+ cpu2_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu3: cpu@3 {
+ clock-frequency = <0>;
+ compatible = "sifive,u54-mc", "sifive,rocket0";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <3>;
+ riscv,isa = "rv64imafdc";
+ status = "okay";
+ tlb-split;
+ cpu3_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu4: cpu@4 {
+ clock-frequency = <0>;
+ compatible = "sifive,u54-mc", "sifive,rocket0";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <4>;
+ riscv,isa = "rv64imafdc";
+ status = "okay";
+ tlb-split;
+ cpu4_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
+ ranges;
+ prci: prci@10000000 {
+ compatible = "sifive,fu540-c000-prci";
+ reg = <0x0 0x10000000 0x0 0x1000>;
+ clocks = <&hfclk>, <&rtcclk>;
+ #clock-cells = <1>;
+ };
+ uart0: serial@10010000 {
+ compatible = "sifive,fu540-c000-uart", "sifive,uart0";
+ interrupt-parent = <&plic0>;
+ interrupts = <4>;
+ reg = <0x0 0x10010000 0x0 0x1000>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ };
+ uart1: serial@10011000 {
+ compatible = "sifive,fu540-c000-uart", "sifive,uart0";
+ interrupt-parent = <&plic0>;
+ interrupts = <5>;
+ reg = <0x0 0x10011000 0x0 0x1000>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ };
+ plic0: interrupt-controller@c000000 {
+ #interrupt-cells = <1>;
+ compatible = "riscv,plic0";
+ interrupt-controller;
+ interrupts-extended = <
+ &cpu0_intc 11
+ &cpu1_intc 11 &cpu1_intc 9
+ &cpu2_intc 11 &cpu2_intc 9
+ &cpu3_intc 11 &cpu3_intc 9
+ &cpu4_intc 11 &cpu4_intc 9>;
+ reg = <0x0 0xc000000 0x0 0x4000000>;
+ };
+ };
+};
--
2.20.0
Add compatible strings for the SiFive U54 family of CPU cores to the
RISC-V CPU compatible string documentation. The U54 CPU cores are
described in:
https://static.dev.sifive.com/FU540-C000-v1.0.pdf
Cc: Rob Herring <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
Cc: Albert Ou <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Paul Walmsley <[email protected]>
Signed-off-by: Paul Walmsley <[email protected]>
---
Documentation/devicetree/bindings/riscv/cpus.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt
index fb9d4f86f41f..d8d99b6b5386 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.txt
+++ b/Documentation/devicetree/bindings/riscv/cpus.txt
@@ -70,7 +70,8 @@ described below.
Value type: <stringlist>
Definition: must contain "riscv", may contain one or
more of "sifive,rocket0", "sifive,e51",
- "sifive,e5"
+ "sifive,e5", "sifive,u54-mc", "sifive,u54",
+ "sifive,u5"
- mmu-type:
Usage: optional
Value type: <string>
--
2.20.0
Add compatible strings for the SiFive E51 family of CPU cores to the
RISC-V CPU compatible string documentation. The E51 CPU core is
described in:
https://static.dev.sifive.com/FU540-C000-v1.0.pdf
Cc: Rob Herring <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
Cc: Albert Ou <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Paul Walmsley <[email protected]>
Signed-off-by: Paul Walmsley <[email protected]>
---
Documentation/devicetree/bindings/riscv/cpus.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt
index adf7b7af5dc3..fb9d4f86f41f 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.txt
+++ b/Documentation/devicetree/bindings/riscv/cpus.txt
@@ -68,8 +68,9 @@ described below.
- compatible:
Usage: required
Value type: <stringlist>
- Definition: must contain "riscv", may contain one of
- "sifive,rocket0"
+ Definition: must contain "riscv", may contain one or
+ more of "sifive,rocket0", "sifive,e51",
+ "sifive,e5"
- mmu-type:
Usage: optional
Value type: <string>
--
2.20.0
Hi Paul,
I love your patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on v4.20-rc6 next-20181214]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Paul-Walmsley/arch-riscv-add-DT-file-support-starting-with-the-SiFive-HiFive-U/20181216-103926
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: riscv-tinyconfig (attached as .config)
compiler: riscv64-linux-gcc (GCC) 8.1.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=8.1.0 make.cross ARCH=riscv
Note: the linux-review/Paul-Walmsley/arch-riscv-add-DT-file-support-starting-with-the-SiFive-HiFive-U/20181216-103926 HEAD bd72c6c6fec694776fceb1c4f4cf7c6415a6e8e3 builds fine.
It only hurts bisectibility.
All errors (new ones prefixed by >>):
>> scripts/Makefile.build:42: arch/riscv/boot/dts/Makefile: No such file or directory
>> make[2]: *** No rule to make target 'arch/riscv/boot/dts/Makefile'.
make[2]: Failed to remake makefile 'arch/riscv/boot/dts/Makefile'.
vim +42 scripts/Makefile.build
20a468b51 Sam Ravnborg 2006-01-22 38
2a6914703 Sam Ravnborg 2005-07-25 39 # The filename Kbuild has precedence over Makefile
db8c1a7b2 Sam Ravnborg 2005-07-27 40 kbuild-dir := $(if $(filter /%,$(src)),$(src),$(srctree)/$(src))
0c53c8e6e Sam Ravnborg 2007-10-14 41 kbuild-file := $(if $(wildcard $(kbuild-dir)/Kbuild),$(kbuild-dir)/Kbuild,$(kbuild-dir)/Makefile)
0c53c8e6e Sam Ravnborg 2007-10-14 @42 include $(kbuild-file)
^1da177e4 Linus Torvalds 2005-04-16 43
:::::: The code at line 42 was first introduced by commit
:::::: 0c53c8e6eb456cde30f2305421c605713856abc8 kbuild: check for wrong use of CFLAGS
:::::: TO: Sam Ravnborg <sam@neptun.(none)>
:::::: CC: Sam Ravnborg <sam@neptun.(none)>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.. along with the PRCI patches which are under review.
Will repost these such that the files that depend on the new clock
headers are at the end of this series. Then we can send those last two
patches after the clock merge in the merge window, assuming the PRCI
patches make it.
- Paul
On 12/14/18 9:21 PM, Paul Walmsley wrote:
> Applies on v4.20-rc6.
On Fri, Dec 14, 2018 at 09:21:49PM -0800, Paul Walmsley wrote:
> Add DT binding documentation for the SiFive FU540 SoC. This
> SoC is documented at:
>
> https://static.dev.sifive.com/FU540-C000-v1.0.pdf
>
> This file is originally based on
> Documentation/devicetree/bindings/arm/ti/k3.txt.
>
> Cc: Rob Herring <[email protected]>
> Cc: Mark Rutland <[email protected]>
> Cc: Palmer Dabbelt <[email protected]>
> Cc: Albert Ou <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Signed-off-by: Paul Walmsley <[email protected]>
> Signed-off-by: Paul Walmsley <[email protected]>
> ---
> .../devicetree/bindings/riscv/sifive/fu540.txt | 14 ++++++++++++++
> MAINTAINERS | 9 +++++++++
> 2 files changed, 23 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/riscv/sifive/fu540.txt
Reviewed-by: Rob Herring <[email protected]>
However, with 4.21 we're starting to use json-schema and top-level
SoC/board bindings. Not requiring it yet, but feel free to convert to
that if you want. Then we don't have to do it later.
Rob
On Fri, Dec 14, 2018 at 09:21:50PM -0800, Paul Walmsley wrote:
> Add compatible strings for the SiFive E51 family of CPU cores to the
> RISC-V CPU compatible string documentation. The E51 CPU core is
> described in:
>
> https://static.dev.sifive.com/FU540-C000-v1.0.pdf
>
> Cc: Rob Herring <[email protected]>
> Cc: Mark Rutland <[email protected]>
> Cc: Palmer Dabbelt <[email protected]>
> Cc: Albert Ou <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Signed-off-by: Paul Walmsley <[email protected]>
> Signed-off-by: Paul Walmsley <[email protected]>
> ---
> Documentation/devicetree/bindings/riscv/cpus.txt | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt
> index adf7b7af5dc3..fb9d4f86f41f 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.txt
> +++ b/Documentation/devicetree/bindings/riscv/cpus.txt
> @@ -68,8 +68,9 @@ described below.
> - compatible:
> Usage: required
> Value type: <stringlist>
> - Definition: must contain "riscv", may contain one of
> - "sifive,rocket0"
> + Definition: must contain "riscv", may contain one or
> + more of "sifive,rocket0", "sifive,e51",
> + "sifive,e5"
I can't really tell what are valid combinations from this. It reads that
I could list every string here and that would be valid. It is basically
'riscv' plus any other combinations of strings.
Rob
On Fri, Dec 14, 2018 at 09:21:54PM -0800, Paul Walmsley wrote:
> Add initial board data for the SiFive HiFive Unleashed A00.
>
> Currently the data populated in this DT file describes the board
> DRAM configuration and the external clock sources that supply the
> PRCI.
>
> Cc: Rob Herring <[email protected]>
> Cc: Mark Rutland <[email protected]>
> Cc: Palmer Dabbelt <[email protected]>
> Cc: Albert Ou <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Signed-off-by: Paul Walmsley <[email protected]>
> Signed-off-by: Paul Walmsley <[email protected]>
> ---
> arch/riscv/boot/dts/Makefile | 2 +
> arch/riscv/boot/dts/sifive/Makefile | 4 ++
> .../dts/sifive/hifive-unleashed-a00-fu540.dts | 39 +++++++++++++++++++
> 3 files changed, 45 insertions(+)
> create mode 100644 arch/riscv/boot/dts/Makefile
> create mode 100644 arch/riscv/boot/dts/sifive/Makefile
> create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> new file mode 100644
> index 000000000000..dcc3ada78455
> --- /dev/null
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +subdir-y += sifive
> diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile
> new file mode 100644
> index 000000000000..e120ccf5649c
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sifive/Makefile
> @@ -0,0 +1,4 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_SIFIVE) += hifive-unleashed-a00-fu540.dtb
> +
> +
> diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts
> new file mode 100644
> index 000000000000..0c6afabe69e3
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts
> @@ -0,0 +1,39 @@
> +// SPDX-License-Identifier: Apache-2.0
> +// SPDX-License-Identifier: GPL-2.0-or-later
This should be a single line with: (Apache-2.0 OR GPL-2.0+)
> +/* Copyright (c) 2018 SiFive, Inc */
> +/* See the file LICENSE for further information */
> +
> +/dts-v1/;
> +
> +#include "fu540-c000.dtsi"
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + model = "SiFive HiFive Unleashed A00 (FU540-C000)"
> + compatible = "sifive,hifive-unleashed-a00-fu540",
> + "sifive,hifive-unleashed-fu540";
SoC compatible should be here too.
> +
> + chosen {
> + };
> +
> + memory@80000000 {
> + device_type = "memory";
> + reg = <0x0 0x80000000 0x1f 0x80000000>;
> + };
> +
> + soc {
> + hfclk: hfclk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <33333333>;
> + clock-output-names = "hfclk";
> + };
> + rtcclk: rtcclk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <1000000>;
> + clock-output-names = "rtcclk";
> + };
Are these the clock inputs to the SoC or dummy clocks until you write a
proper clock driver? If the former, they should be at the top level.
Rob
On Fri, 14 Dec 2018 21:21:53 -0800, Paul Walmsley wrote:
> Add DT binding documentation for boards based on the SiFive FU540 SoC.
> The first board, the HiFive Unleashed A00 (FU540), is described here:
>
> https://static.dev.sifive.com/HiFive-Unleashed-Getting-Started-Guide-v1p1.pdf
>
> Cc: Rob Herring <[email protected]>
> Cc: Mark Rutland <[email protected]>
> Cc: Palmer Dabbelt <[email protected]>
> Cc: Albert Ou <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Signed-off-by: Paul Walmsley <[email protected]>
> Signed-off-by: Paul Walmsley <[email protected]>
> ---
> .../devicetree/bindings/riscv/sifive/fu540.txt | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
Reviewed-by: Rob Herring <[email protected]>
On Thu, 20 Dec 2018 13:01:41 PST (-0800), [email protected] wrote:
> On Fri, Dec 14, 2018 at 09:21:50PM -0800, Paul Walmsley wrote:
>> Add compatible strings for the SiFive E51 family of CPU cores to the
>> RISC-V CPU compatible string documentation. The E51 CPU core is
>> described in:
>>
>> https://static.dev.sifive.com/FU540-C000-v1.0.pdf
>>
>> Cc: Rob Herring <[email protected]>
>> Cc: Mark Rutland <[email protected]>
>> Cc: Palmer Dabbelt <[email protected]>
>> Cc: Albert Ou <[email protected]>
>> Cc: [email protected]
>> Cc: [email protected]
>> Cc: [email protected]
>> Signed-off-by: Paul Walmsley <[email protected]>
>> Signed-off-by: Paul Walmsley <[email protected]>
>> ---
>> Documentation/devicetree/bindings/riscv/cpus.txt | 5 +++--
>> 1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt
>> index adf7b7af5dc3..fb9d4f86f41f 100644
>> --- a/Documentation/devicetree/bindings/riscv/cpus.txt
>> +++ b/Documentation/devicetree/bindings/riscv/cpus.txt
>> @@ -68,8 +68,9 @@ described below.
>> - compatible:
>> Usage: required
>> Value type: <stringlist>
>> - Definition: must contain "riscv", may contain one of
>> - "sifive,rocket0"
>> + Definition: must contain "riscv", may contain one or
>> + more of "sifive,rocket0", "sifive,e51",
>> + "sifive,e5"
>
> I can't really tell what are valid combinations from this. It reads that
> I could list every string here and that would be valid. It is basically
> 'riscv' plus any other combinations of strings.
I think that's actually the correct interpretation: if it's a RISC-V CPU then
it must have "riscv" listed in compatible, but it can also be anything else.
There's some concrete examples here (a "sifive,e51" is a type of "riscv"), but
I don't think it's realistic to count on us being able to enumerate all RISC-V
implementations here.
On Fri, Jan 4, 2019 at 4:46 PM Palmer Dabbelt <[email protected]> wrote:
>
> On Thu, 20 Dec 2018 13:01:41 PST (-0800), [email protected] wrote:
> > On Fri, Dec 14, 2018 at 09:21:50PM -0800, Paul Walmsley wrote:
> >> Add compatible strings for the SiFive E51 family of CPU cores to the
> >> RISC-V CPU compatible string documentation. The E51 CPU core is
> >> described in:
> >>
> >> https://static.dev.sifive.com/FU540-C000-v1.0.pdf
> >>
> >> Cc: Rob Herring <[email protected]>
> >> Cc: Mark Rutland <[email protected]>
> >> Cc: Palmer Dabbelt <[email protected]>
> >> Cc: Albert Ou <[email protected]>
> >> Cc: [email protected]
> >> Cc: [email protected]
> >> Cc: [email protected]
> >> Signed-off-by: Paul Walmsley <[email protected]>
> >> Signed-off-by: Paul Walmsley <[email protected]>
> >> ---
> >> Documentation/devicetree/bindings/riscv/cpus.txt | 5 +++--
> >> 1 file changed, 3 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt
> >> index adf7b7af5dc3..fb9d4f86f41f 100644
> >> --- a/Documentation/devicetree/bindings/riscv/cpus.txt
> >> +++ b/Documentation/devicetree/bindings/riscv/cpus.txt
> >> @@ -68,8 +68,9 @@ described below.
> >> - compatible:
> >> Usage: required
> >> Value type: <stringlist>
> >> - Definition: must contain "riscv", may contain one of
> >> - "sifive,rocket0"
> >> + Definition: must contain "riscv", may contain one or
> >> + more of "sifive,rocket0", "sifive,e51",
> >> + "sifive,e5"
> >
> > I can't really tell what are valid combinations from this. It reads that
> > I could list every string here and that would be valid. It is basically
> > 'riscv' plus any other combinations of strings.
>
> I think that's actually the correct interpretation: if it's a RISC-V CPU then
> it must have "riscv" listed in compatible, but it can also be anything else.
But is '"sifive,rocket0", "sifive,e51", "sifive,e5", "riscv"' valid?
What about '"sifive,rocket0", "sifive,e5", "riscv"'?
If they are, is there really any value in specifying all of them or
different variations? I'd suggest keeping things simple because
writing a json-schema gets messy when there's arbitrary combinations
of compatible values.
> There's some concrete examples here (a "sifive,e51" is a type of "riscv"), but
> I don't think it's realistic to count on us being able to enumerate all RISC-V
> implementations here.
I think you'll find that "riscv" will become pointless as it is not
specific enough to mean anything. It would be like having "arm" as a
compatible on Arm based systems.
OTOH, you only really need to enumerate what you can't discover. For
example, how are optional features (SIMD inst a common example)
discovered? On Arm, we generally just have the CPU model in the
compatible, but it's generally not even used because that, cpu
revision, instruction set features, etc. are all discoverable.
Rob
On Fri, Dec 14, 2018 at 09:21:52PM -0800, Paul Walmsley wrote:
> Add initial support for the SiFive FU540-C000 SoC. This is a 28nm SoC
> based around the SiFive U54-MC core complex and a TileLink
> interconnect.
>
> This file is expected to grow considerably as more device drivers are
> added to the kernel.
>
> Cc: Rob Herring <[email protected]>
> Cc: Mark Rutland <[email protected]>
> Cc: Palmer Dabbelt <[email protected]>
> Cc: Albert Ou <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Signed-off-by: Paul Walmsley <[email protected]>
> Signed-off-by: Paul Walmsley <[email protected]>
> ---
> arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 182 +++++++++++++++++++++
> 1 file changed, 182 insertions(+)
> create mode 100644 arch/riscv/boot/dts/sifive/fu540-c000.dtsi
>
> diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> new file mode 100644
> index 000000000000..0ef314cf17b6
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <1000000>;
> + cpu0: cpu@0 {
> + clock-frequency = <0>;
> + compatible = "sifive,e51", "sifive,rocket0";
Looks like you forgot the currently required "riscv" compatible here and
below.
But perhaps it's the binding and arch code that should be revised
instead (e.g. as per your discussion with Rob elsewhere in this thread).
Johan
On Thu, 20 Dec 2018, Rob Herring wrote:
> On Fri, Dec 14, 2018 at 09:21:54PM -0800, Paul Walmsley wrote:
> > Add initial board data for the SiFive HiFive Unleashed A00.
> >
> > Currently the data populated in this DT file describes the board
> > DRAM configuration and the external clock sources that supply the
> > PRCI.
...
> > diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts
> > new file mode 100644
> > index 000000000000..0c6afabe69e3
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts
> > @@ -0,0 +1,39 @@
> > +// SPDX-License-Identifier: Apache-2.0
> > +// SPDX-License-Identifier: GPL-2.0-or-later
>
> This should be a single line with: (Apache-2.0 OR GPL-2.0+)
Done.
> > + model = "SiFive HiFive Unleashed A00 (FU540-C000)"
> > + compatible = "sifive,hifive-unleashed-a00-fu540",
> > + "sifive,hifive-unleashed-fu540";
>
> SoC compatible should be here too.
Done.
> > + soc {
> > + hfclk: hfclk {
> > + #clock-cells = <0>;
> > + compatible = "fixed-clock";
> > + clock-frequency = <33333333>;
> > + clock-output-names = "hfclk";
> > + };
> > + rtcclk: rtcclk {
> > + #clock-cells = <0>;
> > + compatible = "fixed-clock";
> > + clock-frequency = <1000000>;
> > + clock-output-names = "rtcclk";
> > + };
>
> Are these the clock inputs to the SoC or dummy clocks until you write a
> proper clock driver? If the former, they should be at the top level.
Done.
Thanks for your comments; Will send an updated patch set.
- Paul