From: Yazen Ghannam <[email protected]>
The AMD64 EDAC module current hardcodes the EDAC channel layer size
(count) to two. Future AMD systems may have more channels than this.
Set the EDAC channel layer size equal to the maximum number of channels
possible for the system. On Family 17h and later, this is set in the
num_umcs variable. Older systems will continue to use two as the
default.
Signed-off-by: Yazen Ghannam <[email protected]>
---
drivers/edac/amd64_edac.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index b7617fad282c..4c0239aeff2f 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -3357,8 +3357,14 @@ static int init_one_instance(unsigned int nid)
* Always allocate two channels since we can have setups with DIMMs on
* only one channel. Also, this simplifies handling later for the price
* of a couple of KBs tops.
+ *
+ * On Fam17h+, the number of controllers may be greater than two. So set
+ * the size equal to the maximum number of UMCs.
*/
- layers[1].size = 2;
+ if (pvt->fam >= 0x17)
+ layers[1].size = num_umcs;
+ else
+ layers[1].size = 2;
layers[1].is_virt_csrow = false;
mci = edac_mc_alloc(nid, ARRAY_SIZE(layers), layers, 0);
--
2.17.1
On Mon, Mar 25, 2019 at 08:33:30PM +0000, Ghannam, Yazen wrote:
> From: Yazen Ghannam <[email protected]>
>
> The AMD64 EDAC module current hardcodes the EDAC channel layer size
> (count) to two. Future AMD systems may have more channels than this.
>
> Set the EDAC channel layer size equal to the maximum number of channels
> possible for the system. On Family 17h and later, this is set in the
> num_umcs variable. Older systems will continue to use two as the
> default.
>
> Signed-off-by: Yazen Ghannam <[email protected]>
> ---
> drivers/edac/amd64_edac.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
Ok, whole pile here:
https://git.kernel.org/pub/scm/linux/kernel/git/bp/bp.git/log/?h=edac-for-5.2-amd64
Please run it to check all is still good.
Thx.
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
> -----Original Message-----
> From: Borislav Petkov <[email protected]>
> Sent: Tuesday, March 26, 2019 10:55 AM
> To: Ghannam, Yazen <[email protected]>
> Cc: [email protected]; [email protected]
> Subject: Re: [PATCH] EDAC/amd64: Use maximum channel count for the EDAC channel layer size
>
> On Mon, Mar 25, 2019 at 08:33:30PM +0000, Ghannam, Yazen wrote:
> > From: Yazen Ghannam <[email protected]>
> >
> > The AMD64 EDAC module current hardcodes the EDAC channel layer size
> > (count) to two. Future AMD systems may have more channels than this.
> >
> > Set the EDAC channel layer size equal to the maximum number of channels
> > possible for the system. On Family 17h and later, this is set in the
> > num_umcs variable. Older systems will continue to use two as the
> > default.
> >
> > Signed-off-by: Yazen Ghannam <[email protected]>
> > ---
> > drivers/edac/amd64_edac.c | 8 +++++++-
> > 1 file changed, 7 insertions(+), 1 deletion(-)
>
> Ok, whole pile here:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/bp/bp.git/log/?h=edac-for-5.2-amd64
>
> Please run it to check all is still good.
>
Just tested on a fully populated system. Everything seems to be okay.
Thanks,
Yazen
On Tue, Mar 26, 2019 at 07:15:29PM +0000, Ghannam, Yazen wrote:
> Just tested on a fully populated system. Everything seems to be okay.
Thanks, queued.
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.