Hello, Alan,
Just following up on the -rcu commit below. I believe that it needs
some adjustment given Peter Zijlstra's addition of "memory" to the x86
non-value-returning atomics, but thought I should double-check.
Thanx, Paul
------------------------------------------------------------------------
commit f68f031d47f42f9fe07d9dee1ced48b2b0b8ae5e
Author: Alan Stern <[email protected]>
Date: Fri Apr 19 13:21:45 2019 -0400
Documentation: atomic_t.txt: Explain ordering provided by smp_mb__{before,after}_atomic()
The description of smp_mb__before_atomic() and smp_mb__after_atomic()
in Documentation/atomic_t.txt is slightly terse and misleading. It
does not clearly state that these barriers only affect the ordering of
other instructions with respect to the atomic operation.
This improves the text to make the actual ordering implications clear,
and also to explain how these barriers differ from a RELEASE or
ACQUIRE ordering.
Signed-off-by: Alan Stern <[email protected]>
Cc: Jonathan Corbet <[email protected]>
Signed-off-by: Paul E. McKenney <[email protected]>
diff --git a/Documentation/atomic_t.txt b/Documentation/atomic_t.txt
index dca3fb0554db..d6e42d8f66de 100644
--- a/Documentation/atomic_t.txt
+++ b/Documentation/atomic_t.txt
@@ -188,7 +188,10 @@ The barriers:
smp_mb__{before,after}_atomic()
only apply to the RMW ops and can be used to augment/upgrade the ordering
-inherent to the used atomic op. These barriers provide a full smp_mb().
+inherent to the used atomic op. Unlike normal smp_mb() barriers, they order
+only the RMW op itself against the instructions preceding the
+smp_mb__before_atomic() or following the smp_mb__after_atomic(); they do
+not order instructions on the other side of the RMW op at all.
These helper barriers exist because architectures have varying implicit
ordering on their SMP atomic primitives. For example our TSO architectures
@@ -212,7 +215,8 @@ Further, while something like:
atomic_dec(&X);
is a 'typical' RELEASE pattern, the barrier is strictly stronger than
-a RELEASE. Similarly for something like:
+a RELEASE because it orders preceding instructions against both the read
+and write parts of the atomic_dec(). Similarly, something like:
atomic_inc(&X);
smp_mb__after_atomic();
@@ -244,7 +248,8 @@ strictly stronger than ACQUIRE. As illustrated:
This should not happen; but a hypothetical atomic_inc_acquire() --
(void)atomic_fetch_inc_acquire() for instance -- would allow the outcome,
-since then:
+because it would not order the W part of the RMW against the following
+WRITE_ONCE. Thus:
P1 P2
On Fri, 3 May 2019, Peter Zijlstra wrote:
> On Fri, May 03, 2019 at 07:53:26AM -0700, Paul E. McKenney wrote:
> > Hello, Alan,
> >
> > Just following up on the -rcu commit below. I believe that it needs
> > some adjustment given Peter Zijlstra's addition of "memory" to the x86
> > non-value-returning atomics, but thought I should double-check.
>
> Right; I should get back to that thread...
The real question, still outstanding, is whether smp_mb__before_atomic
orders anything following the RMW instruction (and similarly, whether
smp_mb__after_atomic orders anything preceding the RMW instruction).
The other changes in that patch (i.e., the second and third hunks) are
okay in any case, because they just flesh out an explanation that is
already present in the text.
Alan
On Fri, May 03, 2019 at 07:53:26AM -0700, Paul E. McKenney wrote:
> Hello, Alan,
>
> Just following up on the -rcu commit below. I believe that it needs
> some adjustment given Peter Zijlstra's addition of "memory" to the x86
> non-value-returning atomics, but thought I should double-check.
Right; I should get back to that thread...
On Fri, May 03, 2019 at 12:19:21PM -0400, Alan Stern wrote:
> On Fri, 3 May 2019, Peter Zijlstra wrote:
>
> > On Fri, May 03, 2019 at 07:53:26AM -0700, Paul E. McKenney wrote:
> > > Hello, Alan,
> > >
> > > Just following up on the -rcu commit below. I believe that it needs
> > > some adjustment given Peter Zijlstra's addition of "memory" to the x86
> > > non-value-returning atomics, but thought I should double-check.
> >
> > Right; I should get back to that thread...
>
> The real question, still outstanding, is whether smp_mb__before_atomic
> orders anything following the RMW instruction (and similarly, whether
> smp_mb__after_atomic orders anything preceding the RMW instruction).
Yes -- that was very much the intent, and only (some) x86 ops and (some)
MIPS config have issues with that.
On Fri, 3 May 2019, Peter Zijlstra wrote:
> On Fri, May 03, 2019 at 12:19:21PM -0400, Alan Stern wrote:
> > On Fri, 3 May 2019, Peter Zijlstra wrote:
> >
> > > On Fri, May 03, 2019 at 07:53:26AM -0700, Paul E. McKenney wrote:
> > > > Hello, Alan,
> > > >
> > > > Just following up on the -rcu commit below. I believe that it needs
> > > > some adjustment given Peter Zijlstra's addition of "memory" to the x86
> > > > non-value-returning atomics, but thought I should double-check.
> > >
> > > Right; I should get back to that thread...
> >
> > The real question, still outstanding, is whether smp_mb__before_atomic
> > orders anything following the RMW instruction (and similarly, whether
> > smp_mb__after_atomic orders anything preceding the RMW instruction).
>
> Yes -- that was very much the intent, and only (some) x86 ops and (some)
> MIPS config have issues with that.
Okay, then I better update the patch.
Alan
The description of smp_mb__before_atomic() and smp_mb__after_atomic()
in Documentation/atomic_t.txt is slightly terse and misleading. It
does not clearly state which other instructions are ordered by these
barriers.
This improves the text to make the actual ordering implications clear,
and also to explain how these barriers differ from a RELEASE or
ACQUIRE ordering.
Signed-off-by: Alan Stern <[email protected]>
CC: Peter Zijlstra <[email protected]>
---
v2: Update the explanation: These barriers do provide order for
accesses on the far side of the atomic RMW operation.
Documentation/atomic_t.txt | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
Index: usb-devel/Documentation/atomic_t.txt
===================================================================
--- usb-devel.orig/Documentation/atomic_t.txt
+++ usb-devel/Documentation/atomic_t.txt
@@ -170,8 +170,14 @@ The barriers:
smp_mb__{before,after}_atomic()
-only apply to the RMW ops and can be used to augment/upgrade the ordering
-inherent to the used atomic op. These barriers provide a full smp_mb().
+only apply to the RMW atomic ops and can be used to augment/upgrade the
+ordering inherent to the op. These barriers act almost like a full smp_mb():
+smp_mb__before_atomic() orders all earlier accesses against the RMW op
+itself and all accesses following it, and smp_mb__after_atomic() orders all
+later accesses against the RMW op and all accesses preceding it. However,
+accesses between the smp_mb__{before,after}_atomic() and the RMW op are not
+ordered, so it is advisable to place the barrier right next to the RMW atomic
+op whenever possible.
These helper barriers exist because architectures have varying implicit
ordering on their SMP atomic primitives. For example our TSO architectures
@@ -195,7 +201,9 @@ Further, while something like:
atomic_dec(&X);
is a 'typical' RELEASE pattern, the barrier is strictly stronger than
-a RELEASE. Similarly for something like:
+a RELEASE because it orders preceding instructions against both the read
+and write parts of the atomic_dec(), and against all following instructions
+as well. Similarly, something like:
atomic_inc(&X);
smp_mb__after_atomic();
@@ -227,7 +235,8 @@ strictly stronger than ACQUIRE. As illus
This should not happen; but a hypothetical atomic_inc_acquire() --
(void)atomic_fetch_inc_acquire() for instance -- would allow the outcome,
-since then:
+because it would not order the W part of the RMW against the following
+WRITE_ONCE. Thus:
P1 P2
On Fri, May 03, 2019 at 01:13:44PM -0400, Alan Stern wrote:
> The description of smp_mb__before_atomic() and smp_mb__after_atomic()
> in Documentation/atomic_t.txt is slightly terse and misleading. It
> does not clearly state which other instructions are ordered by these
> barriers.
>
> This improves the text to make the actual ordering implications clear,
> and also to explain how these barriers differ from a RELEASE or
> ACQUIRE ordering.
>
> Signed-off-by: Alan Stern <[email protected]>
> CC: Peter Zijlstra <[email protected]>
I understand that this does indeed better describe the intended semantics:
Acked-by: Andrea Parri <[email protected]>
Now we would only need to fix the implementations and a few (mis)uses. ;-)
Andrea
>
> ---
>
> v2: Update the explanation: These barriers do provide order for
> accesses on the far side of the atomic RMW operation.
>
>
> Documentation/atomic_t.txt | 17 +++++++++++++----
> 1 file changed, 13 insertions(+), 4 deletions(-)
>
> Index: usb-devel/Documentation/atomic_t.txt
> ===================================================================
> --- usb-devel.orig/Documentation/atomic_t.txt
> +++ usb-devel/Documentation/atomic_t.txt
> @@ -170,8 +170,14 @@ The barriers:
>
> smp_mb__{before,after}_atomic()
>
> -only apply to the RMW ops and can be used to augment/upgrade the ordering
> -inherent to the used atomic op. These barriers provide a full smp_mb().
> +only apply to the RMW atomic ops and can be used to augment/upgrade the
> +ordering inherent to the op. These barriers act almost like a full smp_mb():
> +smp_mb__before_atomic() orders all earlier accesses against the RMW op
> +itself and all accesses following it, and smp_mb__after_atomic() orders all
> +later accesses against the RMW op and all accesses preceding it. However,
> +accesses between the smp_mb__{before,after}_atomic() and the RMW op are not
> +ordered, so it is advisable to place the barrier right next to the RMW atomic
> +op whenever possible.
>
> These helper barriers exist because architectures have varying implicit
> ordering on their SMP atomic primitives. For example our TSO architectures
> @@ -195,7 +201,9 @@ Further, while something like:
> atomic_dec(&X);
>
> is a 'typical' RELEASE pattern, the barrier is strictly stronger than
> -a RELEASE. Similarly for something like:
> +a RELEASE because it orders preceding instructions against both the read
> +and write parts of the atomic_dec(), and against all following instructions
> +as well. Similarly, something like:
>
> atomic_inc(&X);
> smp_mb__after_atomic();
> @@ -227,7 +235,8 @@ strictly stronger than ACQUIRE. As illus
>
> This should not happen; but a hypothetical atomic_inc_acquire() --
> (void)atomic_fetch_inc_acquire() for instance -- would allow the outcome,
> -since then:
> +because it would not order the W part of the RMW against the following
> +WRITE_ONCE. Thus:
>
> P1 P2
>
>
On Mon, May 06, 2019 at 06:42:38PM +0200, Andrea Parri wrote:
> On Fri, May 03, 2019 at 01:13:44PM -0400, Alan Stern wrote:
> > The description of smp_mb__before_atomic() and smp_mb__after_atomic()
> > in Documentation/atomic_t.txt is slightly terse and misleading. It
> > does not clearly state which other instructions are ordered by these
> > barriers.
> >
> > This improves the text to make the actual ordering implications clear,
> > and also to explain how these barriers differ from a RELEASE or
> > ACQUIRE ordering.
> >
> > Signed-off-by: Alan Stern <[email protected]>
> > CC: Peter Zijlstra <[email protected]>
>
> I understand that this does indeed better describe the intended semantics:
>
> Acked-by: Andrea Parri <[email protected]>
I reverted the original and applied this one. It will become visible
at the next rebase.
> Now we would only need to fix the implementations and a few (mis)uses. ;-)
You do have a start on this task! ;-)
Thanx, Paul
> Andrea
>
>
> >
> > ---
> >
> > v2: Update the explanation: These barriers do provide order for
> > accesses on the far side of the atomic RMW operation.
> >
> >
> > Documentation/atomic_t.txt | 17 +++++++++++++----
> > 1 file changed, 13 insertions(+), 4 deletions(-)
> >
> > Index: usb-devel/Documentation/atomic_t.txt
> > ===================================================================
> > --- usb-devel.orig/Documentation/atomic_t.txt
> > +++ usb-devel/Documentation/atomic_t.txt
> > @@ -170,8 +170,14 @@ The barriers:
> >
> > smp_mb__{before,after}_atomic()
> >
> > -only apply to the RMW ops and can be used to augment/upgrade the ordering
> > -inherent to the used atomic op. These barriers provide a full smp_mb().
> > +only apply to the RMW atomic ops and can be used to augment/upgrade the
> > +ordering inherent to the op. These barriers act almost like a full smp_mb():
> > +smp_mb__before_atomic() orders all earlier accesses against the RMW op
> > +itself and all accesses following it, and smp_mb__after_atomic() orders all
> > +later accesses against the RMW op and all accesses preceding it. However,
> > +accesses between the smp_mb__{before,after}_atomic() and the RMW op are not
> > +ordered, so it is advisable to place the barrier right next to the RMW atomic
> > +op whenever possible.
> >
> > These helper barriers exist because architectures have varying implicit
> > ordering on their SMP atomic primitives. For example our TSO architectures
> > @@ -195,7 +201,9 @@ Further, while something like:
> > atomic_dec(&X);
> >
> > is a 'typical' RELEASE pattern, the barrier is strictly stronger than
> > -a RELEASE. Similarly for something like:
> > +a RELEASE because it orders preceding instructions against both the read
> > +and write parts of the atomic_dec(), and against all following instructions
> > +as well. Similarly, something like:
> >
> > atomic_inc(&X);
> > smp_mb__after_atomic();
> > @@ -227,7 +235,8 @@ strictly stronger than ACQUIRE. As illus
> >
> > This should not happen; but a hypothetical atomic_inc_acquire() --
> > (void)atomic_fetch_inc_acquire() for instance -- would allow the outcome,
> > -since then:
> > +because it would not order the W part of the RMW against the following
> > +WRITE_ONCE. Thus:
> >
> > P1 P2
> >
> >
>