From: Chen-Yu Tsai <[email protected]>
Hi everyone,
This is series is the first part of a large series (I haven't done the
rest) of patches to rewrite the clk parent relationship handling within
the sunxi-ng clk driver. This is based on Stephen's recent work allowing
clk drivers to specify clk parents using struct clk_hw * or parsing DT
phandles in the clk node.
This series can be split into a few major parts:
1) The first patch is a small fix for clk debugfs representation. This
was done before commit 1a079560b145 ("clk: Cache core in
clk_fetch_parent_index() without names") was posted, so it might or
might not be needed. Found this when checking my work using
clk_possible_parents.
2) A bunch of CLK_HW_INIT_* helper macros are added. These cover the
situations I encountered, or assume I will encounter, such as single
internal (struct clk_hw *) parent, single DT (struct clk_parent_data
.fw_name), multiple internal parents, and multiple mixed (internal +
DT) parents. A special variant for just an internal single parent is
added, CLK_HW_INIT_HWS, which lets the driver share the singular
list, instead of having the compiler create a compound literal every
time. It might even make sense to only keep this variant.
3) A bunch of CLK_FIXED_FACTOR_* helper macros are added. The rationale
is the same as the single parent CLK_HW_INIT_* helpers.
4) Bulk conversion of CLK_FIXED_FACTOR to use local parent references,
either struct clk_hw * or DT .fw_name types, whichever the hardware
requires.
5) The beginning of SUNXI_CCU_GATE conversion to local parent
references. This part is not done. They are included as justification
and examples for the shared list of clk parents case.
I realize this is going to be many patches every time I convert a clock
type. Going forward would the people involved prefer I send out
individual patches like this series, or squash them all together?
Stephen, would it make sense for you to pick up the first 7 patches that
touch the clk core? And then we can base our clk branch on top of those?
Thanks
ChenYu
Chen-Yu Tsai (25):
clk: Fix debugfs clk_possible_parents for clks without parent string
names
clk: Add CLK_HW_INIT_* macros using .parent_hws
clk: Add CLK_HW_INIT_FW_NAME macro using .fw_name in .parent_data
clk: Add CLK_HW_INIT_PARENT_DATA macro using .parent_data
clk: fixed-factor: Add CLK_FIXED_FACTOR_HW which takes clk_hw pointer
as parent
clk: fixed-factor: Add CLK_FIXED_FACTOR_HWS which takes list of struct
clk_hw *
clk: fixed-factor: Add CLK_FIXED_FACTOR_FW_NAME for DT clock-names
parent
clk: sunxi-ng: switch to of_clk_hw_register() for registering clks
clk: sunxi-ng: sun8i-r: Use local parent references for CLK_HW_INIT_*
clk: sunxi-ng: a10: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: sun5i: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a31: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a23: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a33: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: h3: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: r40: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: v3s: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: sun8i-r: Use local parent references for
CLK_FIXED_FACTOR
clk: sunxi-ng: f1c100s: Use local parent references for
CLK_FIXED_FACTOR
clk: sunxi-ng: a64: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: h6: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: h6-r: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: gate: Add macros for referencing local clock parents
clk: sunxi-ng: a80-usb: Use local parent references for SUNXI_CCU_GATE
clk: sunxi-ng: sun8i-r: Use local parent references for SUNXI_CCU_GATE
drivers/clk/clk.c | 10 ++-
drivers/clk/sunxi-ng/ccu-sun4i-a10.c | 39 ++++++---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 41 +++++----
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 2 +-
drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 69 +++++++++------
drivers/clk/sunxi-ng/ccu-sun5i.c | 34 +++++---
drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 39 ++++++---
drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 34 +++++---
drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 34 +++++---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 29 ++++---
drivers/clk/sunxi-ng/ccu-sun8i-r.c | 104 +++++++++++------------
drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 46 ++++++----
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 29 ++++---
drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c | 32 ++++---
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c | 29 ++++---
drivers/clk/sunxi-ng/ccu_common.c | 2 +-
drivers/clk/sunxi-ng/ccu_gate.h | 53 ++++++++++++
include/linux/clk-provider.h | 84 ++++++++++++++++++
18 files changed, 487 insertions(+), 223 deletions(-)
--
2.20.1
From: Chen-Yu Tsai <[email protected]>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 39 ++++++++++++++++++----------
1 file changed, 25 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
index b494c4fe0b2c..048c0d75d0b0 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
@@ -963,21 +963,32 @@ static struct ccu_common *sun6i_a31_ccu_clks[] = {
&out_c_clk.common,
};
+static const struct clk_hw *clk_parent_pll_audio[] = {
+ &pll_audio_base_clk.common.hw
+};
+
/* We hardcode the divider to 1 for now */
-static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
- "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
- "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
- "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
- "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x",
- "pll-periph", 1, 2, 0);
-static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
- "pll-video0", 1, 2, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x",
- "pll-video1", 1, 2, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
+ clk_parent_pll_audio,
+ 1, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
+ clk_parent_pll_audio,
+ 2, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
+ clk_parent_pll_audio,
+ 1, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
+ clk_parent_pll_audio,
+ 1, 2, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
+ &pll_periph_clk.common.hw,
+ 1, 2, 0);
+static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
+ &pll_video0_clk.common.hw,
+ 1, 2, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
+ &pll_video1_clk.common.hw,
+ 1, 2, CLK_SET_RATE_PARENT);
static struct clk_hw_onecell_data sun6i_a31_hw_clks = {
.hws = {
--
2.20.1
From: Chen-Yu Tsai <[email protected]>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c | 29 ++++++++++++++++--------
1 file changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
index e748b8a6f3c5..f6b776ca8e49 100644
--- a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
+++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
@@ -374,16 +374,25 @@ static struct ccu_common *suniv_ccu_clks[] = {
&avs_clk.common,
};
-static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
- "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
- "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
- "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
- "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_video_2x_clk, "pll-video-2x",
- "pll-video", 1, 2, 0);
+static const struct clk_hw *clk_parent_pll_audio[] = {
+ &pll_audio_base_clk.common.hw
+};
+
+static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
+ clk_parent_pll_audio
+ 4, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
+ clk_parent_pll_audio
+ 2, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
+ clk_parent_pll_audio
+ 1, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
+ clk_parent_pll_audio
+ 1, 2, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
+ &pll_video0_clk.common.hw,
+ 1, 2, 0);
static struct clk_hw_onecell_data suniv_hw_clks = {
.hws = {
--
2.20.1
From: Chen-Yu Tsai <[email protected]>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 41 +++++++++++++++++----------
1 file changed, 26 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index d3fc1f5bf396..97fd037ed0d9 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -605,23 +605,34 @@ static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
/* Fixed Factor clocks */
-static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0);
+static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
+
+static const struct clk_hw *clk_parent_pll_audio[] = {
+ &pll_audio_base_clk.common.hw
+};
/* We hardcode the divider to 1 for now */
-static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
- "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
- "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
- "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
- "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
- "pll-periph0", 1, 2, 0);
-static CLK_FIXED_FACTOR(pll_periph1_2x_clk, "pll-periph1-2x",
- "pll-periph1", 1, 2, 0);
-static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
- "pll-video0", 1, 2, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
+ clk_parent_pll_audio
+ 1, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
+ clk_parent_pll_audio
+ 2, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
+ clk_parent_pll_audio
+ 1, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
+ clk_parent_pll_audio
+ 1, 2, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
+ &pll_periph0_clk.common.hw,
+ 1, 2, 0);
+static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
+ &pll_periph1_clk.common.hw,
+ 1, 2, 0);
+static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
+ &pll_video0_clk.common.hw,
+ 1, 2, CLK_SET_RATE_PARENT);
static struct ccu_common *sun50i_a64_ccu_clks[] = {
&pll_cpux_clk.common,
--
2.20.1
From: Chen-Yu Tsai <[email protected]>
With the new clk parenting code, clk_init_data was expanded to include
.parent_hws, for clk drivers to directly reference parents by clk_hw,
and .parent_data, for clk drivers to specify parents using a combination
of device tree clock-names, pointers to struct clk_hw, device tree clocks,
and/or fallback global clock names.
Add four new macros:
- SUNXI_CCU_GATE_HW, that can take a struct clk_hw pointer, instead
of a string, as its parent.
- SUNXI_CCU_GATE_FW that takes a string to match a clock-names entry
in the device tree to specify the clock parent.
- SUNXI_CCU_GATE_HWS that takes an array of struct clk_hw * as its
parent. This allows the array to be shared with other clk
declarations.
- SUNXI_CCU_GATE_DATA that takes an array of struct clk_parent_data *
as its parent. This allows the array to be shared with other clk
declarations.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
drivers/clk/sunxi-ng/ccu_gate.h | 53 +++++++++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu_gate.h b/drivers/clk/sunxi-ng/ccu_gate.h
index 4466169bd2d7..613ddd03629e 100644
--- a/drivers/clk/sunxi-ng/ccu_gate.h
+++ b/drivers/clk/sunxi-ng/ccu_gate.h
@@ -36,6 +36,59 @@ struct ccu_gate {
} \
}
+#define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \
+ struct ccu_gate _struct = { \
+ .enable = _gate, \
+ .common = { \
+ .reg = _reg, \
+ .hw.init = CLK_HW_INIT_HW(_name, \
+ _parent, \
+ &ccu_gate_ops, \
+ _flags), \
+ } \
+ }
+
+#define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \
+ struct ccu_gate _struct = { \
+ .enable = _gate, \
+ .common = { \
+ .reg = _reg, \
+ .hw.init = CLK_HW_INIT_FW_NAME(_name, \
+ _parent, \
+ &ccu_gate_ops, \
+ _flags), \
+ } \
+ }
+
+/*
+ * The following two macros allow the re-use of the data structure
+ * holding the parent info.
+ */
+#define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \
+ struct ccu_gate _struct = { \
+ .enable = _gate, \
+ .common = { \
+ .reg = _reg, \
+ .hw.init = CLK_HW_INIT_HWS(_name, \
+ _parent, \
+ &ccu_gate_ops, \
+ _flags), \
+ } \
+ }
+
+#define SUNXI_CCU_GATE_DATA(_struct, _name, _data, _reg, _gate, _flags) \
+ struct ccu_gate _struct = { \
+ .enable = _gate, \
+ .common = { \
+ .reg = _reg, \
+ .hw.init = \
+ CLK_HW_INIT_PARENTS_DATA(_name, \
+ _data, \
+ &ccu_gate_ops, \
+ _flags), \
+ } \
+ }
+
static inline struct ccu_gate *hw_to_ccu_gate(struct clk_hw *hw)
{
struct ccu_common *common = hw_to_ccu_common(hw);
--
2.20.1
From: Chen-Yu Tsai <[email protected]>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 34 ++++++++++++++++++----------
1 file changed, 22 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
index 25bcf3fd2dfc..25a14548f39b 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
@@ -588,19 +588,29 @@ static struct ccu_common *sun8i_a33_ccu_clks[] = {
&ats_clk.common,
};
+static const struct clk_hw *clk_parent_pll_audio[] = {
+ &pll_audio_base_clk.common.hw
+};
+
/* We hardcode the divider to 1 for now */
-static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
- "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
- "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
- "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
- "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x",
- "pll-periph", 1, 2, 0);
-static CLK_FIXED_FACTOR(pll_video_2x_clk, "pll-video-2x",
- "pll-video", 1, 2, 0);
+static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
+ clk_parent_pll_audio,
+ 1, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
+ clk_parent_pll_audio,
+ 2, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
+ clk_parent_pll_audio,
+ 1, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
+ clk_parent_pll_audio,
+ 1, 2, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
+ &pll_periph_clk.common.hw,
+ 1, 2, 0);
+static CLK_FIXED_FACTOR_HW(pll_video_2x_clk, "pll-video-2x",
+ &pll_video_clk.common.hw,
+ 1, 2, 0);
static struct clk_hw_onecell_data sun8i_a33_hw_clks = {
.hws = {
--
2.20.1
From: Chen-Yu Tsai <[email protected]>
With the new clk parenting code, struct clk_init_data was expanded to
include .parent_data, for clk drivers that have parents referenced using
a combination of device tree clock-names, clock indices, and/or struct
clk_hw pointers.
Add a new macro that can take a list of struct clk_parent_data for
drivers to use.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
include/linux/clk-provider.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index edad4ad5d897..d0d58c49f3ad 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -951,6 +951,15 @@ extern struct of_device_id __clk_of_table;
.ops = _ops, \
})
+#define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \
+ (&(struct clk_init_data) { \
+ .flags = _flags, \
+ .name = _name, \
+ .parent_data = _parents, \
+ .num_parents = ARRAY_SIZE(_parents), \
+ .ops = _ops, \
+ })
+
#define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
(&(struct clk_init_data) { \
.flags = _flags, \
--
2.20.1
From: Chen-Yu Tsai <[email protected]>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 34 ++++++++++++++++++----------
1 file changed, 22 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a23.c b/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
index a9c0c5406b85..de2f2962164e 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
@@ -551,19 +551,29 @@ static struct ccu_common *sun8i_a23_ccu_clks[] = {
&ats_clk.common,
};
+static const struct clk_hw *clk_parent_pll_audio[] = {
+ &pll_audio_base_clk.common.hw
+};
+
/* We hardcode the divider to 1 for now */
-static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
- "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
- "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
- "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
- "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x",
- "pll-periph", 1, 2, 0);
-static CLK_FIXED_FACTOR(pll_video_2x_clk, "pll-video-2x",
- "pll-video", 1, 2, 0);
+static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
+ clk_parent_pll_audio,
+ 1, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
+ clk_parent_pll_audio,
+ 2, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
+ clk_parent_pll_audio,
+ 1, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
+ clk_parent_pll_audio,
+ 1, 2, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
+ &pll_periph_clk.common.hw,
+ 1, 2, 0);
+static CLK_FIXED_FACTOR_HW(pll_video_2x_clk, "pll-video-2x",
+ &pll_video_clk.common.hw,
+ 1, 2, 0);
static struct clk_hw_onecell_data sun8i_a23_hw_clks = {
.hws = {
--
2.20.1
From: Chen-Yu Tsai <[email protected]>
With the new clk parenting code, clk_init_data was expanded to include
.parent_data, for clk drivers that have parents referenced using a
combination of device tree clock-names, clock indices, and/or clk_hw
pointers.
Add a CLK_HW_INIT macro for specifying a single parent from the device
tree using .fw_name in struct clk_parent_data.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
include/linux/clk-provider.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 0c241b43a802..edad4ad5d897 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -922,6 +922,17 @@ extern struct of_device_id __clk_of_table;
.ops = _ops, \
})
+#define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \
+ (&(struct clk_init_data) { \
+ .flags = _flags, \
+ .name = _name, \
+ .parent_data = (const struct clk_parent_data[]) { \
+ { .fw_name = _parent }, \
+ }, \
+ .num_parents = 1, \
+ .ops = _ops, \
+ })
+
#define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
(&(struct clk_init_data) { \
.flags = _flags, \
--
2.20.1
From: Chen-Yu Tsai <[email protected]>
With the new clk parenting code, clk_init_data was expanded to include
.parent_data, for clk drivers to specify parents using a combination of
device tree clock-names, pointers to struct clk_hw, device tree clocks,
and/or fallback global clock names.
Add a new macro, CLK_FIXED_FACTOR_FW_NAME, that takes a string to match
a clock-names entry in the device tree to specify the clock parent.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
include/linux/clk-provider.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index ac26aef874d1..a6cd04442eff 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -1006,6 +1006,17 @@ extern struct of_device_id __clk_of_table;
_flags), \
}
+#define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \
+ _div, _mult, _flags) \
+ struct clk_fixed_factor _struct = { \
+ .div = _div, \
+ .mult = _mult, \
+ .hw.init = CLK_HW_INIT_FW_NAME(_name, \
+ _parent, \
+ &clk_fixed_factor_ops, \
+ _flags), \
+ }
+
#ifdef CONFIG_OF
int of_clk_add_provider(struct device_node *np,
struct clk *(*clk_src_get)(struct of_phandle_args *args,
--
2.20.1
From: Chen-Yu Tsai <[email protected]>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
A forward declaration for struct clk_fixed_factor pll_periph0_4x_clk
is added as the definitions of the fixed factor clocks appear much later
in the file. The position of fixed factor clock definitions will be
moved for all drivers at a later time, before the conversion of all
other clock types.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 69 ++++++++++++++++++----------
1 file changed, 44 insertions(+), 25 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
index 9d3f98962779..207c65dc5d70 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
@@ -622,8 +622,9 @@ static SUNXI_CCU_GATE(bus_xhci_clk, "bus-xhci", "ahb3", 0xa8c, BIT(5), 0);
static SUNXI_CCU_GATE(bus_ehci3_clk, "bus-ehci3", "ahb3", 0xa8c, BIT(7), 0);
static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0);
-static CLK_FIXED_FACTOR(pcie_ref_100m_clk, "pcie-ref-100M",
- "pll-periph0-4x", 24, 1, 0);
+static struct clk_fixed_factor pll_periph0_4x_clk;
+static CLK_FIXED_FACTOR_HW(pcie_ref_100m_clk, "pcie-ref-100M",
+ &pll_periph0_4x_clk.hw, 24, 1, 0);
static SUNXI_CCU_GATE(pcie_ref_clk, "pcie-ref", "pcie-ref-100M",
0xab0, BIT(31), 0);
static SUNXI_CCU_GATE(pcie_ref_out_clk, "pcie-ref-out", "pcie-ref",
@@ -745,34 +746,52 @@ static SUNXI_CCU_M_WITH_MUX_GATE(hdcp_clk, "hdcp", hdcp_parents, 0xc40,
static SUNXI_CCU_GATE(bus_hdcp_clk, "bus-hdcp", "ahb3", 0xc4c, BIT(0), 0);
/* Fixed factor clocks */
-static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0);
+static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
+
+static const struct clk_hw *clk_parent_pll_audio[] = {
+ &pll_audio_base_clk.common.hw
+};
/*
* The divider of pll-audio is fixed to 8 now, as pll-audio-4x has a
* fixed post-divider 2.
*/
-static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
- "pll-audio-base", 8, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
- "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
- "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
-
-static CLK_FIXED_FACTOR(pll_periph0_4x_clk, "pll-periph0-4x",
- "pll-periph0", 1, 4, 0);
-static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
- "pll-periph0", 1, 2, 0);
-
-static CLK_FIXED_FACTOR(pll_periph1_4x_clk, "pll-periph1-4x",
- "pll-periph1", 1, 4, 0);
-static CLK_FIXED_FACTOR(pll_periph1_2x_clk, "pll-periph1-2x",
- "pll-periph1", 1, 2, 0);
-
-static CLK_FIXED_FACTOR(pll_video0_4x_clk, "pll-video0-4x",
- "pll-video0", 1, 4, CLK_SET_RATE_PARENT);
-
-static CLK_FIXED_FACTOR(pll_video1_4x_clk, "pll-video1-4x",
- "pll-video1", 1, 4, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
+ clk_parent_pll_audio,
+ 8, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
+ clk_parent_pll_audio,
+ 4, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
+ clk_parent_pll_audio,
+ 2, 1, CLK_SET_RATE_PARENT);
+
+static const struct clk_hw pll_periph0_parents[] = {
+ &pll_periph0_clk.common.hw
+};
+static CLK_FIXED_FACTOR_HWS(pll_periph0_4x_clk, "pll-periph0-4x",
+ pll_periph0_parents,
+ 1, 4, 0);
+static CLK_FIXED_FACTOR_HWS(pll_periph0_2x_clk, "pll-periph0-2x",
+ pll_periph0_parents,
+ 1, 2, 0);
+
+static const struct clk_hw pll_periph1_parents[] = {
+ &pll_periph1_clk.common.hw
+};
+static CLK_FIXED_FACTOR_HWS(pll_periph1_4x_clk, "pll-periph1-4x",
+ pll_periph1_parents,
+ 1, 4, 0);
+static CLK_FIXED_FACTOR_HWS(pll_periph1_2x_clk, "pll-periph1-2x",
+ pll_periph1_parents,
+ 1, 2, 0);
+
+static CLK_FIXED_FACTOR_HW(pll_video0_4x_clk, "pll-video0-4x",
+ &pll_video0_clk.common.hw,
+ 1, 4, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HW(pll_video1_4x_clk, "pll-video1-4x",
+ &pll_video1_clk.common.hw,
+ 1, 4, CLK_SET_RATE_PARENT);
static struct ccu_common *sun50i_h6_ccu_clks[] = {
&pll_cpux_clk.common,
--
2.20.1
From: Chen-Yu Tsai <[email protected]>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 29 ++++++++++++++++++----------
1 file changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
index ec64eb692ecf..60f011b1fbf6 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
@@ -437,17 +437,26 @@ static struct ccu_common *sun8i_v3s_ccu_clks[] = {
&mipi_csi_clk.common,
};
+static const struct clk_hw *clk_parent_pll_audio[] = {
+ &pll_audio_base_clk.common.hw
+};
+
/* We hardcode the divider to 4 for now */
-static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
- "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
- "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
- "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
- "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
- "pll-periph0", 1, 2, 0);
+static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
+ clk_parent_pll_audio,
+ 4, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
+ clk_parent_pll_audio,
+ 2, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
+ clk_parent_pll_audio,
+ 1, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
+ clk_parent_pll_audio,
+ 1, 2, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
+ &pll_periph0_clk.common.hw,
+ 1, 2, 0);
static struct clk_hw_onecell_data sun8i_v3s_hw_clks = {
.hws = {
--
2.20.1
From: Chen-Yu Tsai <[email protected]>
With the new clk parenting code and SUNXI_CCU_GATE macros, we can
reference parents locally via pointers to struct clk_hw or DT
clock-names.
Convert existing SUNXI_CCU_GATE definitions to SUNXI_CCU_GATE_DATA to
specify the parent clock.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c | 32 +++++++++++++++---------
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c
index 1d76f24f7df3..23bc11e65539 100644
--- a/drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c
+++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c
@@ -22,18 +22,26 @@
#include "ccu-sun9i-a80-usb.h"
-static SUNXI_CCU_GATE(bus_hci0_clk, "bus-hci0", "bus-usb", 0x0, BIT(1), 0);
-static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M", 0x0, BIT(2), 0);
-static SUNXI_CCU_GATE(bus_hci1_clk, "bus-hci1", "bus-usb", 0x0, BIT(3), 0);
-static SUNXI_CCU_GATE(bus_hci2_clk, "bus-hci2", "bus-usb", 0x0, BIT(5), 0);
-static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M", 0x0, BIT(6), 0);
-
-static SUNXI_CCU_GATE(usb0_phy_clk, "usb0-phy", "osc24M", 0x4, BIT(1), 0);
-static SUNXI_CCU_GATE(usb1_hsic_clk, "usb1-hsic", "osc24M", 0x4, BIT(2), 0);
-static SUNXI_CCU_GATE(usb1_phy_clk, "usb1-phy", "osc24M", 0x4, BIT(3), 0);
-static SUNXI_CCU_GATE(usb2_hsic_clk, "usb2-hsic", "osc24M", 0x4, BIT(4), 0);
-static SUNXI_CCU_GATE(usb2_phy_clk, "usb2-phy", "osc24M", 0x4, BIT(5), 0);
-static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "osc24M", 0x4, BIT(10), 0);
+static const struct clk_parent_data clk_parent_hosc[] = {
+ { .fw_name = "hosc" },
+};
+
+static const struct clk_parent_data clk_parent_bus[] = {
+ { .fw_name = "bus" },
+};
+
+static SUNXI_CCU_GATE_DATA(bus_hci0_clk, "bus-hci0", clk_parent_bus, 0x0, BIT(1), 0);
+static SUNXI_CCU_GATE_DATA(usb_ohci0_clk, "usb-ohci0", clk_parent_hosc, 0x0, BIT(2), 0);
+static SUNXI_CCU_GATE_DATA(bus_hci1_clk, "bus-hci1", clk_parent_bus, 0x0, BIT(3), 0);
+static SUNXI_CCU_GATE_DATA(bus_hci2_clk, "bus-hci2", clk_parent_bus, 0x0, BIT(5), 0);
+static SUNXI_CCU_GATE_DATA(usb_ohci2_clk, "usb-ohci2", clk_parent_hosc, 0x0, BIT(6), 0);
+
+static SUNXI_CCU_GATE_DATA(usb0_phy_clk, "usb0-phy", clk_parent_hosc, 0x4, BIT(1), 0);
+static SUNXI_CCU_GATE_DATA(usb1_hsic_clk, "usb1-hsic", clk_parent_hosc, 0x4, BIT(2), 0);
+static SUNXI_CCU_GATE_DATA(usb1_phy_clk, "usb1-phy", clk_parent_hosc, 0x4, BIT(3), 0);
+static SUNXI_CCU_GATE_DATA(usb2_hsic_clk, "usb2-hsic", clk_parent_hosc, 0x4, BIT(4), 0);
+static SUNXI_CCU_GATE_DATA(usb2_phy_clk, "usb2-phy", clk_parent_hosc, 0x4, BIT(5), 0);
+static SUNXI_CCU_GATE_DATA(usb_hsic_clk, "usb-hsic", clk_parent_hosc, 0x4, BIT(10), 0);
static struct ccu_common *sun9i_a80_usb_clks[] = {
&bus_hci0_clk.common,
--
2.20.1
From: Chen-Yu Tsai <[email protected]>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 46 ++++++++++++++++++----------
1 file changed, 29 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
index f9625f7b9ec2..5fef799740ac 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
@@ -952,25 +952,37 @@ static struct ccu_common *sun8i_r40_ccu_clks[] = {
};
/* Fixed Factor clocks */
-static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0);
+static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
+
+static const struct clk_hw *clk_parent_pll_audio[] = {
+ &pll_audio_base_clk.common.hw
+};
/* We hardcode the divider to 4 for now */
-static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
- "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
- "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
- "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
- "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
- "pll-periph0", 1, 2, 0);
-static CLK_FIXED_FACTOR(pll_periph1_2x_clk, "pll-periph1-2x",
- "pll-periph1", 1, 2, 0);
-static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
- "pll-video0", 1, 2, 0);
-static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x",
- "pll-video1", 1, 2, 0);
+static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
+ clk_parent_pll_audio,
+ 4, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
+ clk_parent_pll_audio,
+ 2, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
+ clk_parent_pll_audio,
+ 1, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
+ clk_parent_pll_audio,
+ 1, 2, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
+ &pll_periph0_clk.common.hw,
+ 1, 2, 0);
+static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
+ &pll_periph1_clk.common.hw,
+ 1, 2, 0);
+static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
+ &pll_video0_clk.common.hw,
+ 1, 2, 0);
+static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
+ &pll_video1_clk.common.hw,
+ 1, 2, 0);
static struct clk_hw_onecell_data sun8i_r40_hw_clks = {
.hws = {
--
2.20.1
From: Chen-Yu Tsai <[email protected]>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 29 +++++++++++++++++++----------
1 file changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 0f3df565c6c1..d5b5cd558ecf 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -725,17 +725,26 @@ static struct ccu_common *sun50i_h5_ccu_clks[] = {
&gpu_clk.common,
};
+static const struct clk_hw *clk_parent_pll_audio[] = {
+ &pll_audio_base_clk.common.hw
+};
+
/* We hardcode the divider to 1 for now */
-static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
- "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
- "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
- "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
- "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
- "pll-periph0", 1, 2, 0);
+static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
+ clk_parent_pll_audio,
+ 1, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
+ clk_parent_pll_audio,
+ 2, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
+ clk_parent_pll_audio,
+ 1, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
+ clk_parent_pll_audio,
+ 1, 2, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
+ &pll_periph0_clk.common.hw,
+ 1, 2, 0);
static struct clk_hw_onecell_data sun8i_h3_hw_clks = {
.hws = {
--
2.20.1
From: Chen-Yu Tsai <[email protected]>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
drivers/clk/sunxi-ng/ccu-sun8i-r.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
index a43e8de873d7..4a111c28b8c3 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
@@ -57,7 +57,7 @@ static struct ccu_div ar100_clk = {
},
};
-static CLK_FIXED_FACTOR(ahb0_clk, "ahb0", "ar100", 1, 1, 0);
+static CLK_FIXED_FACTOR_HW(ahb0_clk, "ahb0", &ar100_clk.common.hw, 1, 1, 0);
static struct ccu_div apb0_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
--
2.20.1
From: Chen-Yu Tsai <[email protected]>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
drivers/clk/sunxi-ng/ccu-sun4i-a10.c | 39 ++++++++++++++++++----------
1 file changed, 25 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
index 2bbfb3343311..59def849db08 100644
--- a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
+++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
@@ -168,8 +168,9 @@ static struct ccu_nk pll_periph_base_clk = {
},
};
-static CLK_FIXED_FACTOR(pll_periph_clk, "pll-periph", "pll-periph-base",
- 2, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HW(pll_periph_clk, "pll-periph",
+ &pll_periph_base_clk.common.hw,
+ 2, 1, CLK_SET_RATE_PARENT);
/* Not documented on A10 */
static struct ccu_div pll_periph_sata_clk = {
@@ -1036,19 +1037,29 @@ static struct ccu_common *sun4i_sun7i_ccu_clks[] = {
&out_b_clk.common
};
+static const struct clk_hw *clk_parent_pll_audio[] = {
+ &pll_audio_base_clk.common.hw
+};
+
/* Post-divider for pll-audio is hardcoded to 1 */
-static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
- "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
- "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
- "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
- "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
- "pll-video0", 1, 2, CLK_SET_RATE_PARENT);
-static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x",
- "pll-video1", 1, 2, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
+ clk_parent_pll_audio,
+ 1, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
+ clk_parent_pll_audio,
+ 2, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
+ clk_parent_pll_audio,
+ 1, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
+ clk_parent_pll_audio,
+ 1, 2, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
+ &pll_video0_clk.common.hw,
+ 1, 2, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
+ &pll_video1_clk.common.hw,
+ 1, 2, CLK_SET_RATE_PARENT);
static struct clk_hw_onecell_data sun4i_a10_hw_clks = {
--
2.20.1
From: Chen-Yu Tsai <[email protected]>
With the new clk parenting code, clk_init_data was expanded to include
.parent_hws, for clk drivers to directly reference parents by clk_hw.
Add a new macro, CLK_FIXED_FACTOR_HWS, that can take an array of pointers
to struct clk_hw, instead of a string, as its parent. Taking an array
instead of a direct pointer allows the reuse of the array for multiple
clks, rather than having one compound literal with the same contents
allocated for each clk declaration.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
include/linux/clk-provider.h | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index c7b10dd32c39..ac26aef874d1 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -991,6 +991,21 @@ extern struct of_device_id __clk_of_table;
_flags), \
}
+/*
+ * This macro allows the driver to reuse the _parent array for multiple
+ * fixed factor clk declarations.
+ */
+#define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \
+ _div, _mult, _flags) \
+ struct clk_fixed_factor _struct = { \
+ .div = _div, \
+ .mult = _mult, \
+ .hw.init = CLK_HW_INIT_HWS(_name, \
+ _parent, \
+ &clk_fixed_factor_ops, \
+ _flags), \
+ }
+
#ifdef CONFIG_OF
int of_clk_add_provider(struct device_node *np,
struct clk *(*clk_src_get)(struct of_phandle_args *args,
--
2.20.1
From: Chen-Yu Tsai <[email protected]>
With the new clk parenting code and CLK_HW_INIT_* macros, we can
reference parents locally via pointers to struct clk_hw or DT
clock-names.
Convert existing CLK_HW_INIT_* definitions to describe parents using
either struct clk_hw pointers or clock-names from the device tree
binding.
For the AR100, this also allows us to merge the generic AR100 and the
A83T specific one, which only differed in the global clock names for
their parent clocks. The device tree bindings used the same name
specifiers.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
drivers/clk/sunxi-ng/ccu-sun8i-r.c | 65 ++++++++++++------------------
1 file changed, 25 insertions(+), 40 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
index 71feb7b24e8a..a43e8de873d7 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
@@ -25,10 +25,13 @@
#include "ccu-sun8i-r.h"
-static const char * const ar100_parents[] = { "osc32k", "osc24M",
- "pll-periph0", "iosc" };
-static const char * const a83t_ar100_parents[] = { "osc16M-d512", "osc24M",
- "pll-periph0", "iosc" };
+static const struct clk_parent_data ar100_parents[] = {
+ { .fw_name = "losc" },
+ { .fw_name = "hosc" },
+ { .fw_name = "pll-periph" },
+ { .fw_name = "iosc" },
+};
+
static const struct ccu_mux_var_prediv ar100_predivs[] = {
{ .index = 2, .shift = 8, .width = 5 },
};
@@ -47,31 +50,10 @@ static struct ccu_div ar100_clk = {
.common = {
.reg = 0x00,
.features = CCU_FEATURE_VARIABLE_PREDIV,
- .hw.init = CLK_HW_INIT_PARENTS("ar100",
- ar100_parents,
- &ccu_div_ops,
- 0),
- },
-};
-
-static struct ccu_div a83t_ar100_clk = {
- .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
-
- .mux = {
- .shift = 16,
- .width = 2,
-
- .var_predivs = ar100_predivs,
- .n_var_predivs = ARRAY_SIZE(ar100_predivs),
- },
-
- .common = {
- .reg = 0x00,
- .features = CCU_FEATURE_VARIABLE_PREDIV,
- .hw.init = CLK_HW_INIT_PARENTS("ar100",
- a83t_ar100_parents,
- &ccu_div_ops,
- 0),
+ .hw.init = CLK_HW_INIT_PARENTS_DATA("ar100",
+ ar100_parents,
+ &ccu_div_ops,
+ 0),
},
};
@@ -82,10 +64,10 @@ static struct ccu_div apb0_clk = {
.common = {
.reg = 0x0c,
- .hw.init = CLK_HW_INIT("apb0",
- "ahb0",
- &ccu_div_ops,
- 0),
+ .hw.init = CLK_HW_INIT_HW("apb0",
+ &ahb0_clk.hw,
+ &ccu_div_ops,
+ 0),
},
};
@@ -115,7 +97,10 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
BIT(31), /* gate */
0);
-static const char *const a83t_r_mod0_parents[] = { "osc16M", "osc24M" };
+static const struct clk_parent_data a83t_r_mod0_parents[] = {
+ { .fw_name = "iosc" },
+ { .fw_name = "hosc" },
+};
static const struct ccu_mux_fixed_prediv a83t_ir_predivs[] = {
{ .index = 0, .div = 16 },
};
@@ -135,15 +120,15 @@ static struct ccu_mp a83t_ir_clk = {
.common = {
.reg = 0x54,
.features = CCU_FEATURE_VARIABLE_PREDIV,
- .hw.init = CLK_HW_INIT_PARENTS("ir",
- a83t_r_mod0_parents,
- &ccu_mp_ops,
- 0),
+ .hw.init = CLK_HW_INIT_PARENTS_DATA("ir",
+ a83t_r_mod0_parents,
+ &ccu_mp_ops,
+ 0),
},
};
static struct ccu_common *sun8i_a83t_r_ccu_clks[] = {
- &a83t_ar100_clk.common,
+ &ar100_clk.common,
&a83t_apb0_clk.common,
&apb0_pio_clk.common,
&apb0_ir_clk.common,
@@ -182,7 +167,7 @@ static struct ccu_common *sun50i_a64_r_ccu_clks[] = {
static struct clk_hw_onecell_data sun8i_a83t_r_hw_clks = {
.hws = {
- [CLK_AR100] = &a83t_ar100_clk.common.hw,
+ [CLK_AR100] = &ar100_clk.common.hw,
[CLK_AHB0] = &ahb0_clk.hw,
[CLK_APB0] = &a83t_apb0_clk.common.hw,
[CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
--
2.20.1
From: Chen-Yu Tsai <[email protected]>
With the new clk parenting code, struct clk_init_data was expanded to
include .parent_hws, for clk drivers to directly list parents by
pointing to their respective struct clk_hw's.
Add macros that can take either one single struct clk_hw *, or an array
of them, for drivers to use.
A special CLK_HW_INIT_HWS macro is included, which takes an array of
struct clk_hw *, but sets .num_parents to 1. This variant is to allow
the reuse of the array, instead of having a compound literal allocated
for each clk sharing the same parent.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
include/linux/clk-provider.h | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index bb6118f79784..0c241b43a802 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -904,6 +904,24 @@ extern struct of_device_id __clk_of_table;
.ops = _ops, \
})
+#define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \
+ (&(struct clk_init_data) { \
+ .flags = _flags, \
+ .name = _name, \
+ .parent_hws = (const struct clk_hw*[]) { _parent }, \
+ .num_parents = 1, \
+ .ops = _ops, \
+ })
+
+#define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \
+ (&(struct clk_init_data) { \
+ .flags = _flags, \
+ .name = _name, \
+ .parent_hws = _parent, \
+ .num_parents = 1, \
+ .ops = _ops, \
+ })
+
#define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
(&(struct clk_init_data) { \
.flags = _flags, \
@@ -913,6 +931,15 @@ extern struct of_device_id __clk_of_table;
.ops = _ops, \
})
+#define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \
+ (&(struct clk_init_data) { \
+ .flags = _flags, \
+ .name = _name, \
+ .parent_hws = _parents, \
+ .num_parents = ARRAY_SIZE(_parents), \
+ .ops = _ops, \
+ })
+
#define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
(&(struct clk_init_data) { \
.flags = _flags, \
--
2.20.1
On Mon, May 20, 2019 at 04:03:56PM +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai <[email protected]>
>
> Hi everyone,
>
> This is series is the first part of a large series (I haven't done the
> rest) of patches to rewrite the clk parent relationship handling within
> the sunxi-ng clk driver. This is based on Stephen's recent work allowing
> clk drivers to specify clk parents using struct clk_hw * or parsing DT
> phandles in the clk node.
>
> This series can be split into a few major parts:
>
> 1) The first patch is a small fix for clk debugfs representation. This
> was done before commit 1a079560b145 ("clk: Cache core in
> clk_fetch_parent_index() without names") was posted, so it might or
> might not be needed. Found this when checking my work using
> clk_possible_parents.
>
> 2) A bunch of CLK_HW_INIT_* helper macros are added. These cover the
> situations I encountered, or assume I will encounter, such as single
> internal (struct clk_hw *) parent, single DT (struct clk_parent_data
> .fw_name), multiple internal parents, and multiple mixed (internal +
> DT) parents. A special variant for just an internal single parent is
> added, CLK_HW_INIT_HWS, which lets the driver share the singular
> list, instead of having the compiler create a compound literal every
> time. It might even make sense to only keep this variant.
>
> 3) A bunch of CLK_FIXED_FACTOR_* helper macros are added. The rationale
> is the same as the single parent CLK_HW_INIT_* helpers.
>
> 4) Bulk conversion of CLK_FIXED_FACTOR to use local parent references,
> either struct clk_hw * or DT .fw_name types, whichever the hardware
> requires.
>
> 5) The beginning of SUNXI_CCU_GATE conversion to local parent
> references. This part is not done. They are included as justification
> and examples for the shared list of clk parents case.
That series is pretty neat. As far as sunxi is concerned, you can add my
Acked-by: Maxime Ripard <[email protected]>
> I realize this is going to be many patches every time I convert a clock
> type. Going forward would the people involved prefer I send out
> individual patches like this series, or squash them all together?
For bisection, I guess it would be good to keep the approach you've
had in this series. If this is really too much, I guess we can always
change oru mind later on.
Thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Hi Stephen,
On Mon, May 20, 2019 at 5:03 PM Maxime Ripard <[email protected]> wrote:
>
> On Mon, May 20, 2019 at 04:03:56PM +0800, Chen-Yu Tsai wrote:
> > From: Chen-Yu Tsai <[email protected]>
> >
> > Hi everyone,
> >
> > This is series is the first part of a large series (I haven't done the
> > rest) of patches to rewrite the clk parent relationship handling within
> > the sunxi-ng clk driver. This is based on Stephen's recent work allowing
> > clk drivers to specify clk parents using struct clk_hw * or parsing DT
> > phandles in the clk node.
> >
> > This series can be split into a few major parts:
> >
> > 1) The first patch is a small fix for clk debugfs representation. This
> > was done before commit 1a079560b145 ("clk: Cache core in
> > clk_fetch_parent_index() without names") was posted, so it might or
> > might not be needed. Found this when checking my work using
> > clk_possible_parents.
> >
> > 2) A bunch of CLK_HW_INIT_* helper macros are added. These cover the
> > situations I encountered, or assume I will encounter, such as single
> > internal (struct clk_hw *) parent, single DT (struct clk_parent_data
> > .fw_name), multiple internal parents, and multiple mixed (internal +
> > DT) parents. A special variant for just an internal single parent is
> > added, CLK_HW_INIT_HWS, which lets the driver share the singular
> > list, instead of having the compiler create a compound literal every
> > time. It might even make sense to only keep this variant.
> >
> > 3) A bunch of CLK_FIXED_FACTOR_* helper macros are added. The rationale
> > is the same as the single parent CLK_HW_INIT_* helpers.
> >
> > 4) Bulk conversion of CLK_FIXED_FACTOR to use local parent references,
> > either struct clk_hw * or DT .fw_name types, whichever the hardware
> > requires.
> >
> > 5) The beginning of SUNXI_CCU_GATE conversion to local parent
> > references. This part is not done. They are included as justification
> > and examples for the shared list of clk parents case.
>
> That series is pretty neat. As far as sunxi is concerned, you can add my
> Acked-by: Maxime Ripard <[email protected]>
>
> > I realize this is going to be many patches every time I convert a clock
> > type. Going forward would the people involved prefer I send out
> > individual patches like this series, or squash them all together?
>
> For bisection, I guess it would be good to keep the approach you've
> had in this series. If this is really too much, I guess we can always
> change oru mind later on.
Any thoughts on this series and how to proceed?
Thanks
ChenYu
Quoting Chen-Yu Tsai (2019-05-20 01:03:58)
> A special CLK_HW_INIT_HWS macro is included, which takes an array of
> struct clk_hw *, but sets .num_parents to 1. This variant is to allow
> the reuse of the array, instead of having a compound literal allocated
> for each clk sharing the same parent.
>
> Signed-off-by: Chen-Yu Tsai <[email protected]>
[...]
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index bb6118f79784..0c241b43a802 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -904,6 +904,24 @@ extern struct of_device_id __clk_of_table;
> .ops = _ops, \
> })
>
> +#define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \
> + (&(struct clk_init_data) { \
> + .flags = _flags, \
> + .name = _name, \
> + .parent_hws = (const struct clk_hw*[]) { _parent }, \
> + .num_parents = 1, \
> + .ops = _ops, \
> + })
> +
> +#define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \
Minor nitpick, please add a comment here to indicate that this is here
to share the same compound literal between multiple clks using the same
parent.
> + (&(struct clk_init_data) { \
> + .flags = _flags, \
> + .name = _name, \
> + .parent_hws = _parent, \
> + .num_parents = 1, \
> + .ops = _ops, \
> + })
Quoting Chen-Yu Tsai (2019-06-03 09:38:22)
> Hi Stephen,
>
> On Mon, May 20, 2019 at 5:03 PM Maxime Ripard <[email protected]> wrote:
> >
> > On Mon, May 20, 2019 at 04:03:56PM +0800, Chen-Yu Tsai wrote:
> > > From: Chen-Yu Tsai <[email protected]>
> > >
> > > Hi everyone,
> > >
> > > This is series is the first part of a large series (I haven't done the
> > > rest) of patches to rewrite the clk parent relationship handling within
> > > the sunxi-ng clk driver. This is based on Stephen's recent work allowing
> > > clk drivers to specify clk parents using struct clk_hw * or parsing DT
> > > phandles in the clk node.
> > >
> > > This series can be split into a few major parts:
> > >
> > > 1) The first patch is a small fix for clk debugfs representation. This
> > > was done before commit 1a079560b145 ("clk: Cache core in
> > > clk_fetch_parent_index() without names") was posted, so it might or
> > > might not be needed. Found this when checking my work using
> > > clk_possible_parents.
> > >
> > > 2) A bunch of CLK_HW_INIT_* helper macros are added. These cover the
> > > situations I encountered, or assume I will encounter, such as single
> > > internal (struct clk_hw *) parent, single DT (struct clk_parent_data
> > > .fw_name), multiple internal parents, and multiple mixed (internal +
> > > DT) parents. A special variant for just an internal single parent is
> > > added, CLK_HW_INIT_HWS, which lets the driver share the singular
> > > list, instead of having the compiler create a compound literal every
> > > time. It might even make sense to only keep this variant.
> > >
> > > 3) A bunch of CLK_FIXED_FACTOR_* helper macros are added. The rationale
> > > is the same as the single parent CLK_HW_INIT_* helpers.
> > >
> > > 4) Bulk conversion of CLK_FIXED_FACTOR to use local parent references,
> > > either struct clk_hw * or DT .fw_name types, whichever the hardware
> > > requires.
> > >
> > > 5) The beginning of SUNXI_CCU_GATE conversion to local parent
> > > references. This part is not done. They are included as justification
> > > and examples for the shared list of clk parents case.
> >
> > That series is pretty neat. As far as sunxi is concerned, you can add my
> > Acked-by: Maxime Ripard <[email protected]>
> >
> > > I realize this is going to be many patches every time I convert a clock
> > > type. Going forward would the people involved prefer I send out
> > > individual patches like this series, or squash them all together?
> >
> > For bisection, I guess it would be good to keep the approach you've
> > had in this series. If this is really too much, I guess we can always
> > change oru mind later on.
>
> Any thoughts on this series and how to proceed?
>
I have a few minor nitpicks but otherwise the series looks good to me.
I'm perfectly happy to see the individual patches unless you want to
squash them into one big patch. I can review the conversions either way.
Did you need me to apply any patches here? Or can I assume you'll resend
with a pull request so it can be merged into clk-next?
BTW, did you have to update any DT bindings or documentation? I didn't
see anything, so I'm a little surprised that all that stuff was already
in place.
On Sat, Jun 8, 2019 at 2:46 AM Stephen Boyd <[email protected]> wrote:
>
> Quoting Chen-Yu Tsai (2019-06-03 09:38:22)
> > Hi Stephen,
> >
> > On Mon, May 20, 2019 at 5:03 PM Maxime Ripard <[email protected]> wrote:
> > >
> > > On Mon, May 20, 2019 at 04:03:56PM +0800, Chen-Yu Tsai wrote:
> > > > From: Chen-Yu Tsai <[email protected]>
> > > >
> > > > Hi everyone,
> > > >
> > > > This is series is the first part of a large series (I haven't done the
> > > > rest) of patches to rewrite the clk parent relationship handling within
> > > > the sunxi-ng clk driver. This is based on Stephen's recent work allowing
> > > > clk drivers to specify clk parents using struct clk_hw * or parsing DT
> > > > phandles in the clk node.
> > > >
> > > > This series can be split into a few major parts:
> > > >
> > > > 1) The first patch is a small fix for clk debugfs representation. This
> > > > was done before commit 1a079560b145 ("clk: Cache core in
> > > > clk_fetch_parent_index() without names") was posted, so it might or
> > > > might not be needed. Found this when checking my work using
> > > > clk_possible_parents.
> > > >
> > > > 2) A bunch of CLK_HW_INIT_* helper macros are added. These cover the
> > > > situations I encountered, or assume I will encounter, such as single
> > > > internal (struct clk_hw *) parent, single DT (struct clk_parent_data
> > > > .fw_name), multiple internal parents, and multiple mixed (internal +
> > > > DT) parents. A special variant for just an internal single parent is
> > > > added, CLK_HW_INIT_HWS, which lets the driver share the singular
> > > > list, instead of having the compiler create a compound literal every
> > > > time. It might even make sense to only keep this variant.
> > > >
> > > > 3) A bunch of CLK_FIXED_FACTOR_* helper macros are added. The rationale
> > > > is the same as the single parent CLK_HW_INIT_* helpers.
> > > >
> > > > 4) Bulk conversion of CLK_FIXED_FACTOR to use local parent references,
> > > > either struct clk_hw * or DT .fw_name types, whichever the hardware
> > > > requires.
> > > >
> > > > 5) The beginning of SUNXI_CCU_GATE conversion to local parent
> > > > references. This part is not done. They are included as justification
> > > > and examples for the shared list of clk parents case.
> > >
> > > That series is pretty neat. As far as sunxi is concerned, you can add my
> > > Acked-by: Maxime Ripard <[email protected]>
> > >
> > > > I realize this is going to be many patches every time I convert a clock
> > > > type. Going forward would the people involved prefer I send out
> > > > individual patches like this series, or squash them all together?
> > >
> > > For bisection, I guess it would be good to keep the approach you've
> > > had in this series. If this is really too much, I guess we can always
> > > change oru mind later on.
> >
> > Any thoughts on this series and how to proceed?
> >
>
> I have a few minor nitpicks but otherwise the series looks good to me.
> I'm perfectly happy to see the individual patches unless you want to
> squash them into one big patch. I can review the conversions either way.
OK. Based on your and Maxime's response, I'll send them individually.
> Did you need me to apply any patches here? Or can I assume you'll resend
> with a pull request so it can be merged into clk-next?
I can send them as part of our normal pull request. Or did you want this
as a separate topic?
I'll still send out a v2 to cover your review comments.
> BTW, did you have to update any DT bindings or documentation? I didn't
> see anything, so I'm a little surprised that all that stuff was already
> in place.
The bindings had the clocks / clock-names all defined, and the DT all had
the properties, because we had already gone through one rewrite. It's just
the driver didn't follow them properly, because the parents were cross
node / driver, and we had these statically initialized parent name arrays.
I had started work on having the driver rewrite the parents lists based on
fetching clock names via DT, but it was far from elegant. Then this came
up. :)
Regards
ChenYu