From: Hoan Nguyen An <[email protected]>
Add r8a77965 DRIF bindings.
Signed-off-by: Hoan Nguyen An <[email protected]>
---
Documentation/devicetree/bindings/media/renesas,drif.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/media/renesas,drif.txt b/Documentation/devicetree/bindings/media/renesas,drif.txt
index 0d8974a..16cdee3 100644
--- a/Documentation/devicetree/bindings/media/renesas,drif.txt
+++ b/Documentation/devicetree/bindings/media/renesas,drif.txt
@@ -41,6 +41,7 @@ Required properties of an internal channel:
-------------------------------------------
- compatible: "renesas,r8a7795-drif" if DRIF controller is a part of R8A7795 SoC.
"renesas,r8a7796-drif" if DRIF controller is a part of R8A7796 SoC.
+ "renesas,r8a77965-drif" if DRIF controller is a part of R8A77965 SoC.
"renesas,rcar-gen3-drif" for a generic R-Car Gen3 compatible device.
When compatible with the generic version, nodes must list the
--
2.7.4
From: Hoan Nguyen An <[email protected]>
Adds the DRIF controller nodes for r8a77965.\n
Signed-off-by: Hoan Nguyen An <[email protected]>
---
arch/arm64/boot/dts/renesas/r8a77965.dtsi | 120 ++++++++++++++++++++++++++++++
1 file changed, 120 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index d8b8172..f4841619 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -1443,6 +1443,126 @@
};
};
+ drif00: rif@e6f40000 {
+ compatible = "renesas,r8a77965-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f40000 0 0x64>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 515>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x20>, <&dmac2 0x20>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 515>;
+ renesas,bonding = <&drif01>;
+ status = "disabled";
+ };
+
+ drif01: rif@e6f50000 {
+ compatible = "renesas,r8a77965-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f50000 0 0x64>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 514>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x22>, <&dmac2 0x22>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 514>;
+ renesas,bonding = <&drif00>;
+ status = "disabled";
+ };
+
+ drif10: rif@e6f60000 {
+ compatible = "renesas,r8a77965-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f60000 0 0x64>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 513>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x24>, <&dmac2 0x24>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 513>;
+ renesas,bonding = <&drif11>;
+ status = "disabled";
+ };
+
+ drif11: rif@e6f70000 {
+ compatible = "renesas,r8a77965-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f70000 0 0x64>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 512>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x26>, <&dmac2 0x26>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 512>;
+ renesas,bonding = <&drif10>;
+ status = "disabled";
+ };
+
+ drif20: rif@e6f80000 {
+ compatible = "renesas,r8a77965-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f80000 0 0x64>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 511>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x28>, <&dmac2 0x28>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 511>;
+ renesas,bonding = <&drif21>;
+ status = "disabled";
+ };
+
+ drif21: rif@e6f90000 {
+ compatible = "renesas,r8a77965-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f90000 0 0x64>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 510>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 510>;
+ renesas,bonding = <&drif20>;
+ status = "disabled";
+ };
+
+ drif30: rif@e6fa0000 {
+ compatible = "renesas,r8a77965-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6fa0000 0 0x64>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 509>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 509>;
+ renesas,bonding = <&drif31>;
+ status = "disabled";
+ };
+
+ drif31: rif@e6fb0000 {
+ compatible = "renesas,r8a77965-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6fb0000 0 0x64>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 508>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 508>;
+ renesas,bonding = <&drif30>;
+ status = "disabled";
+ };
+
rcar_sound: sound@ec500000 {
/*
* #sound-dai-cells is required
--
2.7.4
On Tue, Apr 23, 2019 at 07:09:58PM +0900, Nguyen An Hoan wrote:
> From: Hoan Nguyen An <[email protected]>
>
> Add r8a77965 DRIF bindings.
>
> Signed-off-by: Hoan Nguyen An <[email protected]>
According to the User's Manual Hardware, v1.50 Nov 20 2019,
the DRIF IP block M3-N (r8a77965) has a BITCTR register which
is not present on the H3 (r8a7795) or M3-W (r8a77995).
Does the DRIF IP block present on the M3-N (r8a77965) function
without support for this register in the driver?
If not then I think that:
1) This patch should be updated to note that renesas,rcar-gen3-drif
can only be used with H3 (r8a7795) and M3-W (r8a77995).
2) A driver patch is required
3) The DT patch, 2/2 of this series, should be updated to
i) Not use renesas,rcar-gen3-drif
ii) Extend the register aperture from 0x64 to 0x84.
> ---
> Documentation/devicetree/bindings/media/renesas,drif.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/media/renesas,drif.txt b/Documentation/devicetree/bindings/media/renesas,drif.txt
> index 0d8974a..16cdee3 100644
> --- a/Documentation/devicetree/bindings/media/renesas,drif.txt
> +++ b/Documentation/devicetree/bindings/media/renesas,drif.txt
> @@ -41,6 +41,7 @@ Required properties of an internal channel:
> -------------------------------------------
> - compatible: "renesas,r8a7795-drif" if DRIF controller is a part of R8A7795 SoC.
> "renesas,r8a7796-drif" if DRIF controller is a part of R8A7796 SoC.
> + "renesas,r8a77965-drif" if DRIF controller is a part of R8A77965 SoC.
> "renesas,rcar-gen3-drif" for a generic R-Car Gen3 compatible device.
>
> When compatible with the generic version, nodes must list the
> --
> 2.7.4
>
On Tue, Apr 23, 2019 at 12:50:46PM +0200, Simon Horman wrote:
> On Tue, Apr 23, 2019 at 07:09:58PM +0900, Nguyen An Hoan wrote:
> > From: Hoan Nguyen An <[email protected]>
> >
> > Add r8a77965 DRIF bindings.
> >
> > Signed-off-by: Hoan Nguyen An <[email protected]>
>
> According to the User's Manual Hardware, v1.50 Nov 20 2019,
> the DRIF IP block M3-N (r8a77965) has a BITCTR register which
> is not present on the H3 (r8a7795) or M3-W (r8a77995).
>
> Does the DRIF IP block present on the M3-N (r8a77965) function
> without support for this register in the driver?
>
> If not then I think that:
> 1) This patch should be updated to note that renesas,rcar-gen3-drif
> can only be used with H3 (r8a7795) and M3-W (r8a77995).
> 2) A driver patch is required
> 3) The DT patch, 2/2 of this series, should be updated to
> i) Not use renesas,rcar-gen3-drif
> ii) Extend the register aperture from 0x64 to 0x84.
Hi,
I'm wondering what the status of this patchset it.
>
> > ---
> > Documentation/devicetree/bindings/media/renesas,drif.txt | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/Documentation/devicetree/bindings/media/renesas,drif.txt b/Documentation/devicetree/bindings/media/renesas,drif.txt
> > index 0d8974a..16cdee3 100644
> > --- a/Documentation/devicetree/bindings/media/renesas,drif.txt
> > +++ b/Documentation/devicetree/bindings/media/renesas,drif.txt
> > @@ -41,6 +41,7 @@ Required properties of an internal channel:
> > -------------------------------------------
> > - compatible: "renesas,r8a7795-drif" if DRIF controller is a part of R8A7795 SoC.
> > "renesas,r8a7796-drif" if DRIF controller is a part of R8A7796 SoC.
> > + "renesas,r8a77965-drif" if DRIF controller is a part of R8A77965 SoC.
> > "renesas,rcar-gen3-drif" for a generic R-Car Gen3 compatible device.
> >
> > When compatible with the generic version, nodes must list the
> > --
> > 2.7.4
> >
>