by Maxime Ripard

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Subject: Re: [PATCH v3 9/9] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3

On Sun, Jun 23, 2019 at 12:38:01PM +0800, Icenowy Zheng wrote:
> Lichee zero plus is a core board made by Sipeed, which includes on-board
> TF slot or SMT SD NAND, and optional SPI NOR or eMMC, a UART debug
> header, a microUSB slot and a gold finger connector for expansion. It
> can use either Sochip S3 or Allwinner S3L SoC.
>
> Add the basic device tree for the core board, w/o optional onboard
> storage, and with S3 SoC.
>
> Signed-off-by: Icenowy Zheng <[email protected]>
> ---
> Changes in v3:
> - Drop common regulator DTSI usage and added vcc3v3 regulator.
>
> arch/arm/boot/dts/Makefile | 1 +
> .../boot/dts/sun8i-s3-lichee-zero-plus.dts | 8 ++++
> .../dts/sun8i-s3-s3l-lichee-zero-plus.dtsi | 44 +++++++++++++++++++
> 3 files changed, 53 insertions(+)
> create mode 100644 arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts
> create mode 100644 arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index c4742afe41a7..d24dec29245e 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1113,6 +1113,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
> sun8i-r16-nintendo-super-nes-classic.dtb \
> sun8i-r16-parrot.dtb \
> sun8i-r40-bananapi-m2-ultra.dtb \
> + sun8i-s3-lichee-zero-plus.dtb \
> sun8i-t3-cqa3t-bv3.dtb \
> sun8i-v3s-licheepi-zero.dtb \
> sun8i-v3s-licheepi-zero-dock.dtb \
> diff --git a/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts
> new file mode 100644
> index 000000000000..7d2f6b145190
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts
> @@ -0,0 +1,8 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Icenowy Zheng <[email protected]>
> + */
> +
> +/dts-v1/;
> +#include "sun8i-s3.dtsi"
> +#include "sun8i-s3-s3l-lichee-zero-plus.dtsi"
> diff --git a/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi
> new file mode 100644
> index 000000000000..e68f738c3046
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi
> @@ -0,0 +1,46 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Icenowy Zheng <[email protected]>
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + reg_vcc3v3: vcc3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +};
> +
> +&mmc0 {
> + broken-cd;
> + bus-width = <4>;
> + vmmc-supply = <&reg_vcc3v3>;
> + status = "okay";
> +};
> +
> +&uart0 {
> + pinctrl-0 = <&uart0_pb_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&usb_otg {
> + dr_mode = "otg";
> + status = "okay";
> +};
> +
> +&usbphy {
> + usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +};

How can it do OTG if there's no controllable VBUS regulator?

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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2019-06-24 14:12:03

by Maxime Ripard

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Subject: Re: [PATCH v3 1/9] pinctrl: sunxi: v3s: introduce support for V3

On Sun, Jun 23, 2019 at 12:37:53PM +0800, Icenowy Zheng wrote:
> Introduce the GPIO pins that is only available on V3 (not on V3s) to the
> V3s pinctrl driver.
>
> Signed-off-by: Icenowy Zheng <[email protected]>
> ---
> Changes in v3:
> - Fixed code alignment.
> - Fixed LVDS function number.
>
> Changes in v2:
> - Dropped the driver rename patch and apply the changes directly on V3s
> driver.
>
> drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 473 +++++++++++++++++-----
> drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 +
> 2 files changed, 366 insertions(+), 109 deletions(-)
>
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
> index 6704ce8e5e3d..721c997d472b 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
> @@ -1,5 +1,5 @@
> /*
> - * Allwinner V3s SoCs pinctrl driver.
> + * Allwinner V3/V3s SoCs pinctrl driver.
> *
> * Copyright (C) 2016 Icenowy Zheng <[email protected]>
> *
> @@ -28,235 +28,433 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = {
> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> - SUNXI_FUNCTION(0x2, "uart2"), /* TX */
> - SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */
> + SUNXI_FUNCTION(0x2, "uart2"), /* TX */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */

I'm not sure why all that churn is needed.

Looks good otherwise.

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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2019-06-24 14:12:17

On Mon, Jun 24, 2019 at 09:43:23PM +0800, Icenowy Zheng wrote:
> >> +&usb_otg {
> >> + dr_mode = "otg";
> >> + status = "okay";
> >> +};
> >> +
> >> +&usbphy {
> >> + usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
> >> + status = "okay";
> >> +};
> >
> >How can it do OTG if there's no controllable VBUS regulator?
>
> All 5V's are connected together, like Orange Pi Zero.

So it's a "it can't"?

And the orange pi zero says that it can only do peripheral.

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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2019-06-25 13:56:06

by Linus Walleij

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Subject: Re: [PATCH v3 5/9] dt-bindings: vendor-prefixes: add SoChip

On Sun, Jun 23, 2019 at 6:39 AM Icenowy Zheng <[email protected]> wrote:

> Shenzhen SoChip Technology Co., Ltd. is a hardware vendor that produces
> EVBs with Allwinner chips. There's also a SoC named S3 that is developed
> by Allwinner (based on Allwinner V3/V3s) but branded SoChip.
>
> Add the vendor prefix for SoChip.
>
> Signed-off-by: Icenowy Zheng <[email protected]>
> Reviewed-by: Rob Herring <[email protected]>
> ---
> No changes in v3.
>
> Changes in v2:
> - Add the review tag by Rob.

Should I apply this to the pinctrl tree? Rob?

Yours,
Linus Walleij

2019-06-25 13:59:18

by Linus Walleij

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Subject: Re: [PATCH v3 1/9] pinctrl: sunxi: v3s: introduce support for V3

On Mon, Jun 24, 2019 at 2:40 PM Maxime Ripard <[email protected]> wrote:
> On Sun, Jun 23, 2019 at 12:37:53PM +0800, Icenowy Zheng wrote:
> > Introduce the GPIO pins that is only available on V3 (not on V3s) to the
> > V3s pinctrl driver.
> >
> > Signed-off-by: Icenowy Zheng <[email protected]>
> > ---
> > Changes in v3:
> > - Fixed code alignment.
> > - Fixed LVDS function number.

> > - SUNXI_FUNCTION(0x2, "uart2"), /* TX */
> > - SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */
> > + SUNXI_FUNCTION(0x2, "uart2"), /* TX */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */
>
> I'm not sure why all that churn is needed.
>
> Looks good otherwise.

Should I apply the patch or wait for a new version without the
whitespace fixes?

Yours,
Linus Walleij

2019-06-25 14:11:04

On Sun, 23 Jun 2019 12:37:59 +0800, Icenowy Zheng wrote:
> Shenzhen?Sipeed?Technology?Co.,?Ltd. is a company focused on development
> kits, which also contains rebranded Lichee Pi series.
>
> Add its vendor prefix binding.
>
> Signed-off-by: Icenowy Zheng <[email protected]>
> ---
> Changes in v3:
> - Rebased because of the addition of sinlinx and sinovoip.
>
> Patch introduced in v2.
>
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>

Applied, thanks.

Rob