Reading the count register clears the interrupt signal. Currently, the
count registers are read into 'regval' variable but the variable is
never used. Therefore remove it.
Signed-off-by: Yash Shah <[email protected]>
---
arch/riscv/mm/sifive_l2_cache.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/mm/sifive_l2_cache.c b/arch/riscv/mm/sifive_l2_cache.c
index 4eb6461..3052a42 100644
--- a/arch/riscv/mm/sifive_l2_cache.c
+++ b/arch/riscv/mm/sifive_l2_cache.c
@@ -109,13 +109,13 @@ int unregister_sifive_l2_error_notifier(struct notifier_block *nb)
static irqreturn_t l2_int_handler(int irq, void *device)
{
- unsigned int regval, add_h, add_l;
+ unsigned int add_h, add_l;
if (irq == g_irq[DIR_CORR]) {
add_h = readl(l2_base + SIFIVE_L2_DIRECCFIX_HIGH);
add_l = readl(l2_base + SIFIVE_L2_DIRECCFIX_LOW);
pr_err("L2CACHE: DirError @ 0x%08X.%08X\n", add_h, add_l);
- regval = readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT);
+ readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT);
atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE,
"DirECCFix");
}
@@ -123,7 +123,7 @@ static irqreturn_t l2_int_handler(int irq, void *device)
add_h = readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH);
add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW);
pr_err("L2CACHE: DataError @ 0x%08X.%08X\n", add_h, add_l);
- regval = readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT);
+ readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT);
atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE,
"DatECCFix");
}
@@ -131,7 +131,7 @@ static irqreturn_t l2_int_handler(int irq, void *device)
add_h = readl(l2_base + SIFIVE_L2_DATECCFAIL_HIGH);
add_l = readl(l2_base + SIFIVE_L2_DATECCFAIL_LOW);
pr_err("L2CACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l);
- regval = readl(l2_base + SIFIVE_L2_DATECCFAIL_COUNT);
+ readl(l2_base + SIFIVE_L2_DATECCFAIL_COUNT);
atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE,
"DatECCFail");
}
--
1.9.1
On Thu, Jun 27, 2019 at 02:04:46PM +0530, Yash Shah wrote:
> Reading the count register clears the interrupt signal. Currently, the
> count registers are read into 'regval' variable but the variable is
> never used. Therefore remove it.
>
> Signed-off-by: Yash Shah <[email protected]>
> ---
> arch/riscv/mm/sifive_l2_cache.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
Unrelated note: that driver absolutely does not belong into
arch/riscv/mm. arch/$(ARCH)/mm is for architecte-specific memory
management code, not for random drivers.
On Thu, 27 Jun 2019, Yash Shah wrote:
> Reading the count register clears the interrupt signal. Currently, the
> count registers are read into 'regval' variable but the variable is
> never used. Therefore remove it.
>
> Signed-off-by: Yash Shah <[email protected]>
This is a good start. Could you also add comments in the code that
describe what those reads are doing, as you did in the patch description?
Otherwise they look pretty mysterious.
- Paul
On Thu, Jun 27, 2019 at 9:43 PM Paul Walmsley <[email protected]> wrote:
>
> On Thu, 27 Jun 2019, Yash Shah wrote:
>
> > Reading the count register clears the interrupt signal. Currently, the
> > count registers are read into 'regval' variable but the variable is
> > never used. Therefore remove it.
> >
> > Signed-off-by: Yash Shah <[email protected]>
>
> This is a good start. Could you also add comments in the code that
> describe what those reads are doing, as you did in the patch description?
> Otherwise they look pretty mysterious.
>
Sure, will add comments and send v2
>
> - Paul