Various Lantiq (now Intel) SoCs contain one or more PCIe controllers
and PHYs.
This adds a driver for the PCIe PHYs found on the Lantiq VRX200 and
ARX300 SoCs. GRX390 should also be supported as far as I can tell,
but I don't have any of these devices to further verify that.
I have tested this PCIe PHY driver with the out-of-tree PCIe controller
driver in OpenWrt: [0]
dependencies for this series:
none
patches 1-3 should go through the PHY tree
patch 4 should go through the mips tree
I am aware that this series is too late for the v5.3 development cycle.
Getting review comments is still appreciated so this can be queued early
in the v5.4 development cycle.
Changes since v1 at [1]:
- many thanks to Rob for giving me many hints regarding the .yaml bindings!
- update the .yaml binding license to (GPL-2.0-only OR BSD-2-Clause)
- changed the property lantiq,rcu to type phandle
- add the optional big-endian and little-endian boolean properties
- use numeric values for the clock phandles in the example to make the
dt_binding_check build happy
- replaced two mdelay(1); with usleep_range(1000, 2000); in patch #2
(spotted and reported by Hauke off-list)
[0] https://github.com/xdarklight/openwrt/commits/lantiq-mainline-pcie-phy-20190702
[1] https://patchwork.kernel.org/cover/11028797/
Martin Blumenstingl (4):
dt-bindings: phy: add binding for the Lantiq VRX200 and ARX300 PCIe
PHYs
phy: lantiq: vrx200-pcie: add a driver for the Lantiq VRX200 PCIe PHY
phy: enable compile-testing for the Lantiq PHY drivers
MIPS: lantiq: update the clock alias' for the mainline PCIe PHY driver
.../bindings/phy/lantiq,vrx200-pcie-phy.yaml | 95 ++++
arch/mips/lantiq/xway/sysctrl.c | 16 +-
drivers/phy/Makefile | 2 +-
drivers/phy/lantiq/Kconfig | 11 +
drivers/phy/lantiq/Makefile | 1 +
drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c | 494 ++++++++++++++++++
.../dt-bindings/phy/phy-lantiq-vrx200-pcie.h | 11 +
7 files changed, 621 insertions(+), 9 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml
create mode 100644 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c
create mode 100644 include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h
--
2.22.0
Add the bindings for the PCIe PHY on Lantiq VRX200 and ARX300 SoCs.
The IP block contains settings for the PHY and a PLL.
The PLL mode is configurable through a dedicated #phy-cell in .dts.
Signed-off-by: Martin Blumenstingl <[email protected]>
---
.../bindings/phy/lantiq,vrx200-pcie-phy.yaml | 95 +++++++++++++++++++
.../dt-bindings/phy/phy-lantiq-vrx200-pcie.h | 11 +++
2 files changed, 106 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml
create mode 100644 include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h
diff --git a/Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml
new file mode 100644
index 000000000000..8a56a8526cef
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Lantiq VRX200 and ARX300 PCIe PHY Device Tree Bindings
+
+maintainers:
+ - Martin Blumenstingl <[email protected]>
+
+properties:
+ "#phy-cells":
+ const: 1
+ description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
+
+ compatible:
+ enum:
+ - lantiq,vrx200-pcie-phy
+ - lantiq,arx300-pcie-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: PHY module clock
+ - description: PDI register clock
+
+ clock-names:
+ items:
+ - const: phy
+ - const: pdi
+
+ resets:
+ items:
+ - description: exclusive PHY reset line
+ - description: shared reset line between the PCIe PHY and PCIe controller
+
+ resets-names:
+ items:
+ - const: phy
+ - const: pcie
+
+ lantiq,rcu:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the RCU syscon
+
+ lantiq,rcu-endian-offset:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: the offset of the endian registers for this PHY instance in the RCU syscon
+
+ lantiq,rcu-big-endian-mask:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: the mask to set the PDI (PHY) registers for this PHY instance to big endian
+
+ big-endian:
+ description: Configures the PDI (PHY) registers in big-endian mode
+ type: boolean
+
+ little-endian:
+ description: Configures the PDI (PHY) registers in big-endian mode
+ type: boolean
+
+required:
+ - "#phy-cells"
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - lantiq,rcu
+ - lantiq,rcu-endian-offset
+ - lantiq,rcu-big-endian-mask
+
+additionalProperties: false
+
+examples:
+ - |
+ pcie0_phy: phy@106800 {
+ compatible = "lantiq,vrx200-pcie-phy";
+ reg = <0x106800 0x100>;
+ lantiq,rcu = <&rcu0>;
+ lantiq,rcu-endian-offset = <0x4c>;
+ lantiq,rcu-big-endian-mask = <0x80>; /* bit 7 */
+ big-endian;
+ clocks = <&pmu 32>, <&pmu 36>;
+ clock-names = "phy", "pdi";
+ resets = <&reset0 12 24>, <&reset0 22 22>;
+ reset-names = "phy", "pcie";
+ #phy-cells = <1>;
+ };
+
+...
diff --git a/include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h b/include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h
new file mode 100644
index 000000000000..95a7896356d6
--- /dev/null
+++ b/include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2019 Martin Blumenstingl <[email protected]>
+ */
+
+#define LANTIQ_PCIE_PHY_MODE_25MHZ 0
+#define LANTIQ_PCIE_PHY_MODE_25MHZ_SSC 1
+#define LANTIQ_PCIE_PHY_MODE_36MHZ 2
+#define LANTIQ_PCIE_PHY_MODE_36MHZ_SSC 3
+#define LANTIQ_PCIE_PHY_MODE_100MHZ 4
+#define LANTIQ_PCIE_PHY_MODE_100MHZ_SSC 5
--
2.22.0
Unconditionally include the lantiq subdirectory in the phy Makefile.
All drivers in there have their dependencies maintained. One of these
(optional) dependencies is COMPILE_TEST, however this can only be
evaluated when Kconfig scans the lantiq subdirectory.
Signed-off-by: Martin Blumenstingl <[email protected]>
---
drivers/phy/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 0d9fddc498a6..c96a1afc95bd 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -10,7 +10,6 @@ obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
obj-$(CONFIG_ARCH_SUNXI) += allwinner/
obj-$(CONFIG_ARCH_MESON) += amlogic/
-obj-$(CONFIG_LANTIQ) += lantiq/
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_ARCH_RENESAS) += renesas/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
@@ -19,6 +18,7 @@ obj-y += broadcom/ \
cadence/ \
freescale/ \
hisilicon/ \
+ lantiq/ \
marvell/ \
motorola/ \
mscc/ \
--
2.22.0
On Thu, Jul 4, 2019 at 6:23 AM Martin Blumenstingl
<[email protected]> wrote:
>
> Add the bindings for the PCIe PHY on Lantiq VRX200 and ARX300 SoCs.
> The IP block contains settings for the PHY and a PLL.
> The PLL mode is configurable through a dedicated #phy-cell in .dts.
>
> Signed-off-by: Martin Blumenstingl <[email protected]>
> ---
> .../bindings/phy/lantiq,vrx200-pcie-phy.yaml | 95 +++++++++++++++++++
> .../dt-bindings/phy/phy-lantiq-vrx200-pcie.h | 11 +++
> 2 files changed, 106 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml
> create mode 100644 include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h
Reviewed-by: Rob Herring <[email protected]>
On Thu, Jul 4, 2019 at 7:23 AM Martin Blumenstingl
<[email protected]> wrote:
>
> Add the bindings for the PCIe PHY on Lantiq VRX200 and ARX300 SoCs.
> The IP block contains settings for the PHY and a PLL.
> The PLL mode is configurable through a dedicated #phy-cell in .dts.
>
> Signed-off-by: Martin Blumenstingl <[email protected]>
> ---
> .../bindings/phy/lantiq,vrx200-pcie-phy.yaml | 95 +++++++++++++++++++
> .../dt-bindings/phy/phy-lantiq-vrx200-pcie.h | 11 +++
> 2 files changed, 106 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml
> create mode 100644 include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h
>
> diff --git a/Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml
> new file mode 100644
> index 000000000000..8a56a8526cef
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml
> @@ -0,0 +1,95 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Lantiq VRX200 and ARX300 PCIe PHY Device Tree Bindings
> +
> +maintainers:
> + - Martin Blumenstingl <[email protected]>
> +
> +properties:
> + "#phy-cells":
> + const: 1
> + description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
> +
> + compatible:
> + enum:
> + - lantiq,vrx200-pcie-phy
> + - lantiq,arx300-pcie-phy
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: PHY module clock
> + - description: PDI register clock
> +
> + clock-names:
> + items:
> + - const: phy
> + - const: pdi
> +
> + resets:
> + items:
> + - description: exclusive PHY reset line
> + - description: shared reset line between the PCIe PHY and PCIe controller
> +
> + resets-names:
This breaks 'make dt_binding_check'. It should be 'reset-names'.
Rob
Hi Rob,
On Wed, Oct 2, 2019 at 4:37 PM Rob Herring <[email protected]> wrote:
>
> On Thu, Jul 4, 2019 at 7:23 AM Martin Blumenstingl
> <[email protected]> wrote:
> >
> > Add the bindings for the PCIe PHY on Lantiq VRX200 and ARX300 SoCs.
> > The IP block contains settings for the PHY and a PLL.
> > The PLL mode is configurable through a dedicated #phy-cell in .dts.
> >
> > Signed-off-by: Martin Blumenstingl <[email protected]>
> > ---
> > .../bindings/phy/lantiq,vrx200-pcie-phy.yaml | 95 +++++++++++++++++++
> > .../dt-bindings/phy/phy-lantiq-vrx200-pcie.h | 11 +++
> > 2 files changed, 106 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml
> > create mode 100644 include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h
> >
> > diff --git a/Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml
> > new file mode 100644
> > index 000000000000..8a56a8526cef
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml
> > @@ -0,0 +1,95 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Lantiq VRX200 and ARX300 PCIe PHY Device Tree Bindings
> > +
> > +maintainers:
> > + - Martin Blumenstingl <[email protected]>
> > +
> > +properties:
> > + "#phy-cells":
> > + const: 1
> > + description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
> > +
> > + compatible:
> > + enum:
> > + - lantiq,vrx200-pcie-phy
> > + - lantiq,arx300-pcie-phy
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: PHY module clock
> > + - description: PDI register clock
> > +
> > + clock-names:
> > + items:
> > + - const: phy
> > + - const: pdi
> > +
> > + resets:
> > + items:
> > + - description: exclusive PHY reset line
> > + - description: shared reset line between the PCIe PHY and PCIe controller
> > +
> > + resets-names:
>
> This breaks 'make dt_binding_check'. It should be 'reset-names'.
sorry for the typo
Maxime has already fixed this (thank you!) and the fix has already
landed in 5.4-rc2 with f437ade3296bacaddb6d7882ba0515940f01daf4
Martin