Zhaoxin newer CPUs support LMCE that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin LMCE
in mce/core.c.
Signed-off-by: Tony W Wang-oc <[email protected]>
---
arch/x86/include/asm/mce.h | 2 ++
arch/x86/kernel/cpu/mce/core.c | 25 +++++++++++++++++++++++--
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 0986a11..01840ec 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -352,8 +352,10 @@ static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_am
#ifdef CONFIG_CPU_SUP_ZHAOXIN
void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c);
+void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c);
#else
static inline void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) { }
+static inline void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) { }
#endif
#endif /* _ASM_X86_MCE_H */
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index a3b07ca..857570f 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1129,6 +1129,17 @@ static bool __mc_check_crashing_cpu(int cpu)
u64 mcgstatus;
mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
+
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {
+ if (mcgstatus & MCG_STATUS_LMCES) {
+ return false;
+ } else {
+ if (mcgstatus & MCG_STATUS_RIPV)
+ mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
+ return true;
+ }
+ }
+
if (mcgstatus & MCG_STATUS_RIPV) {
mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
return true;
@@ -1279,9 +1290,10 @@ void do_machine_check(struct pt_regs *regs, long error_code)
/*
* Check if this MCE is signaled to only this logical processor,
- * on Intel only.
+ * on Intel, Zhaoxin only.
*/
- if (m.cpuvendor == X86_VENDOR_INTEL)
+ if (m.cpuvendor == X86_VENDOR_INTEL ||
+ m.cpuvendor == X86_VENDOR_ZHAOXIN)
lmce = m.mcgstatus & MCG_STATUS_LMCES;
/*
@@ -1795,9 +1807,15 @@ void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
}
intel_init_cmci();
+ intel_init_lmce();
mce_adjust_timer = cmci_intel_adjust_timer;
}
+void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)
+{
+ intel_clear_lmce();
+}
+
static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
{
switch (c->x86_vendor) {
@@ -1834,6 +1852,9 @@ static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c)
case X86_VENDOR_INTEL:
mce_intel_feature_clear(c);
break;
+ case X86_VENDOR_ZHAOXIN:
+ mce_zhaoxin_feature_clear(c);
+ break;
default:
break;
}
--
2.7.4
Hi Tony,
I love your patch! Yet something to improve:
[auto build test ERROR on linus/master]
[cannot apply to v5.3-rc8 next-20190904]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Tony-W-Wang-oc/x86-mce-Add-Zhaoxin-MCE-support/20190909-190435
config: i386-randconfig-b002-201936 (attached as .config)
compiler: gcc-7 (Debian 7.4.0-11) 7.4.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <[email protected]>
All errors (new ones prefixed by >>):
arch/x86//kernel/cpu/mce/core.c:1792:6: error: redefinition of 'mce_zhaoxin_feature_init'
void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
^~~~~~~~~~~~~~~~~~~~~~~~
In file included from arch/x86//kernel/cpu/mce/core.c:50:0:
arch/x86/include/asm/mce.h:357:20: note: previous definition of 'mce_zhaoxin_feature_init' was here
static inline void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) { }
^~~~~~~~~~~~~~~~~~~~~~~~
>> arch/x86//kernel/cpu/mce/core.c:1814:6: error: redefinition of 'mce_zhaoxin_feature_clear'
void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)
^~~~~~~~~~~~~~~~~~~~~~~~~
In file included from arch/x86//kernel/cpu/mce/core.c:50:0:
arch/x86/include/asm/mce.h:358:20: note: previous definition of 'mce_zhaoxin_feature_clear' was here
static inline void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) { }
^~~~~~~~~~~~~~~~~~~~~~~~~
vim +/mce_zhaoxin_feature_clear +1814 arch/x86//kernel/cpu/mce/core.c
1791
> 1792 void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
1793 {
1794 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1795
1796 /*
1797 * These CPUs bank8 SVAD error may be triggered unexpected when
1798 * bringup virtual machine. it is not hardware bug. Always disable
1799 * bank8 SVAD error by default.
1800 */
1801 if ((c->x86 == 6 && c->x86_model == 0x19 &&
1802 (c->x86_stepping > 3 && c->x86_stepping < 8)) ||
1803 (c->x86 == 6 && c->x86_model == 0x1f) ||
1804 (c->x86 == 7 && c->x86_model == 0x1b)) {
1805 if (this_cpu_read(mce_num_banks) > 8)
1806 mce_banks[8].ctl = 0;
1807 }
1808
1809 intel_init_cmci();
1810 intel_init_lmce();
1811 mce_adjust_timer = cmci_intel_adjust_timer;
1812 }
1813
> 1814 void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)
1815 {
1816 intel_clear_lmce();
1817 }
1818
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation