Add basic dts support for a Advantech iMX8QM Qseven Board
Signed-off-by: Oliver Graute <[email protected]>
---
Changelog:
v4:
- added reg_usdhc3_vmmc node
- added usdhc3 node
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../boot/dts/freescale/imx8qm-rom7720-a1.dts | 299 ++++++++++++++++++
2 files changed, 300 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 93fce8f0c66d..0de6d384b5ea 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -30,5 +30,6 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8qm-rom7720-a1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts b/arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts
new file mode 100644
index 000000000000..b7b6f96f224c
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+* Copyright 2017-2018 NXP
+* Copyright (C) 2019 Oliver Graute <[email protected]>
+*/
+/dts-v1/;
+
+#include "imx8qm.dtsi"
+
+/ {
+ model = "Advantech iMX8QM Qseven series";
+ compatible = "fsl,imx8qm";
+
+ board {
+ compatible = "proc-board";
+ board-type = "ROM-7720_A1";
+ board-cpu = "iMX8QM";
+ };
+
+ chosen {
+ bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
+ stdout-path = &lpuart0;
+ };
+
+ cpus {
+ /delete-node/ cpu-map;
+ /delete-node/ cpu@100;
+ /delete-node/ cpu@101;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0 0x40000000>;
+ };
+
+ reg_usdhc2_vmmc: usdhc2_vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "sw-3p3-sd1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>;
+ off-on-delay = <3000>;
+ enable-active-high;
+ };
+
+ reg_usdhc3_vmmc: usdhc3_vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "sw-3p3-sd2";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&lsio_gpio4 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+};
+
+&lpuart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart0>;
+ status = "okay";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-txid";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ fsl,rgmii_rxc_dly;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <4>;
+ at803x,eee-disabled;
+ at803x,vddio-1p8v;
+ };
+ };
+};
+
+&lsio_gpio4 {
+ status = "okay";
+};
+
+&lsio_gpio5 {
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ bus-width = <4>;
+ cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
+ bus-width = <4>;
+ cd-gpios = <&lsio_gpio4 12 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&lsio_gpio4 11 GPIO_ACTIVE_HIGH>;
+ vmmc-supply = <®_usdhc3_vmmc>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0
+ IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020
+ IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
+ IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060
+ IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060
+ IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060
+ IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060
+ IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060
+ IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060
+ IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060
+ IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060
+ IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060
+ IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060
+ IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060
+ IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060
+ >;
+ };
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ IMX8QM_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048
+ >;
+ };
+
+ pinctrl_lpuart0: lpuart0grp {
+ fsl,pins = <
+ IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020
+ IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
+ IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
+ IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
+ IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
+ IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
+ IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
+ IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
+ IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
+ IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
+ IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
+ IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
+ IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
+ IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
+ IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
+ IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
+ IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
+ IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
+ IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
+ IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
+ IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
+ IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
+ IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
+ IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
+ IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
+ IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
+ IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
+ IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
+ IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
+ IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
+ IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
+ IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
+ IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
+ IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ fsl,pins = <
+ IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021
+ IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021
+ IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
+ IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
+ IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
+ IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
+ IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
+ IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
+ IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
+ IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
+ IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
+ IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
+ IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
+ IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
+ IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
+ IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
+ IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
+ IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
+ IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
+ IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
+ IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041
+ IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021
+ IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021
+ IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021
+ IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021
+ IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021
+ IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021
+ >;
+ };
+
+ pinctrl_usdhc3_gpio: usdhc3grpgpio {
+ fsl,pins = <
+ IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021
+ IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021
+ IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x00000021
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+ fsl,pins = <
+ IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
+ IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
+ IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
+ IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
+ IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
+ IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
+ IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+ fsl,pins = <
+ IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
+ IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
+ IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
+ IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
+ IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
+ IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
+ IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
+ >;
+ };
+};
--
2.17.1
Hi Oliver,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on v5.4-rc5 next-20191025]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Oliver-Graute/arm64-dts-add-basic-DTS-for-imx8qm-rom7720-board/20191028-060303
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-defconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 7.4.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.4.0 make.cross ARCH=arm64
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <[email protected]>
All errors (new ones prefixed by >>):
>> arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts:8:10: fatal error: imx8qm.dtsi: No such file or directory
8 | #include "imx8qm.dtsi"
| ^~~~~~~~~~~~~
compilation terminated.
vim +8 arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts
7
> 8 #include "imx8qm.dtsi"
9
---
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