Hi all,
below is a series to support nommu mode on RISC-V. For now this series
just works under qemu with the qemu-virt platform, but Damien has also
been able to get kernel based on this tree with additional driver hacks
to work on the Kendryte KD210, but that will take a while to cleanup
an upstream.
A git tree is available here:
git://git.infradead.org/users/hch/riscv.git riscv-nommu.6
Gitweb:
http://git.infradead.org/users/hch/riscv.git/shortlog/refs/heads/riscv-nommu.6
I've also pushed out a builtroot branch that can build a RISC-V nommu
root filesystem here:
git://git.infradead.org/users/hch/buildroot.git riscv-nommu.2
Gitweb:
http://git.infradead.org/users/hch/buildroot.git/shortlog/refs/heads/riscv-nommu.2
Changes since v5:
- rebased to Linux 5.4-rc5
- fix up a newly sneaked in use of ->sepc in the perf callchain code
- fix out of tree builds with the generated loader.lds
- replace the plic context hack with a cleaner solution
Changes since v4:
- rebased to 5.4-rc + latest riscv fixes
- clean up do_trap_break
- fix an SR_XPIE issue (Paul Walmsley)
- use the symbolic PAGE_OFFSET value in the flat loader
(Aurabindo Jayamohanan)
Changes since v3:
- improve a few commit message
- cleanup riscv_cpuid_to_hartid_mask
- cleanup the timer handling
- cleanup the IPI handling a little more
- renamed CONFIG_M_MODE to CONFIG_RISCV_M_MODE
- split out CONFIG_RISCV_SBI to make some of the ifdefs more obbious
- use IS_ENABLED wherever possible instead of if ifdefs to make the
code more readable
Changes since v2:
- rebased to 5.3-rc
- remove the EFI image header for nommu builds
- set ARCH_SLAB_MINALIGN to ensure stack alignment in the flat binary
loader
- minor comment improvement
- use #defines for more CSRs
Changes since v1:
- fixes so that a kernel with this series still work on builds with an
IOMMU
- small clint cleanups
- the binfmt_flat base and buildroot now don't put arguments on the stack
There is no SBI when we run in M-mode, so fail the compile for any code
trying to use SBI calls.
Signed-off-by: Christoph Hellwig <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
---
arch/riscv/include/asm/sbi.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 21134b3ef404..b167af3e7470 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -8,6 +8,7 @@
#include <linux/types.h>
+#ifdef CONFIG_RISCV_SBI
#define SBI_SET_TIMER 0
#define SBI_CONSOLE_PUTCHAR 1
#define SBI_CONSOLE_GETCHAR 2
@@ -93,5 +94,5 @@ static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
{
SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid);
}
-
-#endif
+#endif /* CONFIG_RISCV_SBI */
+#endif /* _ASM_RISCV_SBI_H */
--
2.20.1
When running in M-mode we can't use the SBI to set the timer, and
don't have access to the time CSR as that usually is emulated by
M-mode. Instead provide code that directly accesses the MMIO for
the timer.
Signed-off-by: Christoph Hellwig <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
---
arch/riscv/include/asm/sbi.h | 3 ++-
arch/riscv/include/asm/timex.h | 19 +++++++++++++++++--
drivers/clocksource/timer-riscv.c | 21 +++++++++++++++++----
3 files changed, 36 insertions(+), 7 deletions(-)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 0cb74eccc73f..a4774bafe033 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -95,7 +95,8 @@ static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid);
}
#else /* CONFIG_RISCV_SBI */
-/* stub to for code is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */
+/* stubs to for code is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */
+void sbi_set_timer(uint64_t stime_value);
void sbi_remote_fence_i(const unsigned long *hart_mask);
#endif /* CONFIG_RISCV_SBI */
#endif /* _ASM_RISCV_SBI_H */
diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h
index c7ef131b9e4c..e17837d61667 100644
--- a/arch/riscv/include/asm/timex.h
+++ b/arch/riscv/include/asm/timex.h
@@ -7,12 +7,25 @@
#define _ASM_RISCV_TIMEX_H
#include <asm/csr.h>
+#include <asm/io.h>
typedef unsigned long cycles_t;
+extern u64 __iomem *riscv_time_val;
+extern u64 __iomem *riscv_time_cmp;
+
+#ifdef CONFIG_64BIT
+#define mmio_get_cycles() readq_relaxed(riscv_time_val)
+#else
+#define mmio_get_cycles() readl_relaxed(riscv_time_val)
+#define mmio_get_cycles_hi() readl_relaxed(((u32 *)riscv_time_val) + 1)
+#endif
+
static inline cycles_t get_cycles(void)
{
- return csr_read(CSR_TIME);
+ if (IS_ENABLED(CONFIG_RISCV_SBI))
+ return csr_read(CSR_TIME);
+ return mmio_get_cycles();
}
#define get_cycles get_cycles
@@ -24,7 +37,9 @@ static inline u64 get_cycles64(void)
#else /* CONFIG_64BIT */
static inline u32 get_cycles_hi(void)
{
- return csr_read(CSR_TIMEH);
+ if (IS_ENABLED(CONFIG_RISCV_SBI))
+ return csr_read(CSR_TIMEH);
+ return mmio_get_cycles_hi();
}
static inline u64 get_cycles64(void)
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index d083bfb535f6..f3eb0c04401a 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -3,9 +3,9 @@
* Copyright (C) 2012 Regents of the University of California
* Copyright (C) 2017 SiFive
*
- * All RISC-V systems have a timer attached to every hart. These timers can be
- * read from the "time" and "timeh" CSRs, and can use the SBI to setup
- * events.
+ * All RISC-V systems have a timer attached to every hart. These timers can
+ * either be read from the "time" and "timeh" CSRs, and can use the SBI to
+ * setup events, or directly accessed using MMIO registers.
*/
#include <linux/clocksource.h>
#include <linux/clockchips.h>
@@ -13,14 +13,27 @@
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/sched_clock.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
#include <asm/smp.h>
#include <asm/sbi.h>
+u64 __iomem *riscv_time_cmp;
+u64 __iomem *riscv_time_val;
+
+static inline void mmio_set_timer(u64 val)
+{
+ writeq_relaxed(val,
+ riscv_time_cmp + cpuid_to_hartid_map(smp_processor_id()));
+}
+
static int riscv_clock_next_event(unsigned long delta,
struct clock_event_device *ce)
{
csr_set(CSR_IE, IE_TIE);
- sbi_set_timer(get_cycles64() + delta);
+ if (IS_ENABLED(CONFIG_RISCV_SBI))
+ sbi_set_timer(get_cycles64() + delta);
+ else
+ mmio_set_timer(get_cycles64() + delta);
return 0;
}
--
2.20.1
This allows just loading the kernel at a pre-set address without
qemu going bonkers trying to map the ELF file.
Contains a controbution from Aurabindo Jayamohanan to reuse the
PAGE_OFFSET definition.
Signed-off-by: Christoph Hellwig <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
---
arch/riscv/Makefile | 13 +++++++++----
arch/riscv/boot/Makefile | 7 ++++++-
arch/riscv/boot/loader.S | 8 ++++++++
arch/riscv/boot/loader.lds.S | 16 ++++++++++++++++
4 files changed, 39 insertions(+), 5 deletions(-)
create mode 100644 arch/riscv/boot/loader.S
create mode 100644 arch/riscv/boot/loader.lds.S
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index f5e914210245..b9009a2fbaf5 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -83,13 +83,18 @@ PHONY += vdso_install
vdso_install:
$(Q)$(MAKE) $(build)=arch/riscv/kernel/vdso $@
-all: Image.gz
+ifeq ($(CONFIG_RISCV_M_MODE),y)
+KBUILD_IMAGE := $(boot)/loader
+else
+KBUILD_IMAGE := $(boot)/Image.gz
+endif
+BOOT_TARGETS := Image Image.gz loader
-Image: vmlinux
- $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
+all: $(notdir $(KBUILD_IMAGE))
-Image.%: Image
+$(BOOT_TARGETS): vmlinux
$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
+ @$(kecho) ' Kernel: $(boot)/$@ is ready'
zinstall install:
$(Q)$(MAKE) $(build)=$(boot) $@
diff --git a/arch/riscv/boot/Makefile b/arch/riscv/boot/Makefile
index 0990a9fdbe5d..433ccbcabb23 100644
--- a/arch/riscv/boot/Makefile
+++ b/arch/riscv/boot/Makefile
@@ -16,7 +16,7 @@
OBJCOPYFLAGS_Image :=-O binary -R .note -R .note.gnu.build-id -R .comment -S
-targets := Image
+targets := Image loader
$(obj)/Image: vmlinux FORCE
$(call if_changed,objcopy)
@@ -24,6 +24,11 @@ $(obj)/Image: vmlinux FORCE
$(obj)/Image.gz: $(obj)/Image FORCE
$(call if_changed,gzip)
+loader.o: $(src)/loader.S $(obj)/Image
+
+$(obj)/loader: $(obj)/loader.o $(obj)/Image $(obj)/loader.lds FORCE
+ $(Q)$(LD) -T $(obj)/loader.lds -o $@ $(obj)/loader.o
+
install:
$(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
$(obj)/Image System.map "$(INSTALL_PATH)"
diff --git a/arch/riscv/boot/loader.S b/arch/riscv/boot/loader.S
new file mode 100644
index 000000000000..5586e2610dbb
--- /dev/null
+++ b/arch/riscv/boot/loader.S
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+
+ .align 4
+ .section .payload, "ax", %progbits
+ .globl _start
+_start:
+ .incbin "arch/riscv/boot/Image"
+
diff --git a/arch/riscv/boot/loader.lds.S b/arch/riscv/boot/loader.lds.S
new file mode 100644
index 000000000000..47a5003c2e28
--- /dev/null
+++ b/arch/riscv/boot/loader.lds.S
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#include <asm/page.h>
+
+OUTPUT_ARCH(riscv)
+ENTRY(_start)
+
+SECTIONS
+{
+ . = PAGE_OFFSET;
+
+ .payload : {
+ *(.payload)
+ . = ALIGN(8);
+ }
+}
--
2.20.1
From: Damien Le Moal <[email protected]>
When in M-Mode, we can use the mhartid CSR to get the ID of the running
HART. Doing so, direct M-Mode boot without firmware is possible.
Signed-off-by: Damien Le Moal <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Signed-off-by: Christoph Hellwig <[email protected]>
---
arch/riscv/include/asm/csr.h | 1 +
arch/riscv/kernel/head.S | 8 ++++++++
2 files changed, 9 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 0ab642811028..318192c66fd8 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -99,6 +99,7 @@
#define CSR_MCAUSE 0x342
#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
+#define CSR_MHARTID 0xf14
#ifdef CONFIG_RISCV_M_MODE
# define CSR_STATUS CSR_MSTATUS
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 5cfd2c582945..fc9973086946 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -50,6 +50,14 @@ _start_kernel:
csrw CSR_IE, zero
csrw CSR_IP, zero
+#ifdef CONFIG_RISCV_M_MODE
+ /*
+ * The hartid in a0 is expected later on, and we have no firmware
+ * to hand it to us.
+ */
+ csrr a0, CSR_MHARTID
+#endif
+
/* Load the global pointer */
.option push
.option norelax
--
2.20.1
Hi Christoph,
On Mon, 28 Oct 2019, Christoph Hellwig wrote:
> below is a series to support nommu mode on RISC-V. For now this series
> just works under qemu with the qemu-virt platform, but Damien has also
> been able to get kernel based on this tree with additional driver hacks
> to work on the Kendryte KD210, but that will take a while to cleanup
> an upstream.
>
> A git tree is available here:
>
> git://git.infradead.org/users/hch/riscv.git riscv-nommu.6
[ ... ]
> I've also pushed out a builtroot branch that can build a RISC-V nommu
> root filesystem here:
>
> git://git.infradead.org/users/hch/buildroot.git riscv-nommu.2
[ ... ]
I tried building this series from your git branch mentioned above, and
booted it with a buildroot userspace built from your custom buildroot
tree. Am seeing some segmentation faults from userspace (below).
Am still planning to merge your patches.
But I'm wondering whether you are seeing these segmentation faults also?
Or is it something that might be specific to my test setup?
- Paul
[ 0.000000] Linux version 5.4.0-rc5-00012-gb66bae191a9b (paulw@pjw-001) (gcc version 9.2.1 20190909 (Debian 9.2.1-8)) #64 SMP Wed Oct 30 13:09:11 PDT 2019
[ 0.000000] earlycon: uart8250 at MMIO 0x0000000010000000 (options '115200n8')
[ 0.000000] printk: bootconsole [uart8250] enabled
[ 0.000000] initrd not found or empty - disabling initrd
[ 0.000000] Zone ranges:
[ 0.000000] DMA32 [mem 0x0000000080000000-0x0000000083ffffff]
[ 0.000000] Normal empty
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000080000000-0x0000000083ffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x0000000083ffffff]
[ 0.000000] elf_hwcap is 0x112d
[ 0.000000] percpu: max_distance=0x18000 too large for vmalloc space 0x0
[ 0.000000] percpu: Embedded 12 pages/cpu s18080 r0 d31072 u49152
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 16160
[ 0.000000] Kernel command line: root=/dev/vda rw earlycon=uart8250,mmio,0x10000000,115200n8 console=ttyS0
[ 0.000000] Dentry cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
[ 0.000000] Inode-cache hash table entries: 4096 (order: 3, 32768 bytes, linear)
[ 0.000000] Sorting __ex_table...
[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[ 0.000000] Memory: 62820K/65536K available (1068K kernel code, 117K rwdata, 189K rodata, 97K init, 126K bss, 2716K reserved, 0K cma-reserved)
[ 0.000000] rcu: Hierarchical RCU implementation.
[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=2.
[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
[ 0.000000] plic: mapped 53 interrupts with 2 handlers for 4 contexts.
[ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [1]
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x24e6a1710, max_idle_ns: 440795202120 ns
[ 0.000206] sched_clock: 64 bits at 10MHz, resolution 100ns, wraps every 4398046511100ns
[ 0.004614] Console: colour dummy device 80x25
[ 0.009015] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=40000)
[ 0.010069] pid_max: default: 4096 minimum: 301
[ 0.011429] Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear)
[ 0.012301] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear)
[ 0.040643] rcu: Hierarchical SRCU implementation.
[ 0.043654] smp: Bringing up secondary CPUs ...
[ 0.048887] smp: Brought up 1 node, 2 CPUs
[ 0.060191] devtmpfs: initialized
[ 0.069148] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[ 0.070136] futex hash table entries: 16 (order: -2, 1024 bytes, linear)
[ 0.096905] clocksource: Switched to clocksource riscv_clocksource
[ 0.130551] workingset: timestamp_bits=62 max_order=14 bucket_order=0
[ 0.135947] Serial: 8250/16550 driver, 1 ports, IRQ sharing disabled
[ 0.144355] printk: console [ttyS0] disabled
[ 0.145926] 10000000.uart: ttyS0 at MMIO 0x10000000 (irq = 10, base_baud = 230400) is a 16550A
[ 0.147596] printk: console [ttyS0] enabled
[ 0.147596] printk: console [ttyS0] enabled
[ 0.148466] printk: bootconsole [uart8250] disabled
[ 0.148466] printk: bootconsole [uart8250] disabled
[ 0.163272] virtio_blk virtio0: [vda] 122880 512-byte logical blocks (62.9 MB/60.0 MiB)
[ 0.169270] random: get_random_bytes called from 0x000000008001d068 with crng_init=0
[ 0.189781] EXT2-fs (vda): warning: mounting unchecked fs, running e2fsck is recommended
[ 0.192221] VFS: Mounted root (ext2 filesystem) on device 254:0.
[ 0.195277] devtmpfs: mounted
[ 0.207866] Freeing unused kernel memory: 96K
[ 0.208270] This architecture does not have kernel memory protection.
[ 0.209017] Run /sbin/init as init process
[ 0.255239] mount[24]: unhandled signal 11 code 0x2 at 0x00000000836000e4
[ 0.256504] CPU: 1 PID: 24 Comm: mount Not tainted 5.4.0-rc5-00012-gb66bae191a9b #64
[ 0.257783] epc: 00000000836000e4 ra : 000000008361c1d8 sp : 000000008368adb0
[ 0.258718] gp : 0000000083671300 tp : 0000000000000000 t0 : 0000000000000032
[ 0.259482] t1 : 8101010101010100 t2 : 0000000000000007 s0 : 0000000000000001
[ 0.260566] s1 : 0000000000000001 a0 : 0000000000000000 a1 : 000000008368af96
[ 0.261521] a2 : 000000008368af8c a3 : 0000000000008000 a4 : 0000000000000000
[ 0.262270] a5 : 0000000000084000 a6 : 78fef8fefefcf8f8 a7 : 0000000000000028
[ 0.263215] s2 : 0000000083683fd0 s3 : fffffffffffffff8 s4 : 0000000083625dcc
[ 0.264160] s5 : 0000000000000001 s6 : 0000000000000001 s7 : 0000000000000001
[ 0.265075] s8 : 0000000000000000 s9 : 0000000000000000 s10: 0000000000000000
[ 0.266009] s11: 0000000000000000 t3 : 000000000000003d t4 : 000000000000002b
[ 0.267201] t5 : 0000000000000002 t6 : 0000000000000001
[ 0.267957] status: 0000000000004080 badaddr: 0000000000084010 cause: 0000000000000005
[ 0.300301] mount[25]: unhandled signal 11 code 0x2 at 0x00000000836000e4
[ 0.301112] CPU: 1 PID: 25 Comm: mount Not tainted 5.4.0-rc5-00012-gb66bae191a9b #64
[ 0.301888] epc: 00000000836000e4 ra : 000000008361c1d8 sp : 000000008368adc0
[ 0.302530] gp : 0000000083671300 tp : 0000000000000000 t0 : 0000000000000200
[ 0.303192] t1 : 8101010101010100 t2 : 0000000000000007 s0 : 0000000000000001
[ 0.303847] s1 : 0000000000000001 a0 : 0000000000000000 a1 : 00000000836866b6
[ 0.304518] a2 : 00000000836866b8 a3 : 0000000000208020 a4 : 0000000000000000
[ 0.305371] a5 : 0000000000084000 a6 : 80fefcf8fcf0f8fe a7 : 0000000000000028
[ 0.306045] s2 : 0000000083683fd0 s3 : fffffffffffffff8 s4 : 0000000083625dcc
[ 0.306714] s5 : 0000000000000001 s6 : 0000000000000001 s7 : 0000000000000001
[ 0.307378] s8 : 0000000000000000 s9 : 0000000000000000 s10: 0000000000000000
[ 0.308029] s11: 0000000000000000 t3 : 0000000083674474 t4 : 0000000000000000
[ 0.308885] t5 : 0000000000000001 t6 : 0000000000000100
[ 0.309727] status: 0000000000004080 badaddr: 0000000000084010 cause: 0000000000000005
[ 0.324586] mkdir[27]: unhandled signal 11 code 0x2 at 0x00000000836000e4
[ 0.325692] CPU: 1 PID: 27 Comm: mkdir Not tainted 5.4.0-rc5-00012-gb66bae191a9b #64
[ 0.326902] epc: 00000000836000e4 ra : 000000008361c1d8 sp : 000000008368adb0
[ 0.328001] gp : 0000000083671300 tp : 0000000000000000 t0 : 0000000000000003
[ 0.329058] t1 : 8101010101010100 t2 : 0000000000000007 s0 : 0000000000000001
[ 0.330086] s1 : 0000000000000001 a0 : 0000000000000000 a1 : 000000008368af93
[ 0.331186] a2 : 00000000000001ff a3 : 0000000000000000 a4 : 0000000000000000
[ 0.332312] a5 : 0000000000084000 a6 : 0000000083686320 a7 : 0000000000000022
[ 0.333299] s2 : 0000000083683fd0 s3 : fffffffffffffff8 s4 : 0000000083625dcc
[ 0.334445] s5 : 0000000000000001 s6 : 0000000000000001 s7 : 0000000000000001
[ 0.335564] s8 : 0000000000000000 s9 : 0000000000000000 s10: 0000000000000000
[ 0.336671] s11: 0000000000000000 t3 : 0000000083674474 t4 : 0000000000000000
[ 0.337603] t5 : 0000000000000018 t6 : 2f20730000000000
[ 0.338302] status: 0000000000004080 badaddr: 0000000000084010 cause: 0000000000000005
[ 0.402732] mount[28]: unhandled signal 11 code 0x2 at 0x00000000836000e4
[ 0.405458] CPU: 1 PID: 28 Comm: mount Not tainted 5.4.0-rc5-00012-gb66bae191a9b #64
[ 0.406238] epc: 00000000836000e4 ra : 000000008361c1d8 sp : 000000008368add0
[ 0.406894] gp : 0000000083671300 tp : 0000000000000000 t0 : 0000000000000000
[ 0.407561] t1 : 000000008359d038 t2 : 0000000000000009 s0 : 0000000000000001
[ 0.408269] s1 : 0000000000000001 a0 : 0000000000000000 a1 : 00000000000001fb
[ 0.409161] a2 : 0000000083670b60 a3 : 00000000000001fc a4 : 0000000000000000
[ 0.409879] a5 : 0000000000084000 a6 : 0000000000000fc8 a7 : 000000000000003f
[ 0.410589] s2 : 0000000083683fd0 s3 : fffffffffffffff8 s4 : 0000000083625dcc
[ 0.411284] s5 : 0000000000000001 s6 : 0000000000000001 s7 : 0000000000000001
[ 0.411973] s8 : 0000000000000000 s9 : 0000000000000000 s10: 0000000000000000
[ 0.412678] s11: 0000000000000000 t3 : 1999999999999999 t4 : 00000000836863cc
[ 0.413489] t5 : 0000000000000005 t6 : 0000000000000000
[ 0.414040] status: 0000000000004080 badaddr: 0000000000084010 cause: 0000000000000005
can't run '/sbin/swapon': No such file or directory
[ 0.456229] ln[30]: unhandled signal 11 code 0x2 at 0x00000000837000e4
[ 0.457222] CPU: 1 PID: 30 Comm: ln Not tainted 5.4.0-rc5-00012-gb66bae191a9b #64
[ 0.458355] epc: 00000000837000e4 ra : 000000008371c1d8 sp : 000000008378adb0
[ 0.459242] gp : 0000000083771300 tp : 0000000000000000 t0 : 0000000000000031
[ 0.459904] t1 : 8101010101010100 t2 : 0000000000000007 s0 : 0000000000000001
[ 0.460576] s1 : 0000000000000001 a0 : 0000000000000000 a1 : 0000000083771980
[ 0.461288] a2 : 000000008378af97 a3 : 0000000000000000 a4 : 0000000000000000
[ 0.462059] a5 : 0000000000084000 a6 : 0000000083786320 a7 : 0000000000000024
[ 0.462817] s2 : 0000000083783fd0 s3 : fffffffffffffff8 s4 : 0000000083725dcc
[ 0.463500] s5 : 0000000000000001 s6 : 0000000000000001 s7 : 0000000000000001
[ 0.464242] s8 : 0000000000000000 s9 : 0000000000000000 s10: 0000000000000000
[ 0.464935] s11: 0000000000000000 t3 : 000000000000003d t4 : 000000000000002b
[ 0.465699] t5 : 0000000000000002 t6 : 0000000000000001
[ 0.466280] status: 0000000000004080 badaddr: 0000000000084010 cause: 0000000000000005
[ 0.473174] ln[31]: unhandled signal 11 code 0x2 at 0x00000000830000e4
[ 0.473764] CPU: 0 PID: 31 Comm: ln Not tainted 5.4.0-rc5-00012-gb66bae191a9b #64
[ 0.474377] epc: 00000000830000e4 ra : 000000008301c1d8 sp : 000000008308adb0
[ 0.474957] gp : 0000000083071300 tp : 0000000000000000 t0 : 0000000000000031
[ 0.475437] t1 : 8101010101010100 t2 : 0000000000000007 s0 : 0000000000000001
[ 0.475976] s1 : 0000000000000001 a0 : 0000000000000000 a1 : 0000000083071980
[ 0.476462] a2 : 000000008308af94 a3 : 0000000000000000 a4 : 0000000000000000
[ 0.477126] a5 : 0000000000084000 a6 : 0000000083086320 a7 : 0000000000000024
[ 0.477761] s2 : 0000000083083fd0 s3 : fffffffffffffff8 s4 : 0000000083025dcc
[ 0.478315] s5 : 0000000000000001 s6 : 0000000000000001 s7 : 0000000000000001
[ 0.478845] s8 : 0000000000000000 s9 : 0000000000000000 s10: 0000000000000000
[ 0.479341] s11: 0000000000000000 t3 : 000000000000003d t4 : 000000000000002b
[ 0.479844] t5 : 0000000000000002 t6 : 0000000000000001
[ 0.480221] status: 0000000000004080 badaddr: 0000000000084010 cause: 0000000000000005
[ 0.490205] ln[32]: unhandled signal 11 code 0x2 at 0x00000000830000e4
[ 0.491256] CPU: 1 PID: 32 Comm: ln Not tainted 5.4.0-rc5-00012-gb66bae191a9b #64
[ 0.492336] epc: 00000000830000e4 ra : 000000008301c1d8 sp : 000000008308adb0
[ 0.493307] gp : 0000000083071300 tp : 0000000000000000 t0 : 0000000000000031
[ 0.494339] t1 : 8101010101010100 t2 : 0000000000000007 s0 : 0000000000000001
[ 0.495393] s1 : 0000000000000001 a0 : 0000000000000000 a1 : 0000000083071980
[ 0.496435] a2 : 000000008308af93 a3 : 0000000000000000 a4 : 0000000000000000
[ 0.497320] a5 : 0000000000084000 a6 : 0000000083086320 a7 : 0000000000000024
[ 0.498423] s2 : 0000000083083fd0 s3 : fffffffffffffff8 s4 : 0000000083025dcc
[ 0.499438] s5 : 0000000000000001 s6 : 0000000000000001 s7 : 0000000000000001
[ 0.500446] s8 : 0000000000000000 s9 : 0000000000000000 s10: 0000000000000000
[ 0.501366] s11: 0000000000000000 t3 : 000000000000003d t4 : 000000000000002b
[ 0.502388] t5 : 0000000000000002 t6 : 0000000000000001
[ 0.503105] status: 0000000000004080 badaddr: 0000000000084010 cause: 0000000000000005
[ 0.509043] ln[33]: unhandled signal 11 code 0x2 at 0x00000000831000e4
[ 0.510043] CPU: 1 PID: 33 Comm: ln Not tainted 5.4.0-rc5-00012-gb66bae191a9b #64
[ 0.511149] epc: 00000000831000e4 ra : 000000008311c1d8 sp : 000000008318adb0
[ 0.512172] gp : 0000000083171300 tp : 0000000000000000 t0 : 0000000000000031
[ 0.513281] t1 : 8101010101010100 t2 : 0000000000000007 s0 : 0000000000000001
[ 0.514394] s1 : 0000000000000001 a0 : 0000000000000000 a1 : 0000000083171980
[ 0.515462] a2 : 000000008318af93 a3 : 0000000000000000 a4 : 0000000000000000
[ 0.516528] a5 : 0000000000084000 a6 : 0000000083186320 a7 : 0000000000000024
[ 0.517673] s2 : 0000000083183fd0 s3 : fffffffffffffff8 s4 : 0000000083125dcc
[ 0.518745] s5 : 0000000000000001 s6 : 0000000000000001 s7 : 0000000000000001
[ 0.519826] s8 : 0000000000000000 s9 : 0000000000000000 s10: 0000000000000000
[ 0.520958] s11: 0000000000000000 t3 : 000000000000003d t4 : 000000000000002b
[ 0.522032] t5 : 0000000000000002 t6 : 0000000000000001
[ 0.522835] status: 0000000000004080 badaddr: 0000000000084010 cause: 0000000000000005
[ 0.531820] hostname[34]: unhandled signal 11 code 0x2 at 0x00000000831000e4
[ 0.532482] CPU: 0 PID: 34 Comm: hostname Not tainted 5.4.0-rc5-00012-gb66bae191a9b #64
[ 0.533301] epc: 00000000831000e4 ra : 000000008311c1d8 sp : 000000008318adc0
[ 0.533936] gp : 0000000083171300 tp : 0000000000000000 t0 : 0000000000000002
[ 0.534545] t1 : 000000008318ada0 t2 : 0000000000000007 s0 : 0000000000000001
[ 0.535092] s1 : 0000000000000001 a0 : 0000000000000000 a1 : 0000000083788008
[ 0.535593] a2 : 0000000000001000 a3 : 0000000000000003 a4 : 0000000000000000
[ 0.536104] a5 : 0000000000084000 a6 : 0000000000000001 a7 : 000000000000003f
[ 0.536609] s2 : 0000000083183fd0 s3 : fffffffffffffff8 s4 : 0000000083125dcc
[ 0.537208] s5 : 0000000000000001 s6 : 0000000000000001 s7 : 0000000000000001
[ 0.537786] s8 : 0000000000000000 s9 : 0000000000000000 s10: 0000000000000000
[ 0.538312] s11: 0000000000000000 t3 : 0000000083174474 t4 : 0000000000000000
[ 0.538828] t5 : 0000000000000018 t6 : 462d200000000000
[ 0.539225] status: 0000000000004080 badaddr: 0000000000084010 cause: 0000000000000005
[ 0.574716] [[36]: unhandled signal 11 code 0x2 at 0x00000000832000e4
[ 0.575424] CPU: 0 PID: 36 Comm: [ Not tainted 5.4.0-rc5-00012-gb66bae191a9b #64
[ 0.575968] epc: 00000000832000e4 ra : 000000008321c1d8 sp : 000000008328ad80
[ 0.576498] gp : 0000000083271300 tp : 0000000000000000 t0 : 0000000000000002
[ 0.577166] t1 : 000000008308d108 t2 : 0000000000000007 s0 : 0000000000000001
[ 0.577723] s1 : 0000000000000001 a0 : 0000000000000001 a1 : 000000008308dfe8
[ 0.578263] a2 : 0000000000000108 a3 : 000000008308d108 a4 : 0000000000000000
[ 0.578814] a5 : 0000000000084000 a6 : 0000000000001000 a7 : 0000000000000018
[ 0.579333] s2 : 0000000083283fd0 s3 : fffffffffffffff8 s4 : 0000000083225dcc
[ 0.579857] s5 : 0000000000000001 s6 : 0000000000000001 s7 : 0000000000000001
[ 0.580386] s8 : 0000000000000008 s9 : 000000000000002f s10: 000000000000002f
[ 0.581058] s11: 0000000000000000 t3 : 0000000083274474 t4 : 0000000000000000
[ 0.581625] t5 : 0000000000000018 t6 : 74696e0000000000
[ 0.582031] status: 0000000000004080 badaddr: 0000000000084010 cause: 0000000000000005
SEGV
SEGV
SEGV
sh: can't execute 'start-stop-daemon': No such file or directory
SEGV
FAIL
SEGV
SEGV
SEGV
SEGV
sh: can't execute 'start-stop-daemon': No such file or directory
SEGV
FAIL
SEGV
SEGV
SEGV
SEGV
SEGV
SEGV
sh: can't execute '/sbin/ifup': No such file or directory
SEGV
FAIL
SEGV
Welcome to Buildroot
buildroot login: QEMU: Terminated
On Wed, Oct 30, 2019 at 01:21:21PM -0700, Paul Walmsley wrote:
> I tried building this series from your git branch mentioned above, and
> booted it with a buildroot userspace built from your custom buildroot
> tree. Am seeing some segmentation faults from userspace (below).
>
> Am still planning to merge your patches.
>
> But I'm wondering whether you are seeing these segmentation faults also?
> Or is it something that might be specific to my test setup?
I just built a fresh image using make -j4 with that report and it works
perfectly fine with my tree.
On Thu, 31 Oct 2019, Christoph Hellwig wrote:
> On Wed, Oct 30, 2019 at 01:21:21PM -0700, Paul Walmsley wrote:
> > I tried building this series from your git branch mentioned above, and
> > booted it with a buildroot userspace built from your custom buildroot
> > tree. Am seeing some segmentation faults from userspace (below).
> >
> > Am still planning to merge your patches.
> >
> > But I'm wondering whether you are seeing these segmentation faults also?
> > Or is it something that might be specific to my test setup?
>
> I just built a fresh image using make -j4 with that report and it works
> perfectly fine with my tree.
OK, good to know.
If there are other folks out there who are using Christoph's nommu patch
set, it'd be great to get testing feedback.
- Paul
On Mon, 28 Oct 2019, Christoph Hellwig wrote:
> There is no SBI when we run in M-mode, so fail the compile for any code
> trying to use SBI calls.
>
> Signed-off-by: Christoph Hellwig <[email protected]>
> Reviewed-by: Anup Patel <[email protected]>
Thanks, queued for v5.5-rc.
- Paul
Daniel, Thomas,
On Mon, 28 Oct 2019, Christoph Hellwig wrote:
> When running in M-mode we can't use the SBI to set the timer, and
> don't have access to the time CSR as that usually is emulated by
> M-mode. Instead provide code that directly accesses the MMIO for
> the timer.
>
> Signed-off-by: Christoph Hellwig <[email protected]>
> Reviewed-by: Anup Patel <[email protected]>
Care to give a quick ack to the drivers/clocksource/timer-riscv.c changes?
thanks,
- Paul
> ---
> arch/riscv/include/asm/sbi.h | 3 ++-
> arch/riscv/include/asm/timex.h | 19 +++++++++++++++++--
> drivers/clocksource/timer-riscv.c | 21 +++++++++++++++++----
> 3 files changed, 36 insertions(+), 7 deletions(-)
>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index 0cb74eccc73f..a4774bafe033 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -95,7 +95,8 @@ static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid);
> }
> #else /* CONFIG_RISCV_SBI */
> -/* stub to for code is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */
> +/* stubs to for code is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */
> +void sbi_set_timer(uint64_t stime_value);
> void sbi_remote_fence_i(const unsigned long *hart_mask);
> #endif /* CONFIG_RISCV_SBI */
> #endif /* _ASM_RISCV_SBI_H */
> diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h
> index c7ef131b9e4c..e17837d61667 100644
> --- a/arch/riscv/include/asm/timex.h
> +++ b/arch/riscv/include/asm/timex.h
> @@ -7,12 +7,25 @@
> #define _ASM_RISCV_TIMEX_H
>
> #include <asm/csr.h>
> +#include <asm/io.h>
>
> typedef unsigned long cycles_t;
>
> +extern u64 __iomem *riscv_time_val;
> +extern u64 __iomem *riscv_time_cmp;
> +
> +#ifdef CONFIG_64BIT
> +#define mmio_get_cycles() readq_relaxed(riscv_time_val)
> +#else
> +#define mmio_get_cycles() readl_relaxed(riscv_time_val)
> +#define mmio_get_cycles_hi() readl_relaxed(((u32 *)riscv_time_val) + 1)
> +#endif
> +
> static inline cycles_t get_cycles(void)
> {
> - return csr_read(CSR_TIME);
> + if (IS_ENABLED(CONFIG_RISCV_SBI))
> + return csr_read(CSR_TIME);
> + return mmio_get_cycles();
> }
> #define get_cycles get_cycles
>
> @@ -24,7 +37,9 @@ static inline u64 get_cycles64(void)
> #else /* CONFIG_64BIT */
> static inline u32 get_cycles_hi(void)
> {
> - return csr_read(CSR_TIMEH);
> + if (IS_ENABLED(CONFIG_RISCV_SBI))
> + return csr_read(CSR_TIMEH);
> + return mmio_get_cycles_hi();
> }
>
> static inline u64 get_cycles64(void)
> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> index d083bfb535f6..f3eb0c04401a 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -3,9 +3,9 @@
> * Copyright (C) 2012 Regents of the University of California
> * Copyright (C) 2017 SiFive
> *
> - * All RISC-V systems have a timer attached to every hart. These timers can be
> - * read from the "time" and "timeh" CSRs, and can use the SBI to setup
> - * events.
> + * All RISC-V systems have a timer attached to every hart. These timers can
> + * either be read from the "time" and "timeh" CSRs, and can use the SBI to
> + * setup events, or directly accessed using MMIO registers.
> */
> #include <linux/clocksource.h>
> #include <linux/clockchips.h>
> @@ -13,14 +13,27 @@
> #include <linux/delay.h>
> #include <linux/irq.h>
> #include <linux/sched_clock.h>
> +#include <linux/io-64-nonatomic-lo-hi.h>
> #include <asm/smp.h>
> #include <asm/sbi.h>
>
> +u64 __iomem *riscv_time_cmp;
> +u64 __iomem *riscv_time_val;
> +
> +static inline void mmio_set_timer(u64 val)
> +{
> + writeq_relaxed(val,
> + riscv_time_cmp + cpuid_to_hartid_map(smp_processor_id()));
> +}
> +
> static int riscv_clock_next_event(unsigned long delta,
> struct clock_event_device *ce)
> {
> csr_set(CSR_IE, IE_TIE);
> - sbi_set_timer(get_cycles64() + delta);
> + if (IS_ENABLED(CONFIG_RISCV_SBI))
> + sbi_set_timer(get_cycles64() + delta);
> + else
> + mmio_set_timer(get_cycles64() + delta);
> return 0;
> }
>
> --
> 2.20.1
>
>
- Paul
Hi Christoph,
On Mon, 11 Nov 2019, Christoph Hellwig wrote:
> what is the status of this series?
At the moment I'm waiting for acks from other maintainers. Could you
please chase those down? It's the responsibility of the developer to do
that.
- Paul
On Mon, 28 Oct 2019, Christoph Hellwig wrote:
> When running in M-mode we can't use the SBI to set the timer, and
> don't have access to the time CSR as that usually is emulated by
> M-mode. Instead provide code that directly accesses the MMIO for
> the timer.
>
> Signed-off-by: Christoph Hellwig <[email protected]>
> Reviewed-by: Anup Patel <[email protected]>
> ---
> arch/riscv/include/asm/sbi.h | 3 ++-
> arch/riscv/include/asm/timex.h | 19 +++++++++++++++++--
> drivers/clocksource/timer-riscv.c | 21 +++++++++++++++++----
Acked-by: Thomas Gleixner <[email protected]>
On Mon, Nov 11, 2019 at 05:02:51PM +0000, Paul Walmsley wrote:
> Hi Christoph,
>
> On Mon, 11 Nov 2019, Christoph Hellwig wrote:
>
> > what is the status of this series?
>
> At the moment I'm waiting for acks from other maintainers.
I think you should have all ACK now, the only ones missing were the
onces for the trivial search and replace in the time driver which
really is maintained by us anyway, but Thomas was so nice to take
a look.
On Mon, 28 Oct 2019, Christoph Hellwig wrote:
> When running in M-mode we can't use the SBI to set the timer, and
> don't have access to the time CSR as that usually is emulated by
> M-mode. Instead provide code that directly accesses the MMIO for
> the timer.
>
> Signed-off-by: Christoph Hellwig <[email protected]>
> Reviewed-by: Anup Patel <[email protected]>
Thanks, queued the following for v5.5-rc1.
- Paul
From: Christoph Hellwig <[email protected]>
Date: Mon, 28 Oct 2019 13:10:37 +0100
Subject: [PATCH] riscv: add support for MMIO access to the timer registers
When running in M-mode we can't use the SBI to set the timer, and
don't have access to the time CSR as that usually is emulated by
M-mode. Instead provide code that directly accesses the MMIO for
the timer.
Signed-off-by: Christoph Hellwig <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Acked-by: Thomas Gleixner <[email protected]>
[[email protected]: updated to apply; fixed checkpatch
issue; timex.h now includes asm/mmio.h to resolve header file
problems]
Signed-off-by: Paul Walmsley <[email protected]>
---
arch/riscv/include/asm/sbi.h | 3 ++-
arch/riscv/include/asm/timex.h | 19 +++++++++++++++++--
drivers/clocksource/timer-riscv.c | 23 +++++++++++++++++++----
3 files changed, 38 insertions(+), 7 deletions(-)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 204af718df61..8e14d4819d0f 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -95,7 +95,8 @@ static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid);
}
#else /* CONFIG_RISCV_SBI */
-/* stub for code that is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */
+/* stubs for code that is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */
+void sbi_set_timer(uint64_t stime_value);
void sbi_remote_fence_i(const unsigned long *hart_mask);
#endif /* CONFIG_RISCV_SBI */
#endif /* _ASM_RISCV_SBI_H */
diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h
index c7ef131b9e4c..bad2a7c2cda5 100644
--- a/arch/riscv/include/asm/timex.h
+++ b/arch/riscv/include/asm/timex.h
@@ -7,12 +7,25 @@
#define _ASM_RISCV_TIMEX_H
#include <asm/csr.h>
+#include <asm/mmio.h>
typedef unsigned long cycles_t;
+extern u64 __iomem *riscv_time_val;
+extern u64 __iomem *riscv_time_cmp;
+
+#ifdef CONFIG_64BIT
+#define mmio_get_cycles() readq_relaxed(riscv_time_val)
+#else
+#define mmio_get_cycles() readl_relaxed(riscv_time_val)
+#define mmio_get_cycles_hi() readl_relaxed(((u32 *)riscv_time_val) + 1)
+#endif
+
static inline cycles_t get_cycles(void)
{
- return csr_read(CSR_TIME);
+ if (IS_ENABLED(CONFIG_RISCV_SBI))
+ return csr_read(CSR_TIME);
+ return mmio_get_cycles();
}
#define get_cycles get_cycles
@@ -24,7 +37,9 @@ static inline u64 get_cycles64(void)
#else /* CONFIG_64BIT */
static inline u32 get_cycles_hi(void)
{
- return csr_read(CSR_TIMEH);
+ if (IS_ENABLED(CONFIG_RISCV_SBI))
+ return csr_read(CSR_TIMEH);
+ return mmio_get_cycles_hi();
}
static inline u64 get_cycles64(void)
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index d083bfb535f6..4e54856ce2a5 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -3,9 +3,9 @@
* Copyright (C) 2012 Regents of the University of California
* Copyright (C) 2017 SiFive
*
- * All RISC-V systems have a timer attached to every hart. These timers can be
- * read from the "time" and "timeh" CSRs, and can use the SBI to setup
- * events.
+ * All RISC-V systems have a timer attached to every hart. These timers can
+ * either be read from the "time" and "timeh" CSRs, and can use the SBI to
+ * setup events, or directly accessed using MMIO registers.
*/
#include <linux/clocksource.h>
#include <linux/clockchips.h>
@@ -13,14 +13,29 @@
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/sched_clock.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
#include <asm/smp.h>
#include <asm/sbi.h>
+u64 __iomem *riscv_time_cmp;
+u64 __iomem *riscv_time_val;
+
+static inline void mmio_set_timer(u64 val)
+{
+ void __iomem *r;
+
+ r = riscv_time_cmp + cpuid_to_hartid_map(smp_processor_id());
+ writeq_relaxed(val, r);
+}
+
static int riscv_clock_next_event(unsigned long delta,
struct clock_event_device *ce)
{
csr_set(CSR_IE, IE_TIE);
- sbi_set_timer(get_cycles64() + delta);
+ if (IS_ENABLED(CONFIG_RISCV_SBI))
+ sbi_set_timer(get_cycles64() + delta);
+ else
+ mmio_set_timer(get_cycles64() + delta);
return 0;
}
--
2.24.0.rc0
On Mon, 28 Oct 2019, Christoph Hellwig wrote:
> This allows just loading the kernel at a pre-set address without
> qemu going bonkers trying to map the ELF file.
>
> Contains a controbution from Aurabindo Jayamohanan to reuse the
> PAGE_OFFSET definition.
>
> Signed-off-by: Christoph Hellwig <[email protected]>
> Reviewed-by: Anup Patel <[email protected]>
Thanks, queued for v5.5-rc1.
- Paul
On Thu, 31 Oct 2019, Christoph Hellwig wrote:
> On Wed, Oct 30, 2019 at 01:21:21PM -0700, Paul Walmsley wrote:
> > I tried building this series from your git branch mentioned above, and
> > booted it with a buildroot userspace built from your custom buildroot
> > tree. Am seeing some segmentation faults from userspace (below).
> >
> > Am still planning to merge your patches.
> >
> > But I'm wondering whether you are seeing these segmentation faults also?
> > Or is it something that might be specific to my test setup?
>
> I just built a fresh image using make -j4 with that report and it works
> perfectly fine with my tree.
Another colleague just gave this a quick test, following your instructions
as I did. He encountered the same segmentation faulting issue. Might be
worth taking a look at this once v5.5-rc1 is released. Could be a
userspace issue, though.
- Paul
Paul Walmsley <[email protected]> 於 2019年11月23日 週六 上午10:24寫道：
>
> On Thu, 31 Oct 2019, Christoph Hellwig wrote:
>
> > On Wed, Oct 30, 2019 at 01:21:21PM -0700, Paul Walmsley wrote:
> > > I tried building this series from your git branch mentioned above, and
> > > booted it with a buildroot userspace built from your custom buildroot
> > > tree. Am seeing some segmentation faults from userspace (below).
> > >
> > > Am still planning to merge your patches.
> > >
> > > But I'm wondering whether you are seeing these segmentation faults also?
> > > Or is it something that might be specific to my test setup?
> >
> > I just built a fresh image using make -j4 with that report and it works
> > perfectly fine with my tree.
>
> Another colleague just gave this a quick test, following your instructions
> as I did. He encountered the same segmentation faulting issue. Might be
> worth taking a look at this once v5.5-rc1 is released. Could be a
> userspace issue, though.
Hi Christoph,
I think it should be replaced with this macro for cores without S-mode.
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 9bca97ffb67a..5c8b24bf4e4e 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -248,7 +248,7 @@ ENTRY(reset_regs)
li t4, 0
li t5, 0
li t6, 0
- csrw sscratch, 0
+ csrw CSR_SCRATCH, 0
#ifdef CONFIG_FPU
csrr t0, CSR_MISA
Paul Walmsley <[email protected]> 於 2019年11月23日 週六 上午10:24寫道：
>
> On Thu, 31 Oct 2019, Christoph Hellwig wrote:
>
> > On Wed, Oct 30, 2019 at 01:21:21PM -0700, Paul Walmsley wrote:
> > > I tried building this series from your git branch mentioned above, and
> > > booted it with a buildroot userspace built from your custom buildroot
> > > tree. Am seeing some segmentation faults from userspace (below).
> > >
> > > Am still planning to merge your patches.
> > >
> > > But I'm wondering whether you are seeing these segmentation faults also?
> > > Or is it something that might be specific to my test setup?
> >
> > I just built a fresh image using make -j4 with that report and it works
> > perfectly fine with my tree.
>
> Another colleague just gave this a quick test, following your instructions
> as I did. He encountered the same segmentation faulting issue. Might be
> worth taking a look at this once v5.5-rc1 is released. Could be a
> userspace issue, though.
>
Hi all,
I have the same symptom too.
[ 0.389983] Run /init as init process
[ 0.457294] mount[24]: unhandled signal 11 code 0x2 at 0x00000000834000e8
[ 0.458057] CPU: 0 PID: 24 Comm: mount Not tainted
5.4.0-rc5-00021-g1a87b1010118 #44
[ 0.458477] epc: 00000000834000e8 ra : 000000008341c140 sp :
000000008348add0
[ 0.458803] gp : 0000000083471300 tp : 0000000000000000 t0 :
0000000000000032
[ 0.459319] t1 : 8101010101010100 t2 : 0000000000000007 s0 :
0000000000000001
[ 0.459678] s1 : 0000000000000001 a0 : 0000000000000000 a1 :
000000008348afb8
[ 0.460027] a2 : 000000008348afa6 a3 : 0000000000008000 a4 :
0000000000000000
[ 0.460370] a5 : 0000000000084000 a6 : 70f8fefcf8fef0fc a7 :
0000000000000028
[ 0.460829] s2 : 0000000083483fd0 s3 : fffffffffffffff8 s4 :
0000000083425dcc
[ 0.461200] s5 : 0000000000000001 s6 : 0000000000000001 s7 :
0000000000000001
[ 0.461592] s8 : 0000000000000000 s9 : 00000000838ccbd0 s10:
0000000000000000
[ 0.461912] s11: 0000000000000000 t3 : 000000000000003d t4 :
000000000000002b
[ 0.462283] t5 : 0000000000000002 t6 : 0000000000000001
[ 0.462562] status: 0000000000004080 badaddr: 0000000000084010
cause: 0000000000000005
SEGV
This failure is because of it tries access the absolute address. This
address is generated by gcc. It tries to access __bss_start in a non-PIC
way. The code sequence will be looked like this.
00000000000000a4 <__do_global_dtors_aux>:
a4: 000847b7 lui a5,0x84
a8: 0107c703 lbu a4,16(a5) # 84010
<__bss_start>
However this is a user program and it will be loaded to any
address of RAM by kernel loader
so that it could not use the absolute address.
In this case, we have to enable PIC when compiling these codes and it is in
gcc so we have to set the correct configuration options for gcc in
buildroot.
-BR2_EXTRA_GCC_CONFIG_OPTIONS=""
+BR2_EXTRA_GCC_CONFIG_OPTIONS="CFLAGS_FOR_TARGET='-O2 -fPIC'
CXXFLAGS_FOR_TARGET='-O2 -fPIC'"
After applying this fix, the code will be looked like this.
00000000000000a0 <__do_global_dtors_aux>:
a0: 00085797 auipc a5,0x85
a4: bf07c783 lbu a5,-1040(a5) #
84c90 <__bss_start>
It could boot to shell without any segmentation fault.
Hi Christoph,
Would you like to upstream the buildroot porting for nommu support?
Then I can upstream this fix. :)