2019-11-07 09:05:26

by Rajan Vaja

Subject: [PATCH] clk: zynqmp: Correct bit index for divider flag

Update divider flag bit index to match with firmware.

Signed-off-by: Rajan Vaja <[email protected]>
Signed-off-by: Jolly Shah <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
---
drivers/clk/zynqmp/divider.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index d8f5b70d..9e60834 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -2,7 +2,7 @@
/*
* Zynq UltraScale+ MPSoC Divider support
*
- * Copyright (C) 2016-2018 Xilinx
+ * Copyright (C) 2016-2019 Xilinx
*
* Adjustable divider clock implementation
*/
@@ -25,7 +25,7 @@
#define to_zynqmp_clk_divider(_hw) \
container_of(_hw, struct zynqmp_clk_divider, hw)

-#define CLK_FRAC BIT(13) /* has a fractional parent */
+#define CLK_FRAC BIT(8) /* has a fractional parent */

/**
* struct zynqmp_clk_divider - adjustable divider clock
--
2.7.4

2019-11-07 17:03:22

by Michael Tretter

Subject: Re: [PATCH] clk: zynqmp: Correct bit index for divider flag

On Thu, 07 Nov 2019 01:01:30 -0800, Rajan Vaja wrote:
> Update divider flag bit index to match with firmware.
>
> Signed-off-by: Rajan Vaja <[email protected]>
> Signed-off-by: Jolly Shah <[email protected]>
> Signed-off-by: Michal Simek <[email protected]>
> ---
> drivers/clk/zynqmp/divider.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
> index d8f5b70d..9e60834 100644
> --- a/drivers/clk/zynqmp/divider.c
> +++ b/drivers/clk/zynqmp/divider.c
> @@ -2,7 +2,7 @@
> /*
> * Zynq UltraScale+ MPSoC Divider support
> *
> - * Copyright (C) 2016-2018 Xilinx
> + * Copyright (C) 2016-2019 Xilinx
> *
> * Adjustable divider clock implementation
> */
> @@ -25,7 +25,7 @@
> #define to_zynqmp_clk_divider(_hw) \
> container_of(_hw, struct zynqmp_clk_divider, hw)
>
> -#define CLK_FRAC BIT(13) /* has a fractional parent */
> +#define CLK_FRAC BIT(8) /* has a fractional parent */

NACK.

This breaks the compatibility with the older/upstream versions of the
TF-A. You have to at least make this dependent on the used version of
the TF-A.

>
> /**
> * struct zynqmp_clk_divider - adjustable divider clock