A device tree binding documentation as well as a driver implementing
support for the external interrupt lines on the ls1021a has been
merged into irqchip-next, so will very likely appear in v5.5. See
87cd38dfd9e6 dt/bindings: Add bindings for Layerscape external irqs
0dcd9f872769 irqchip: Add support for Layerscape external interrupt lines
present in next-20191114.
These patches simply add the extirq node to the ls1021a.dtsi and make
use of it on the LS1021A-TSN board. I hope these can be picked up so
they also land in v5.5, so we don't have to wait a full extra release
cycle.
v2: fix interrupt type in 2/2 (s/IRQ_TYPE_EDGE_FALLING/IRQ_TYPE_LEVEL_LOW/).
Rasmus Villemoes (1):
ARM: dts: ls1021a: add node describing external interrupt lines
Vladimir Oltean (1):
ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYs
arch/arm/boot/dts/ls1021a-tsn.dts | 4 ++++
arch/arm/boot/dts/ls1021a.dtsi | 19 +++++++++++++++++++
2 files changed, 23 insertions(+)
--
2.23.0
From: Vladimir Oltean <[email protected]>
On the LS1021A-TSN board, the 2 Atheros AR8031 PHYs for eth0 and eth1
have interrupt lines connected to the shared IRQ2_B LS1021A pin.
Switching to interrupts offloads the PHY library from the task of
polling the MDIO status and AN registers (1, 4, 5) every second.
Unfortunately, the BCM5464R quad PHY connected to the switch does not
appear to have an interrupt line routed to the SoC.
Signed-off-by: Vladimir Oltean <[email protected]>
Signed-off-by: Rasmus Villemoes <[email protected]>
---
arch/arm/boot/dts/ls1021a-tsn.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/ls1021a-tsn.dts b/arch/arm/boot/dts/ls1021a-tsn.dts
index 5b7689094b70..9d8f0c2a8aba 100644
--- a/arch/arm/boot/dts/ls1021a-tsn.dts
+++ b/arch/arm/boot/dts/ls1021a-tsn.dts
@@ -203,11 +203,15 @@
/* AR8031 */
sgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
+ /* SGMII1_PHY_INT_B: connected to IRQ2, active low */
+ interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
};
/* AR8031 */
sgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
+ /* SGMII2_PHY_INT_B: connected to IRQ2, active low */
+ interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
};
/* BCM5464 quad PHY */
--
2.23.0
On Thu, Nov 14, 2019 at 12:02:53PM +0100, Rasmus Villemoes wrote:
> From: Vladimir Oltean <[email protected]>
>
> On the LS1021A-TSN board, the 2 Atheros AR8031 PHYs for eth0 and eth1
> have interrupt lines connected to the shared IRQ2_B LS1021A pin.
>
> Switching to interrupts offloads the PHY library from the task of
> polling the MDIO status and AN registers (1, 4, 5) every second.
>
> Unfortunately, the BCM5464R quad PHY connected to the switch does not
> appear to have an interrupt line routed to the SoC.
>
> Signed-off-by: Vladimir Oltean <[email protected]>
> Signed-off-by: Rasmus Villemoes <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
Andrew
From: Rasmus Villemoes <[email protected]>
Date: Thu, 14 Nov 2019 12:02:51 +0100
> A device tree binding documentation as well as a driver implementing
> support for the external interrupt lines on the ls1021a has been
> merged into irqchip-next, so will very likely appear in v5.5. See
>
> 87cd38dfd9e6 dt/bindings: Add bindings for Layerscape external irqs
> 0dcd9f872769 irqchip: Add support for Layerscape external interrupt lines
>
> present in next-20191114.
>
> These patches simply add the extirq node to the ls1021a.dtsi and make
> use of it on the LS1021A-TSN board. I hope these can be picked up so
> they also land in v5.5, so we don't have to wait a full extra release
> cycle.
>
> v2: fix interrupt type in 2/2 (s/IRQ_TYPE_EDGE_FALLING/IRQ_TYPE_LEVEL_LOW/).
I am assuming this will go via an ARM tree.
On Thu, 14 Nov 2019 at 23:40, David Miller <[email protected]> wrote:
>
> From: Rasmus Villemoes <[email protected]>
> Date: Thu, 14 Nov 2019 12:02:51 +0100
>
> > A device tree binding documentation as well as a driver implementing
> > support for the external interrupt lines on the ls1021a has been
> > merged into irqchip-next, so will very likely appear in v5.5. See
> >
> > 87cd38dfd9e6 dt/bindings: Add bindings for Layerscape external irqs
> > 0dcd9f872769 irqchip: Add support for Layerscape external interrupt lines
> >
> > present in next-20191114.
> >
> > These patches simply add the extirq node to the ls1021a.dtsi and make
> > use of it on the LS1021A-TSN board. I hope these can be picked up so
> > they also land in v5.5, so we don't have to wait a full extra release
> > cycle.
> >
> > v2: fix interrupt type in 2/2 (s/IRQ_TYPE_EDGE_FALLING/IRQ_TYPE_LEVEL_LOW/).
>
> I am assuming this will go via an ARM tree.
Yes, of course, they are for Shawn. Netdev and Andrew was copied for
patch 2/2 (an SGMII PHY interrupt).
Regards,
-Vladimir
On Thu, Nov 14, 2019 at 12:02:51PM +0100, Rasmus Villemoes wrote:
> A device tree binding documentation as well as a driver implementing
> support for the external interrupt lines on the ls1021a has been
> merged into irqchip-next, so will very likely appear in v5.5. See
>
> 87cd38dfd9e6 dt/bindings: Add bindings for Layerscape external irqs
> 0dcd9f872769 irqchip: Add support for Layerscape external interrupt lines
>
> present in next-20191114.
>
> These patches simply add the extirq node to the ls1021a.dtsi and make
> use of it on the LS1021A-TSN board. I hope these can be picked up so
> they also land in v5.5, so we don't have to wait a full extra release
> cycle.
Sorry. I usually send queued patches around -rc6 timeline to my
arm-soc maintainers. Patches coming later than that will be scheduled
for the next release unless critical fixes.
>
> v2: fix interrupt type in 2/2 (s/IRQ_TYPE_EDGE_FALLING/IRQ_TYPE_LEVEL_LOW/).
>
> Rasmus Villemoes (1):
> ARM: dts: ls1021a: add node describing external interrupt lines
>
> Vladimir Oltean (1):
> ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYs
Applied both, thanks.