There are some typos in boot image header and riscv boot documentation.
Fix the typos.
Signed-off-by: Atish Patra <[email protected]>
---
Documentation/riscv/boot-image-header.rst | 4 ++--
arch/riscv/include/asm/image.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/Documentation/riscv/boot-image-header.rst b/Documentation/riscv/boot-image-header.rst
index 7b4d1d747585..8efb0596a33f 100644
--- a/Documentation/riscv/boot-image-header.rst
+++ b/Documentation/riscv/boot-image-header.rst
@@ -22,7 +22,7 @@ The following 64-byte header is present in decompressed Linux kernel image::
u64 res2 = 0; /* Reserved */
u64 magic = 0x5643534952; /* Magic number, little endian, "RISCV" */
u32 magic2 = 0x56534905; /* Magic number 2, little endian, "RSC\x05" */
- u32 res4; /* Reserved for PE COFF offset */
+ u32 res3; /* Reserved for PE COFF offset */
This header format is compliant with PE/COFF header and largely inspired from
ARM64 header. Thus, both ARM64 & RISC-V header can be combined into one common
@@ -34,7 +34,7 @@ Notes
- This header can also be reused to support EFI stub for RISC-V in future. EFI
specification needs PE/COFF image header in the beginning of the kernel image
in order to load it as an EFI application. In order to support EFI stub,
- code0 should be replaced with "MZ" magic string and res5(at offset 0x3c) should
+ code0 should be replaced with "MZ" magic string and res3(at offset 0x3c) should
point to the rest of the PE/COFF header.
- version field indicate header version number
diff --git a/arch/riscv/include/asm/image.h b/arch/riscv/include/asm/image.h
index 344db5244547..4f8061a5ac4a 100644
--- a/arch/riscv/include/asm/image.h
+++ b/arch/riscv/include/asm/image.h
@@ -42,7 +42,7 @@
* @res2: reserved
* @magic: Magic number (RISC-V specific; deprecated)
* @magic2: Magic number 2 (to match the ARM64 'magic' field pos)
- * @res4: reserved (will be used for PE COFF offset)
+ * @res3: reserved (will be used for PE COFF offset)
*
* The intention is for this header format to be shared between multiple
* architectures to avoid a proliferation of image header formats.
@@ -59,7 +59,7 @@ struct riscv_image_header {
u64 res2;
u64 magic;
u32 magic2;
- u32 res4;
+ u32 res3;
};
#endif /* __ASSEMBLY__ */
#endif /* __ASM_IMAGE_H */
--
2.21.0
On Tue, 2019-10-08 at 18:06 -0700, Atish Patra wrote:
> There are some typos in boot image header and riscv boot
> documentation.
>
> Fix the typos.
>
> Signed-off-by: Atish Patra <[email protected]>
> ---
> Documentation/riscv/boot-image-header.rst | 4 ++--
> arch/riscv/include/asm/image.h | 4 ++--
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/riscv/boot-image-header.rst
> b/Documentation/riscv/boot-image-header.rst
> index 7b4d1d747585..8efb0596a33f 100644
> --- a/Documentation/riscv/boot-image-header.rst
> +++ b/Documentation/riscv/boot-image-header.rst
> @@ -22,7 +22,7 @@ The following 64-byte header is present in
> decompressed Linux kernel image::
> u64 res2 = 0; /* Reserved */
> u64 magic = 0x5643534952; /* Magic number, little endian,
> "RISCV" */
> u32 magic2 = 0x56534905; /* Magic number 2, little endian,
> "RSC\x05" */
> - u32 res4; /* Reserved for PE COFF offset */
> + u32 res3; /* Reserved for PE COFF offset */
>
> This header format is compliant with PE/COFF header and largely
> inspired from
> ARM64 header. Thus, both ARM64 & RISC-V header can be combined into
> one common
> @@ -34,7 +34,7 @@ Notes
> - This header can also be reused to support EFI stub for RISC-V in
> future. EFI
> specification needs PE/COFF image header in the beginning of the
> kernel image
> in order to load it as an EFI application. In order to support EFI
> stub,
> - code0 should be replaced with "MZ" magic string and res5(at offset
> 0x3c) should
> + code0 should be replaced with "MZ" magic string and res3(at offset
> 0x3c) should
> point to the rest of the PE/COFF header.
>
> - version field indicate header version number
> diff --git a/arch/riscv/include/asm/image.h
> b/arch/riscv/include/asm/image.h
> index 344db5244547..4f8061a5ac4a 100644
> --- a/arch/riscv/include/asm/image.h
> +++ b/arch/riscv/include/asm/image.h
> @@ -42,7 +42,7 @@
> * @res2: reserved
> * @magic: Magic number (RISC-V specific; deprecated)
> * @magic2: Magic number 2 (to match the ARM64 'magic'
> field pos)
> - * @res4: reserved (will be used for PE COFF offset)
> + * @res3: reserved (will be used for PE COFF offset)
> *
> * The intention is for this header format to be shared betweenres4
> multiple
> * architectures to avoid a proliferation of image header formats.
> @@ -59,7 +59,7 @@ struct riscv_image_header {
> u64 res2;
> u64 magic;
> u32 magic2;
> - u32 res4;
> + u32 res3;
> };
> #endif /* __ASSEMBLY__ */
> #endif /* __ASM_IMAGE_H */
ping ?
--
Regards,
Atish
On Tue, 26 Nov 2019 14:02:20 PST (-0800), Atish Patra wrote:
> On Tue, 2019-10-08 at 18:06 -0700, Atish Patra wrote:
>> There are some typos in boot image header and riscv boot
>> documentation.
>>
>> Fix the typos.
>>
>> Signed-off-by: Atish Patra <[email protected]>
>> ---
>> Documentation/riscv/boot-image-header.rst | 4 ++--
>> arch/riscv/include/asm/image.h | 4 ++--
>> 2 files changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/riscv/boot-image-header.rst
>> b/Documentation/riscv/boot-image-header.rst
>> index 7b4d1d747585..8efb0596a33f 100644
>> --- a/Documentation/riscv/boot-image-header.rst
>> +++ b/Documentation/riscv/boot-image-header.rst
>> @@ -22,7 +22,7 @@ The following 64-byte header is present in
>> decompressed Linux kernel image::
>> u64 res2 = 0; /* Reserved */
>> u64 magic = 0x5643534952; /* Magic number, little endian,
>> "RISCV" */
>> u32 magic2 = 0x56534905; /* Magic number 2, little endian,
>> "RSC\x05" */
>> - u32 res4; /* Reserved for PE COFF offset */
>> + u32 res3; /* Reserved for PE COFF offset */
>>
>> This header format is compliant with PE/COFF header and largely
>> inspired from
>> ARM64 header. Thus, both ARM64 & RISC-V header can be combined into
>> one common
>> @@ -34,7 +34,7 @@ Notes
>> - This header can also be reused to support EFI stub for RISC-V in
>> future. EFI
>> specification needs PE/COFF image header in the beginning of the
>> kernel image
>> in order to load it as an EFI application. In order to support EFI
>> stub,
>> - code0 should be replaced with "MZ" magic string and res5(at offset
>> 0x3c) should
>> + code0 should be replaced with "MZ" magic string and res3(at offset
>> 0x3c) should
>> point to the rest of the PE/COFF header.
>>
>> - version field indicate header version number
>> diff --git a/arch/riscv/include/asm/image.h
>> b/arch/riscv/include/asm/image.h
>> index 344db5244547..4f8061a5ac4a 100644
>> --- a/arch/riscv/include/asm/image.h
>> +++ b/arch/riscv/include/asm/image.h
>> @@ -42,7 +42,7 @@
>> * @res2: reserved
>> * @magic: Magic number (RISC-V specific; deprecated)
>> * @magic2: Magic number 2 (to match the ARM64 'magic'
>> field pos)
>> - * @res4: reserved (will be used for PE COFF offset)
>> + * @res3: reserved (will be used for PE COFF offset)
>> *
>> * The intention is for this header format to be shared betweenres4
>> multiple
>> * architectures to avoid a proliferation of image header formats.
>> @@ -59,7 +59,7 @@ struct riscv_image_header {
>> u64 res2;
>> u64 magic;
>> u32 magic2;
>> - u32 res4;
>> + u32 res3;
>> };
>> #endif /* __ASSEMBLY__ */
>> #endif /* __ASM_IMAGE_H */
>
> ping ?
Reviewed-by: Palmer Dabbelt <[email protected]>
I'm assuming this is not going in through the RISC-V tree as it mostly touches
Documentation/.
On Thu, 05 Dec 2019 15:03:10 -0800 (PST)
Palmer Dabbelt <[email protected]> wrote:
> Reviewed-by: Palmer Dabbelt <[email protected]>
>
> I'm assuming this is not going in through the RISC-V tree as it mostly touches
> Documentation/.
I was assuming it was going through the risc-v tree since it touches arch
code :) I can go ahead and apply it.
Thanks,
jon
On Tue, 10 Dec 2019 06:29:47 PST (-0800), [email protected] wrote:
> On Thu, 05 Dec 2019 15:03:10 -0800 (PST)
> Palmer Dabbelt <[email protected]> wrote:
>
>> Reviewed-by: Palmer Dabbelt <[email protected]>
>>
>> I'm assuming this is not going in through the RISC-V tree as it mostly touches
>> Documentation/.
>
> I was assuming it was going through the risc-v tree since it touches arch
> code :) I can go ahead and apply it.
I don't see this in 5.5-rc5.
>
> Thanks,
>
> jon
On Thu, 09 Jan 2020 15:42:27 -0800 (PST)
Palmer Dabbelt <[email protected]> wrote:
> > I was assuming it was going through the risc-v tree since it touches arch
> > code :) I can go ahead and apply it.
>
> I don't see this in 5.5-rc5.
It's in docs-next; I've not pushed it through straight to 5.5. I can do
that, I suppose, if it seems urgent?
Thanks,
jon
On Fri, 10 Jan 2020 09:17:07 PST (-0800), [email protected] wrote:
> On Thu, 09 Jan 2020 15:42:27 -0800 (PST)
> Palmer Dabbelt <[email protected]> wrote:
>
>> > I was assuming it was going through the risc-v tree since it touches arch
>> > code :) I can go ahead and apply it.
>>
>> I don't see this in 5.5-rc5.
>
> It's in docs-next; I've not pushed it through straight to 5.5. I can do
> that, I suppose, if it seems urgent?
I just wanted to make sure it didn't get lost. The resolution of the thread
was a bit ambiguous and sometimes that results me losing patches, so I just
want to make sure everything is clear before I drop threads from my inbox
(which is essentially my TODO list). I was just digging myself out of a big
email hole so I figured anything still sitting around would have landed in
Linus' tree by not, but maybe I wasn't as far behind as I thought I was :)
Thanks!
>
> Thanks,
>
> jon