This patch series tries to enable the sata interface on a imx8qm based board.
I'm not sure howto do the sata clocking right. Maybe some can comment on that.
The patches are based on-top of these clock patches.
https://patchwork.kernel.org/patch/11248235/
Oliver Graute (5):
arm64: dts: imx8qm: Add HSIO Subsystem node
arm64: dts: imx8qm: added System MMU
arm64: dts: imx8qm: added sata node
arm64: dts: imx8qm: added pinctrl for pciea
arm64: dts: imx8qm-rom7720: added sata node
.../boot/dts/freescale/imx8qm-rom7720-a1.dts | 14 ++++++
arch/arm64/boot/dts/freescale/imx8qm.dtsi | 45 +++++++++++++++++++
2 files changed, 59 insertions(+)
--
2.17.1
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index 097eca99c6ff..7efc0add74ea 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -125,6 +125,11 @@
interrupt-parent = <&gic>;
};
+ hsio: hsio@5f080000 {
+ compatible = "fsl,imx8qm-hsio", "syscon";
+ reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */
+ };
+
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
--
2.17.1
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index 7efc0add74ea..fa827ed04e09 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -140,6 +140,23 @@
method = "smc";
};
+ smmu: iommu@51400000 {
+ compatible = "arm,mmu-500";
+ interrupt-parent = <&gic>;
+ reg = <0 0x51400000 0 0x40000>;
+ #global-interrupts = <1>;
+ #iommu-cells = <2>;
+ interrupts = <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
--
2.17.1
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts b/arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts
index 466f8c5c3705..8edfc8302357 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts
@@ -106,6 +106,12 @@
};
};
+&sata {
+ pinctrl-0 = <&pinctrl_pciea>;
+ clkreq-gpio = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
--
2.17.1
Signed-off-by: Oliver Graute <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8qm.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index fa827ed04e09..5d96be5fec1b 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -140,6 +140,29 @@
method = "smc";
};
+ sata: sata@5f020000 {
+ compatible = "fsl,imx8qm-ahci";
+ reg = <0x0 0x5f020000 0x0 0x10000>, /* Controller reg */
+ <0x0 0x5f1a0000 0x0 0x10000>; /* PHY reg */
+ reg-names = "ctl", "phy";
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+/*
+ clocks = <&clk IMX8QM_HSIO_SATA_CLK>,
+ <&clk IMX8QM_HSIO_PHY_X1_PCLK>,
+ <&clk IMX8QM_HSIO_SATA_EPCS_TX_CLK>,
+ <&clk IMX8QM_HSIO_SATA_EPCS_RX_CLK>,
+ <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>,
+ <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>,
+ <&clk IMX8QM_HSIO_PHY_X1_APB_CLK>;
+ clock-names = "sata", "sata_ref", "epcs_tx", "epcs_rx",
+ "phy_pclk0", "phy_pclk1", "phy_apbclk";
+*/
+ hsio = <&hsio>;
+ //power-domains = <&pd_sata0>;
+ iommus = <&smmu 0x13 0x7f80>;
+ status = "disabled";
+ };
+
smmu: iommu@51400000 {
compatible = "arm,mmu-500";
interrupt-parent = <&gic>;
--
2.17.1
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts b/arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts
index 331eec2dff01..466f8c5c3705 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts
@@ -174,6 +174,14 @@
>;
};
+ pinctrl_pciea: pcieagrp{
+ fsl,pins = <
+ IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021
+ IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021
+ IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021
+ >;
+ };
+
pinctrl_rtc_epson_rx8900: rtc_epson_rx8900_grp {
fsl,pins = <
IMX8QM_SIM0_POWER_EN_DMA_I2C3_SDA 0xc600004c
--
2.17.1