From: Tom Lendacky <[email protected]>
commit 52918ed5fcf05d97d257f4131e19479da18f5d16 upstream.
The KVM MMIO support uses bit 51 as the reserved bit to cause nested page
faults when a guest performs MMIO. The AMD memory encryption support uses
a CPUID function to define the encryption bit position. Given this, it is
possible that these bits can conflict.
Use svm_hardware_setup() to override the MMIO mask if memory encryption
support is enabled. Various checks are performed to ensure that the mask
is properly defined and rsvd_bits() is used to generate the new mask (as
was done prior to the change that necessitated this patch).
Fixes: 28a1f3ac1d0c ("kvm: x86: Set highest physical address bits in non-present/reserved SPTEs")
Suggested-by: Sean Christopherson <[email protected]>
Reviewed-by: Sean Christopherson <[email protected]>
Signed-off-by: Tom Lendacky <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
---
arch/x86/kvm/svm.c | 43 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -1088,6 +1088,47 @@ static int avic_ga_log_notifier(u32 ga_t
return 0;
}
+/*
+ * The default MMIO mask is a single bit (excluding the present bit),
+ * which could conflict with the memory encryption bit. Check for
+ * memory encryption support and override the default MMIO mask if
+ * memory encryption is enabled.
+ */
+static __init void svm_adjust_mmio_mask(void)
+{
+ unsigned int enc_bit, mask_bit;
+ u64 msr, mask;
+
+ /* If there is no memory encryption support, use existing mask */
+ if (cpuid_eax(0x80000000) < 0x8000001f)
+ return;
+
+ /* If memory encryption is not enabled, use existing mask */
+ rdmsrl(MSR_K8_SYSCFG, msr);
+ if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
+ return;
+
+ enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
+ mask_bit = boot_cpu_data.x86_phys_bits;
+
+ /* Increment the mask bit if it is the same as the encryption bit */
+ if (enc_bit == mask_bit)
+ mask_bit++;
+
+ /*
+ * If the mask bit location is below 52, then some bits above the
+ * physical addressing limit will always be reserved, so use the
+ * rsvd_bits() function to generate the mask. This mask, along with
+ * the present bit, will be used to generate a page fault with
+ * PFER.RSV = 1.
+ *
+ * If the mask bit location is 52 (or above), then clear the mask.
+ */
+ mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
+
+ kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
+}
+
static __init int svm_hardware_setup(void)
{
int cpu;
@@ -1123,6 +1164,8 @@ static __init int svm_hardware_setup(voi
kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
}
+ svm_adjust_mmio_mask();
+
for_each_possible_cpu(cpu) {
r = svm_cpu_init(cpu);
if (r)
Has this been tested on the stable kernels? There's a recent bug report[*]
that suggests the 4.19 backport of this patch may be causing issues.
[*] https://bugzilla.kernel.org/show_bug.cgi?id=206795
On Tue, Mar 10, 2020 at 01:41:18PM +0100, Greg Kroah-Hartman wrote:
> From: Tom Lendacky <[email protected]>
>
> commit 52918ed5fcf05d97d257f4131e19479da18f5d16 upstream.
>
> The KVM MMIO support uses bit 51 as the reserved bit to cause nested page
> faults when a guest performs MMIO. The AMD memory encryption support uses
> a CPUID function to define the encryption bit position. Given this, it is
> possible that these bits can conflict.
>
> Use svm_hardware_setup() to override the MMIO mask if memory encryption
> support is enabled. Various checks are performed to ensure that the mask
> is properly defined and rsvd_bits() is used to generate the new mask (as
> was done prior to the change that necessitated this patch).
>
> Fixes: 28a1f3ac1d0c ("kvm: x86: Set highest physical address bits in non-present/reserved SPTEs")
> Suggested-by: Sean Christopherson <[email protected]>
> Reviewed-by: Sean Christopherson <[email protected]>
> Signed-off-by: Tom Lendacky <[email protected]>
> Signed-off-by: Paolo Bonzini <[email protected]>
> Signed-off-by: Greg Kroah-Hartman <[email protected]>
>
> ---
> arch/x86/kvm/svm.c | 43 +++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
>
> --- a/arch/x86/kvm/svm.c
> +++ b/arch/x86/kvm/svm.c
> @@ -1088,6 +1088,47 @@ static int avic_ga_log_notifier(u32 ga_t
> return 0;
> }
>
> +/*
> + * The default MMIO mask is a single bit (excluding the present bit),
> + * which could conflict with the memory encryption bit. Check for
> + * memory encryption support and override the default MMIO mask if
> + * memory encryption is enabled.
> + */
> +static __init void svm_adjust_mmio_mask(void)
> +{
> + unsigned int enc_bit, mask_bit;
> + u64 msr, mask;
> +
> + /* If there is no memory encryption support, use existing mask */
> + if (cpuid_eax(0x80000000) < 0x8000001f)
> + return;
> +
> + /* If memory encryption is not enabled, use existing mask */
> + rdmsrl(MSR_K8_SYSCFG, msr);
> + if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
> + return;
> +
> + enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
> + mask_bit = boot_cpu_data.x86_phys_bits;
> +
> + /* Increment the mask bit if it is the same as the encryption bit */
> + if (enc_bit == mask_bit)
> + mask_bit++;
> +
> + /*
> + * If the mask bit location is below 52, then some bits above the
> + * physical addressing limit will always be reserved, so use the
> + * rsvd_bits() function to generate the mask. This mask, along with
> + * the present bit, will be used to generate a page fault with
> + * PFER.RSV = 1.
> + *
> + * If the mask bit location is 52 (or above), then clear the mask.
> + */
> + mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
> +
> + kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
> +}
> +
> static __init int svm_hardware_setup(void)
> {
> int cpu;
> @@ -1123,6 +1164,8 @@ static __init int svm_hardware_setup(voi
> kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
> }
>
> + svm_adjust_mmio_mask();
> +
> for_each_possible_cpu(cpu) {
> r = svm_cpu_init(cpu);
> if (r)
>
>
On 3/10/20 1:19 PM, Sean Christopherson wrote:
> Has this been tested on the stable kernels? There's a recent bug report[*]
> that suggests the 4.19 backport of this patch may be causing issues.
I missed this went the stable patches went by... when backported to the
older version of kvm_mmu_set_mmio_spte_mask() in the stable kernels (4.14
and 4.19), the call should have been:
kvm_mmu_set_mmio_spte_mask(mask, mask) and not:
kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
The call in the original upstream patch was:
kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK);
Tom
>
> [*] https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.kernel.org%2Fshow_bug.cgi%3Fid%3D206795&data=02%7C01%7Cthomas.lendacky%40amd.com%7C559dd742543741e4bc7608d7c51fa1d5%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637194611958586378&sdata=k%2F3WUFrqvibbf%2FEaCFgOIhUWMZ%2BqHjawmmy1GII7KgA%3D&reserved=0
>
>
> On Tue, Mar 10, 2020 at 01:41:18PM +0100, Greg Kroah-Hartman wrote:
>> From: Tom Lendacky <[email protected]>
>>
>> commit 52918ed5fcf05d97d257f4131e19479da18f5d16 upstream.
>>
>> The KVM MMIO support uses bit 51 as the reserved bit to cause nested page
>> faults when a guest performs MMIO. The AMD memory encryption support uses
>> a CPUID function to define the encryption bit position. Given this, it is
>> possible that these bits can conflict.
>>
>> Use svm_hardware_setup() to override the MMIO mask if memory encryption
>> support is enabled. Various checks are performed to ensure that the mask
>> is properly defined and rsvd_bits() is used to generate the new mask (as
>> was done prior to the change that necessitated this patch).
>>
>> Fixes: 28a1f3ac1d0c ("kvm: x86: Set highest physical address bits in non-present/reserved SPTEs")
>> Suggested-by: Sean Christopherson <[email protected]>
>> Reviewed-by: Sean Christopherson <[email protected]>
>> Signed-off-by: Tom Lendacky <[email protected]>
>> Signed-off-by: Paolo Bonzini <[email protected]>
>> Signed-off-by: Greg Kroah-Hartman <[email protected]>
>>
>> ---
>> arch/x86/kvm/svm.c | 43 +++++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 43 insertions(+)
>>
>> --- a/arch/x86/kvm/svm.c
>> +++ b/arch/x86/kvm/svm.c
>> @@ -1088,6 +1088,47 @@ static int avic_ga_log_notifier(u32 ga_t
>> return 0;
>> }
>>
>> +/*
>> + * The default MMIO mask is a single bit (excluding the present bit),
>> + * which could conflict with the memory encryption bit. Check for
>> + * memory encryption support and override the default MMIO mask if
>> + * memory encryption is enabled.
>> + */
>> +static __init void svm_adjust_mmio_mask(void)
>> +{
>> + unsigned int enc_bit, mask_bit;
>> + u64 msr, mask;
>> +
>> + /* If there is no memory encryption support, use existing mask */
>> + if (cpuid_eax(0x80000000) < 0x8000001f)
>> + return;
>> +
>> + /* If memory encryption is not enabled, use existing mask */
>> + rdmsrl(MSR_K8_SYSCFG, msr);
>> + if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
>> + return;
>> +
>> + enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
>> + mask_bit = boot_cpu_data.x86_phys_bits;
>> +
>> + /* Increment the mask bit if it is the same as the encryption bit */
>> + if (enc_bit == mask_bit)
>> + mask_bit++;
>> +
>> + /*
>> + * If the mask bit location is below 52, then some bits above the
>> + * physical addressing limit will always be reserved, so use the
>> + * rsvd_bits() function to generate the mask. This mask, along with
>> + * the present bit, will be used to generate a page fault with
>> + * PFER.RSV = 1.
>> + *
>> + * If the mask bit location is 52 (or above), then clear the mask.
>> + */
>> + mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
>> +
>> + kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
>> +}
>> +
>> static __init int svm_hardware_setup(void)
>> {
>> int cpu;
>> @@ -1123,6 +1164,8 @@ static __init int svm_hardware_setup(voi
>> kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
>> }
>>
>> + svm_adjust_mmio_mask();
>> +
>> for_each_possible_cpu(cpu) {
>> r = svm_cpu_init(cpu);
>> if (r)
>>
>>
On 3/10/20 1:42 PM, Tom Lendacky wrote:
> On 3/10/20 1:19 PM, Sean Christopherson wrote:
>> Has this been tested on the stable kernels? There's a recent bug report[*]
>> that suggests the 4.19 backport of this patch may be causing issues.
>
> I missed this went the stable patches went by... when backported to the
> older version of kvm_mmu_set_mmio_spte_mask() in the stable kernels (4.14
> and 4.19), the call should have been:
>
> kvm_mmu_set_mmio_spte_mask(mask, mask) and not:
>
> kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
>
> The call in the original upstream patch was:
>
> kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK);
Greg,
I should have asked in the earlier email... how do you want to address this?
Thanks,
Tom
>
> Tom
>
>>
>> [*] https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.kernel.org%2Fshow_bug.cgi%3Fid%3D206795&data=02%7C01%7Cthomas.lendacky%40amd.com%7C559dd742543741e4bc7608d7c51fa1d5%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637194611958586378&sdata=k%2F3WUFrqvibbf%2FEaCFgOIhUWMZ%2BqHjawmmy1GII7KgA%3D&reserved=0
>>
>>
>> On Tue, Mar 10, 2020 at 01:41:18PM +0100, Greg Kroah-Hartman wrote:
>>> From: Tom Lendacky <[email protected]>
>>>
>>> commit 52918ed5fcf05d97d257f4131e19479da18f5d16 upstream.
>>>
>>> The KVM MMIO support uses bit 51 as the reserved bit to cause nested page
>>> faults when a guest performs MMIO. The AMD memory encryption support uses
>>> a CPUID function to define the encryption bit position. Given this, it is
>>> possible that these bits can conflict.
>>>
>>> Use svm_hardware_setup() to override the MMIO mask if memory encryption
>>> support is enabled. Various checks are performed to ensure that the mask
>>> is properly defined and rsvd_bits() is used to generate the new mask (as
>>> was done prior to the change that necessitated this patch).
>>>
>>> Fixes: 28a1f3ac1d0c ("kvm: x86: Set highest physical address bits in non-present/reserved SPTEs")
>>> Suggested-by: Sean Christopherson <[email protected]>
>>> Reviewed-by: Sean Christopherson <[email protected]>
>>> Signed-off-by: Tom Lendacky <[email protected]>
>>> Signed-off-by: Paolo Bonzini <[email protected]>
>>> Signed-off-by: Greg Kroah-Hartman <[email protected]>
>>>
>>> ---
>>> arch/x86/kvm/svm.c | 43 +++++++++++++++++++++++++++++++++++++++++++
>>> 1 file changed, 43 insertions(+)
>>>
>>> --- a/arch/x86/kvm/svm.c
>>> +++ b/arch/x86/kvm/svm.c
>>> @@ -1088,6 +1088,47 @@ static int avic_ga_log_notifier(u32 ga_t
>>> return 0;
>>> }
>>>
>>> +/*
>>> + * The default MMIO mask is a single bit (excluding the present bit),
>>> + * which could conflict with the memory encryption bit. Check for
>>> + * memory encryption support and override the default MMIO mask if
>>> + * memory encryption is enabled.
>>> + */
>>> +static __init void svm_adjust_mmio_mask(void)
>>> +{
>>> + unsigned int enc_bit, mask_bit;
>>> + u64 msr, mask;
>>> +
>>> + /* If there is no memory encryption support, use existing mask */
>>> + if (cpuid_eax(0x80000000) < 0x8000001f)
>>> + return;
>>> +
>>> + /* If memory encryption is not enabled, use existing mask */
>>> + rdmsrl(MSR_K8_SYSCFG, msr);
>>> + if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
>>> + return;
>>> +
>>> + enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
>>> + mask_bit = boot_cpu_data.x86_phys_bits;
>>> +
>>> + /* Increment the mask bit if it is the same as the encryption bit */
>>> + if (enc_bit == mask_bit)
>>> + mask_bit++;
>>> +
>>> + /*
>>> + * If the mask bit location is below 52, then some bits above the
>>> + * physical addressing limit will always be reserved, so use the
>>> + * rsvd_bits() function to generate the mask. This mask, along with
>>> + * the present bit, will be used to generate a page fault with
>>> + * PFER.RSV = 1.
>>> + *
>>> + * If the mask bit location is 52 (or above), then clear the mask.
>>> + */
>>> + mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
>>> +
>>> + kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
>>> +}
>>> +
>>> static __init int svm_hardware_setup(void)
>>> {
>>> int cpu;
>>> @@ -1123,6 +1164,8 @@ static __init int svm_hardware_setup(voi
>>> kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
>>> }
>>>
>>> + svm_adjust_mmio_mask();
>>> +
>>> for_each_possible_cpu(cpu) {
>>> r = svm_cpu_init(cpu);
>>> if (r)
>>>
>>>
On Tue, Mar 10, 2020 at 03:59:25PM -0500, Tom Lendacky wrote:
> On 3/10/20 1:42 PM, Tom Lendacky wrote:
> > On 3/10/20 1:19 PM, Sean Christopherson wrote:
> >> Has this been tested on the stable kernels? There's a recent bug report[*]
> >> that suggests the 4.19 backport of this patch may be causing issues.
> >
> > I missed this went the stable patches went by... when backported to the
> > older version of kvm_mmu_set_mmio_spte_mask() in the stable kernels (4.14
> > and 4.19), the call should have been:
> >
> > kvm_mmu_set_mmio_spte_mask(mask, mask) and not:
> >
> > kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
> >
> > The call in the original upstream patch was:
> >
> > kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK);
>
> Greg,
>
> I should have asked in the earlier email... how do you want to address this?
I will fix this up now, thanks for pointing out what I got wrong...
greg k-h