2020-03-16 14:33:21

by Jarkko Nikula

Subject: [PATCH] mfd: intel-lpss: Fix Intel Elkhart Lake LPSS I2C input clock

Intel Elkhart Lake LPSS I2C has 100 MHz input clock instead of 133 MHz
that was our preliminary information. This will result slower I2C bus
clock when driver calculates its timing parameters in case ACPI tables
don't provide them.

Slower I2C bus clock is allowed but let's fix this to match with
reality.

While at it, keep the same default I2C device properties as Intel
Broxton since it is not known do they need any update.

Signed-off-by: Jarkko Nikula <[email protected]>
---
For normal development cycle.
---
drivers/mfd/intel-lpss-pci.c | 21 +++++++++++++--------
1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/drivers/mfd/intel-lpss-pci.c b/drivers/mfd/intel-lpss-pci.c
index c40a6c7d0cf8..e48f00448551 100644
--- a/drivers/mfd/intel-lpss-pci.c
+++ b/drivers/mfd/intel-lpss-pci.c
@@ -139,6 +139,11 @@ static const struct intel_lpss_platform_info cnl_i2c_info = {
.properties = spt_i2c_properties,
};

+static const struct intel_lpss_platform_info ehl_i2c_info = {
+ .clk_rate = 100000000,
+ .properties = bxt_i2c_properties,
+};
+
static const struct pci_device_id intel_lpss_pci_ids[] = {
/* CML-LP */
{ PCI_VDEVICE(INTEL, 0x02a8), (kernel_ulong_t)&spt_uart_info },
@@ -231,15 +236,15 @@ static const struct pci_device_id intel_lpss_pci_ids[] = {
{ PCI_VDEVICE(INTEL, 0x4b2a), (kernel_ulong_t)&bxt_info },
{ PCI_VDEVICE(INTEL, 0x4b2b), (kernel_ulong_t)&bxt_info },
{ PCI_VDEVICE(INTEL, 0x4b37), (kernel_ulong_t)&bxt_info },
- { PCI_VDEVICE(INTEL, 0x4b44), (kernel_ulong_t)&bxt_i2c_info },
- { PCI_VDEVICE(INTEL, 0x4b45), (kernel_ulong_t)&bxt_i2c_info },
- { PCI_VDEVICE(INTEL, 0x4b4b), (kernel_ulong_t)&bxt_i2c_info },
- { PCI_VDEVICE(INTEL, 0x4b4c), (kernel_ulong_t)&bxt_i2c_info },
+ { PCI_VDEVICE(INTEL, 0x4b44), (kernel_ulong_t)&ehl_i2c_info },
+ { PCI_VDEVICE(INTEL, 0x4b45), (kernel_ulong_t)&ehl_i2c_info },
+ { PCI_VDEVICE(INTEL, 0x4b4b), (kernel_ulong_t)&ehl_i2c_info },
+ { PCI_VDEVICE(INTEL, 0x4b4c), (kernel_ulong_t)&ehl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x4b4d), (kernel_ulong_t)&bxt_uart_info },
- { PCI_VDEVICE(INTEL, 0x4b78), (kernel_ulong_t)&bxt_i2c_info },
- { PCI_VDEVICE(INTEL, 0x4b79), (kernel_ulong_t)&bxt_i2c_info },
- { PCI_VDEVICE(INTEL, 0x4b7a), (kernel_ulong_t)&bxt_i2c_info },
- { PCI_VDEVICE(INTEL, 0x4b7b), (kernel_ulong_t)&bxt_i2c_info },
+ { PCI_VDEVICE(INTEL, 0x4b78), (kernel_ulong_t)&ehl_i2c_info },
+ { PCI_VDEVICE(INTEL, 0x4b79), (kernel_ulong_t)&ehl_i2c_info },
+ { PCI_VDEVICE(INTEL, 0x4b7a), (kernel_ulong_t)&ehl_i2c_info },
+ { PCI_VDEVICE(INTEL, 0x4b7b), (kernel_ulong_t)&ehl_i2c_info },
/* JSL */
{ PCI_VDEVICE(INTEL, 0x4da8), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0x4da9), (kernel_ulong_t)&spt_uart_info },
--
2.25.1

2020-03-16 14:58:07

by Andy Shevchenko

Subject: Re: [PATCH] mfd: intel-lpss: Fix Intel Elkhart Lake LPSS I2C input clock

On Mon, Mar 16, 2020 at 04:32:24PM +0200, Jarkko Nikula wrote:
> Intel Elkhart Lake LPSS I2C has 100 MHz input clock instead of 133 MHz
> that was our preliminary information. This will result slower I2C bus
> clock when driver calculates its timing parameters in case ACPI tables
> don't provide them.
>
> Slower I2C bus clock is allowed but let's fix this to match with
> reality.
>
> While at it, keep the same default I2C device properties as Intel
> Broxton since it is not known do they need any update.

Reviewed-by: Andy Shevchenko <[email protected]>
Thanks!

>
> Signed-off-by: Jarkko Nikula <[email protected]>
> ---
> For normal development cycle.
> ---
> drivers/mfd/intel-lpss-pci.c | 21 +++++++++++++--------
> 1 file changed, 13 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/mfd/intel-lpss-pci.c b/drivers/mfd/intel-lpss-pci.c
> index c40a6c7d0cf8..e48f00448551 100644
> --- a/drivers/mfd/intel-lpss-pci.c
> +++ b/drivers/mfd/intel-lpss-pci.c
> @@ -139,6 +139,11 @@ static const struct intel_lpss_platform_info cnl_i2c_info = {
> .properties = spt_i2c_properties,
> };
>
> +static const struct intel_lpss_platform_info ehl_i2c_info = {
> + .clk_rate = 100000000,
> + .properties = bxt_i2c_properties,
> +};
> +
> static const struct pci_device_id intel_lpss_pci_ids[] = {
> /* CML-LP */
> { PCI_VDEVICE(INTEL, 0x02a8), (kernel_ulong_t)&spt_uart_info },
> @@ -231,15 +236,15 @@ static const struct pci_device_id intel_lpss_pci_ids[] = {
> { PCI_VDEVICE(INTEL, 0x4b2a), (kernel_ulong_t)&bxt_info },
> { PCI_VDEVICE(INTEL, 0x4b2b), (kernel_ulong_t)&bxt_info },
> { PCI_VDEVICE(INTEL, 0x4b37), (kernel_ulong_t)&bxt_info },
> - { PCI_VDEVICE(INTEL, 0x4b44), (kernel_ulong_t)&bxt_i2c_info },
> - { PCI_VDEVICE(INTEL, 0x4b45), (kernel_ulong_t)&bxt_i2c_info },
> - { PCI_VDEVICE(INTEL, 0x4b4b), (kernel_ulong_t)&bxt_i2c_info },
> - { PCI_VDEVICE(INTEL, 0x4b4c), (kernel_ulong_t)&bxt_i2c_info },
> + { PCI_VDEVICE(INTEL, 0x4b44), (kernel_ulong_t)&ehl_i2c_info },
> + { PCI_VDEVICE(INTEL, 0x4b45), (kernel_ulong_t)&ehl_i2c_info },
> + { PCI_VDEVICE(INTEL, 0x4b4b), (kernel_ulong_t)&ehl_i2c_info },
> + { PCI_VDEVICE(INTEL, 0x4b4c), (kernel_ulong_t)&ehl_i2c_info },
> { PCI_VDEVICE(INTEL, 0x4b4d), (kernel_ulong_t)&bxt_uart_info },
> - { PCI_VDEVICE(INTEL, 0x4b78), (kernel_ulong_t)&bxt_i2c_info },
> - { PCI_VDEVICE(INTEL, 0x4b79), (kernel_ulong_t)&bxt_i2c_info },
> - { PCI_VDEVICE(INTEL, 0x4b7a), (kernel_ulong_t)&bxt_i2c_info },
> - { PCI_VDEVICE(INTEL, 0x4b7b), (kernel_ulong_t)&bxt_i2c_info },
> + { PCI_VDEVICE(INTEL, 0x4b78), (kernel_ulong_t)&ehl_i2c_info },
> + { PCI_VDEVICE(INTEL, 0x4b79), (kernel_ulong_t)&ehl_i2c_info },
> + { PCI_VDEVICE(INTEL, 0x4b7a), (kernel_ulong_t)&ehl_i2c_info },
> + { PCI_VDEVICE(INTEL, 0x4b7b), (kernel_ulong_t)&ehl_i2c_info },
> /* JSL */
> { PCI_VDEVICE(INTEL, 0x4da8), (kernel_ulong_t)&spt_uart_info },
> { PCI_VDEVICE(INTEL, 0x4da9), (kernel_ulong_t)&spt_uart_info },
> --
> 2.25.1
>

--
With Best Regards,
Andy Shevchenko

2020-03-26 09:21:36

by Lee Jones

Subject: Re: [PATCH] mfd: intel-lpss: Fix Intel Elkhart Lake LPSS I2C input clock

On Mon, 16 Mar 2020, Jarkko Nikula wrote:

> Intel Elkhart Lake LPSS I2C has 100 MHz input clock instead of 133 MHz
> that was our preliminary information. This will result slower I2C bus
> clock when driver calculates its timing parameters in case ACPI tables
> don't provide them.
>
> Slower I2C bus clock is allowed but let's fix this to match with
> reality.
>
> While at it, keep the same default I2C device properties as Intel
> Broxton since it is not known do they need any update.
>
> Signed-off-by: Jarkko Nikula <[email protected]>
> ---
> For normal development cycle.
> ---
> drivers/mfd/intel-lpss-pci.c | 21 +++++++++++++--------
> 1 file changed, 13 insertions(+), 8 deletions(-)

Applied, thanks.

--
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
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