The USB support was initialy done with a set of PHYs and dwc3-of-simple
because the architecture of the USB complex was not understood correctly
at the time (and proper documentation was missing...).
But with the G12A family, the USB complex was correctly understood and
implemented correctly.
But seems the G12A architecture was derived for the GXL USB architecture,
with minor differences and looks we can share most of the USB DWC3 glue
driver.
This patchset refactors and adds callbacks to handle the architecture
difference while keeping the main code shared.
The main difference is that on GXL/GXM the USB2 PHY control registers
are mixed with the PHY registers (we already handle correctly), and
the GLUE registers are allmost (99%) the same as G12A.
But, the GXL/GXM HW is buggy, here are the quirks :
- for the DWC2 controller to reset correctly, the GLUE mux must be switched
to peripheral when the PHYs are powered up.
- when manually switching from Host to Device when the USB port is not
populated (should not happen with proper Micro-USB/USB-C OTG switch), it
makes the DWC3 to crash. The only way to avoid that is to use the Host
Disconnect bit to disconnect the DWC3 controller from the port, but we can't
recover the Host functionnality unless resetting the DWC3 controller.
This bit is set when only manual switch is done, and a warning is printed
on manual switching.
The patches 1-3 should be applied first, then either waiting the next release
or if the usb maintainer can provide us a stable tag, we can use it to merge
the DT and bindings.
Changes since v2 at [2]:
- Removed first 6 applied patches
- rebased on usb/testing/next
- Fixed dwc3_meson_g12a_usb2_init in patch 1
- Fixed leftover usage of dwc3_meson_g12a_usb_init in patch 1
- Moved post_init callback before child node probe to avoid bad dwc3 init
Changes since v1 at [1]:
- Fixed DT bindings to take in account usb2-phy2 on GXM
- Added comment in patch2
- Fixed patch 5 and moved fix out
- Collected tags
- Lower DT patch changes, switch p20x-q20x port B as OTG by default
[1] http://lkml.kernel.org/r/[email protected]
[2] http://lkml.kernel.org/r/[email protected]
Martin Blumenstingl (4):
arm64: dts: amlogic: use the new USB control driver for GXL and GXM
phy: amlogic: meson-gxl-usb3: remove code for non-existing PHY
usb: dwc3: of-simple: remove Amlogic GXL and AXG compatibles
dt-bindings: usb: dwc3: remove old DWC3 wrapper
Neil Armstrong (4):
usb: dwc3: meson-g12a: refactor usb init
usb: dwc3: meson-g12a: support the GXL/GXM DWC3 host phy disconnect
usb: dwc3: meson-g12a: add support for GXL and GXM SoCs
doc: dt: bindings: usb: dwc3: remove amlogic compatible entries
.../bindings/phy/meson-gxl-usb3-phy.txt | 31 --
.../devicetree/bindings/usb/amlogic,dwc3.txt | 42 ---
.../devicetree/bindings/usb/dwc3.txt | 2 -
.../dts/amlogic/meson-gx-libretech-pc.dtsi | 3 +-
.../boot/dts/amlogic/meson-gx-p23x-q20x.dtsi | 3 +-
.../amlogic/meson-gxl-s805x-libretech-ac.dts | 3 +-
.../boot/dts/amlogic/meson-gxl-s805x-p241.dts | 3 +-
.../amlogic/meson-gxl-s905d-phicomm-n1.dts | 4 +
.../boot/dts/amlogic/meson-gxl-s905w-p281.dts | 4 +
.../dts/amlogic/meson-gxl-s905w-tx3-mini.dts | 4 +
.../amlogic/meson-gxl-s905x-khadas-vim.dts | 4 +
.../amlogic/meson-gxl-s905x-libretech-cc.dts | 3 +-
.../amlogic/meson-gxl-s905x-nexbox-a95x.dts | 3 +-
.../dts/amlogic/meson-gxl-s905x-p212.dtsi | 3 +-
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 45 +--
.../dts/amlogic/meson-gxm-khadas-vim2.dts | 3 +-
.../boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 3 +-
.../boot/dts/amlogic/meson-gxm-vega-s96.dts | 4 +
arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 7 +-
drivers/phy/amlogic/Kconfig | 12 -
drivers/phy/amlogic/Makefile | 1 -
drivers/phy/amlogic/phy-meson-gxl-usb3.c | 283 ------------------
drivers/usb/dwc3/dwc3-meson-g12a.c | 188 +++++++++++-
drivers/usb/dwc3/dwc3-of-simple.c | 30 +-
24 files changed, 246 insertions(+), 442 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt
delete mode 100644 Documentation/devicetree/bindings/usb/amlogic,dwc3.txt
delete mode 100644 drivers/phy/amlogic/phy-meson-gxl-usb3.c
--
2.22.0
In order to add support for the Amlogic GXL/GXM USB Glue, this adds
the corresponding :
- PHY names
- clock names
- USB2 PHY init and mode set
- regmap setup
Signed-off-by: Neil Armstrong <[email protected]>
---
drivers/usb/dwc3/dwc3-meson-g12a.c | 102 ++++++++++++++++++++++++++++-
1 file changed, 101 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c
index cc0b8a253932..61507abb0ff7 100644
--- a/drivers/usb/dwc3/dwc3-meson-g12a.c
+++ b/drivers/usb/dwc3/dwc3-meson-g12a.c
@@ -101,6 +101,11 @@
#define PHY_COUNT 3
#define USB2_OTG_PHY 1
+static struct clk_bulk_data meson_gxl_clocks[] = {
+ { .id = "usb_ctrl" },
+ { .id = "ddr" },
+};
+
static struct clk_bulk_data meson_g12a_clocks[] = {
{ .id = NULL },
};
@@ -111,6 +116,10 @@ static struct clk_bulk_data meson_a1_clocks[] = {
{ .id = "xtal_usb_ctrl" },
};
+static const char *meson_gxm_phy_names[] = {
+ "usb2-phy0", "usb2-phy1", "usb2-phy2",
+};
+
static const char *meson_g12a_phy_names[] = {
"usb2-phy0", "usb2-phy1", "usb3-phy0",
};
@@ -145,16 +154,25 @@ struct dwc3_meson_g12a_drvdata {
int (*usb_post_init)(struct dwc3_meson_g12a *priv);
};
+static int dwc3_meson_gxl_setup_regmaps(struct dwc3_meson_g12a *priv,
+ void __iomem *base);
static int dwc3_meson_g12a_setup_regmaps(struct dwc3_meson_g12a *priv,
void __iomem *base);
static int dwc3_meson_g12a_usb2_init_phy(struct dwc3_meson_g12a *priv, int i,
- enum phy_mode mode);
+ enum phy_mode mode);
+static int dwc3_meson_gxl_usb2_init_phy(struct dwc3_meson_g12a *priv, int i,
+ enum phy_mode mode);
static int dwc3_meson_g12a_set_phy_mode(struct dwc3_meson_g12a *priv,
int i, enum phy_mode mode);
+static int dwc3_meson_gxl_set_phy_mode(struct dwc3_meson_g12a *priv,
+ int i, enum phy_mode mode);
static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv);
+static int dwc3_meson_gxl_usb_init(struct dwc3_meson_g12a *priv);
+
+static int dwc3_meson_gxl_usb_post_init(struct dwc3_meson_g12a *priv);
/*
* For GXL and GXM SoCs:
@@ -169,6 +187,34 @@ static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv);
* reset to recover usage of the port.
*/
+static struct dwc3_meson_g12a_drvdata gxl_drvdata = {
+ .otg_switch_supported = true,
+ .otg_phy_host_port_disable = true,
+ .clks = meson_gxl_clocks,
+ .num_clks = ARRAY_SIZE(meson_g12a_clocks),
+ .phy_names = meson_a1_phy_names,
+ .num_phys = ARRAY_SIZE(meson_a1_phy_names),
+ .setup_regmaps = dwc3_meson_gxl_setup_regmaps,
+ .usb2_init_phy = dwc3_meson_gxl_usb2_init_phy,
+ .set_phy_mode = dwc3_meson_gxl_set_phy_mode,
+ .usb_init = dwc3_meson_gxl_usb_init,
+ .usb_post_init = dwc3_meson_gxl_usb_post_init,
+};
+
+static struct dwc3_meson_g12a_drvdata gxm_drvdata = {
+ .otg_switch_supported = true,
+ .otg_phy_host_port_disable = true,
+ .clks = meson_gxl_clocks,
+ .num_clks = ARRAY_SIZE(meson_g12a_clocks),
+ .phy_names = meson_gxm_phy_names,
+ .num_phys = ARRAY_SIZE(meson_gxm_phy_names),
+ .setup_regmaps = dwc3_meson_gxl_setup_regmaps,
+ .usb2_init_phy = dwc3_meson_gxl_usb2_init_phy,
+ .set_phy_mode = dwc3_meson_gxl_set_phy_mode,
+ .usb_init = dwc3_meson_gxl_usb_init,
+ .usb_post_init = dwc3_meson_gxl_usb_post_init,
+};
+
static struct dwc3_meson_g12a_drvdata g12a_drvdata = {
.otg_switch_supported = true,
.clks = meson_g12a_clocks,
@@ -209,6 +255,21 @@ struct dwc3_meson_g12a {
const struct dwc3_meson_g12a_drvdata *drvdata;
};
+static int dwc3_meson_gxl_set_phy_mode(struct dwc3_meson_g12a *priv,
+ int i, enum phy_mode mode)
+{
+ return phy_set_mode(priv->phys[i], mode);
+}
+
+static int dwc3_meson_gxl_usb2_init_phy(struct dwc3_meson_g12a *priv, int i,
+ enum phy_mode mode)
+{
+ /* On GXL PHY must be started in device mode for DWC2 init */
+ return priv->drvdata->set_phy_mode(priv, i,
+ (i == USB2_OTG_PHY) ? PHY_MODE_USB_DEVICE
+ : PHY_MODE_USB_HOST);
+}
+
static int dwc3_meson_g12a_set_phy_mode(struct dwc3_meson_g12a *priv,
int i, enum phy_mode mode)
{
@@ -558,6 +619,18 @@ static int dwc3_meson_g12a_otg_init(struct platform_device *pdev,
return 0;
}
+static int dwc3_meson_gxl_setup_regmaps(struct dwc3_meson_g12a *priv,
+ void __iomem *base)
+{
+ /* GXL controls the PHY mode in the PHY registers unlike G12A */
+ priv->usb_glue_regmap = devm_regmap_init_mmio(priv->dev, base,
+ &phy_meson_g12a_usb_glue_regmap_conf);
+ if (IS_ERR(priv->usb_glue_regmap))
+ return PTR_ERR(priv->usb_glue_regmap);
+
+ return 0;
+}
+
static int dwc3_meson_g12a_setup_regmaps(struct dwc3_meson_g12a *priv,
void __iomem *base)
{
@@ -598,6 +671,25 @@ static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv)
return dwc3_meson_g12a_usb_init_glue(priv, priv->otg_phy_mode);
}
+static int dwc3_meson_gxl_usb_init(struct dwc3_meson_g12a *priv)
+{
+ return dwc3_meson_g12a_usb_init_glue(priv, PHY_MODE_USB_DEVICE);
+}
+
+static int dwc3_meson_gxl_usb_post_init(struct dwc3_meson_g12a *priv)
+{
+ int ret;
+
+ ret = priv->drvdata->set_phy_mode(priv, USB2_OTG_PHY,
+ priv->otg_phy_mode);
+ if (ret)
+ return ret;
+
+ dwc3_meson_g12a_usb_otg_apply_mode(priv, priv->otg_phy_mode);
+
+ return 0;
+}
+
static int dwc3_meson_g12a_probe(struct platform_device *pdev)
{
struct dwc3_meson_g12a *priv;
@@ -829,6 +921,14 @@ static const struct dev_pm_ops dwc3_meson_g12a_dev_pm_ops = {
};
static const struct of_device_id dwc3_meson_g12a_match[] = {
+ {
+ .compatible = "amlogic,meson-gxl-usb-ctrl",
+ .data = &gxl_drvdata,
+ },
+ {
+ .compatible = "amlogic,meson-gxm-usb-ctrl",
+ .data = &gxm_drvdata,
+ },
{
.compatible = "amlogic,meson-g12a-usb-ctrl",
.data = &g12a_drvdata,
--
2.22.0
On the Amlogic GXL/GXM SoCs, the OTG PHY status signals are always
connected to the DWC3 controller, thus crashing the controller when
switching to OTG mode when port is not populated with a device/cable to
Host.
Amlogic added a bit to disconnect the OTG PHY status signals from the DWC3
to be used when switching the OTG PHY as Device to the DWC2 controller.
The drawback is that it makes the DWC3 port state machine stall and needs
a full reset of the DWC3 controller to get connect status to the port
connected to the OTG PHY, but not the other one.
Signed-off-by: Neil Armstrong <[email protected]>
---
drivers/usb/dwc3/dwc3-meson-g12a.c | 34 ++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c
index e7a6d05f2a72..cc0b8a253932 100644
--- a/drivers/usb/dwc3/dwc3-meson-g12a.c
+++ b/drivers/usb/dwc3/dwc3-meson-g12a.c
@@ -131,6 +131,7 @@ struct dwc3_meson_g12a;
struct dwc3_meson_g12a_drvdata {
bool otg_switch_supported;
+ bool otg_phy_host_port_disable;
struct clk_bulk_data *clks;
int num_clks;
const char **phy_names;
@@ -155,6 +156,19 @@ static int dwc3_meson_g12a_set_phy_mode(struct dwc3_meson_g12a *priv,
static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv);
+/*
+ * For GXL and GXM SoCs:
+ * USB Phy muxing between the DWC2 Device controller and the DWC3 Host
+ * controller is buggy when switching from Device to Host when USB port
+ * is unpopulated, it causes the DWC3 to hard crash.
+ * When populated (including OTG switching with ID pin), the switch works
+ * like a charm like on the G12A platforms.
+ * In order to still switch from Host to Device on an USB Type-A port,
+ * an U2_PORT_DISABLE bit has been added to disconnect the DWC3 Host
+ * controller from the port, but when used the DWC3 controller must be
+ * reset to recover usage of the port.
+ */
+
static struct dwc3_meson_g12a_drvdata g12a_drvdata = {
.otg_switch_supported = true,
.clks = meson_g12a_clocks,
@@ -290,6 +304,13 @@ static void dwc3_meson_g12a_usb_otg_apply_mode(struct dwc3_meson_g12a *priv,
enum phy_mode mode)
{
if (mode == PHY_MODE_USB_DEVICE) {
+ if (priv->otg_mode != USB_DR_MODE_OTG &&
+ priv->drvdata->otg_phy_host_port_disable)
+ /* Isolate the OTG PHY port from the Host Controller */
+ regmap_update_bits(priv->usb_glue_regmap, USB_R1,
+ USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK,
+ FIELD_PREP(USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK,
+ BIT(USB2_OTG_PHY)));
regmap_update_bits(priv->usb_glue_regmap, USB_R0,
USB_R0_U2D_ACT, USB_R0_U2D_ACT);
regmap_update_bits(priv->usb_glue_regmap, USB_R0,
@@ -297,6 +318,12 @@ static void dwc3_meson_g12a_usb_otg_apply_mode(struct dwc3_meson_g12a *priv,
regmap_update_bits(priv->usb_glue_regmap, USB_R4,
USB_R4_P21_SLEEP_M0, USB_R4_P21_SLEEP_M0);
} else {
+ if (priv->otg_mode != USB_DR_MODE_OTG &&
+ priv->drvdata->otg_phy_host_port_disable) {
+ regmap_update_bits(priv->usb_glue_regmap, USB_R1,
+ USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK, 0);
+ msleep(500);
+ }
regmap_update_bits(priv->usb_glue_regmap, USB_R0,
USB_R0_U2D_ACT, 0);
regmap_update_bits(priv->usb_glue_regmap, USB_R4,
@@ -430,6 +457,13 @@ static int dwc3_meson_g12a_role_set(struct usb_role_switch *sw,
if (mode == priv->otg_phy_mode)
return 0;
+ if (priv->drvdata->otg_phy_host_port_disable)
+ dev_warn_once(priv->dev, "Manual OTG switch is broken on this "\
+ "SoC, when manual switching from "\
+ "Host to device, DWC3 controller "\
+ "will need to be resetted in order "\
+ "to recover usage of the Host port");
+
return dwc3_meson_g12a_otg_mode_set(priv, mode);
}
--
2.22.0
From: Martin Blumenstingl <[email protected]>
There is now an updated bindings for these SoCs making the old
compatible obsolete.
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Martin Blumenstingl <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
---
.../devicetree/bindings/usb/amlogic,dwc3.txt | 42 -------------------
1 file changed, 42 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/usb/amlogic,dwc3.txt
diff --git a/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt b/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt
deleted file mode 100644
index 9a8b631904fd..000000000000
--- a/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-Amlogic Meson GX DWC3 USB SoC controller
-
-Required properties:
-- compatible: depending on the SoC this should contain one of:
- * amlogic,meson-axg-dwc3
- * amlogic,meson-gxl-dwc3
-- clocks: a handle for the "USB general" clock
-- clock-names: must be "usb_general"
-- resets: a handle for the shared "USB OTG" reset line
-- reset-names: must be "usb_otg"
-
-Required child node:
-A child node must exist to represent the core DWC3 IP block. The name of
-the node is not important. The content of the node is defined in dwc3.txt.
-
-PHY documentation is provided in the following places:
-- Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt
-- Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt
-
-Example device nodes:
- usb0: usb@ff500000 {
- compatible = "amlogic,meson-axg-dwc3";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- clocks = <&clkc CLKID_USB>;
- clock-names = "usb_general";
- resets = <&reset RESET_USB_OTG>;
- reset-names = "usb_otg";
-
- dwc3: dwc3@ff500000 {
- compatible = "snps,dwc3";
- reg = <0x0 0xff500000 0x0 0x100000>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- maximum-speed = "high-speed";
- snps,dis_u2_susphy_quirk;
- phys = <&usb3_phy>, <&usb2_phy0>;
- phy-names = "usb2-phy", "usb3-phy";
- };
- };
--
2.22.0
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
---
Documentation/devicetree/bindings/usb/dwc3.txt | 2 --
1 file changed, 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 9946ff9ba735..d03edf9d3935 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -15,8 +15,6 @@ Required properties:
Exception for clocks:
clocks are optional if the parent node (i.e. glue-layer) is compatible to
one of the following:
- "amlogic,meson-axg-dwc3"
- "amlogic,meson-gxl-dwc3"
"cavium,octeon-7130-usb-uctl"
"qcom,dwc3"
"samsung,exynos5250-dwusb3"
--
2.22.0
From: Martin Blumenstingl <[email protected]>
Add the correcly architectured USB Glue node and adapt all the Amlogic
GXL and GXM board to the new organization.
Signed-off-by: Martin Blumenstingl <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
---
.../dts/amlogic/meson-gx-libretech-pc.dtsi | 3 +-
.../boot/dts/amlogic/meson-gx-p23x-q20x.dtsi | 3 +-
.../amlogic/meson-gxl-s805x-libretech-ac.dts | 3 +-
.../boot/dts/amlogic/meson-gxl-s805x-p241.dts | 3 +-
.../amlogic/meson-gxl-s905d-phicomm-n1.dts | 4 ++
.../boot/dts/amlogic/meson-gxl-s905w-p281.dts | 4 ++
.../dts/amlogic/meson-gxl-s905w-tx3-mini.dts | 4 ++
.../amlogic/meson-gxl-s905x-khadas-vim.dts | 4 ++
.../amlogic/meson-gxl-s905x-libretech-cc.dts | 3 +-
.../amlogic/meson-gxl-s905x-nexbox-a95x.dts | 3 +-
.../dts/amlogic/meson-gxl-s905x-p212.dtsi | 3 +-
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 45 ++++++++++---------
.../dts/amlogic/meson-gxm-khadas-vim2.dts | 3 +-
.../boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 3 +-
.../boot/dts/amlogic/meson-gxm-vega-s96.dts | 4 ++
arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 7 ++-
16 files changed, 68 insertions(+), 31 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi
index 248b018c83d5..ed9f89ee86a8 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi
@@ -360,8 +360,9 @@
status = "okay";
};
-&usb0 {
+&usb {
status = "okay";
+ dr_mode = "host";
};
&usb2_phy0 {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
index 12d5e333e5f2..d853981f1ab5 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
@@ -223,6 +223,7 @@
pinctrl-names = "default";
};
-&usb0 {
+&usb {
status = "okay";
+ dr_mode = "otg";
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts
index 4d5949496596..2cfea3094f6c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts
@@ -243,6 +243,7 @@
pinctrl-names = "default";
};
-&usb0 {
+&usb {
status = "okay";
+ dr_mode = "host";
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts
index a1119cfb0280..867e30f1d62b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts
@@ -216,6 +216,7 @@
pinctrl-names = "default";
};
-&usb0 {
+&usb {
status = "okay";
+ dr_mode = "host";
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts
index b5667f1fb2c8..9ef210f17b4a 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts
@@ -29,3 +29,7 @@
&cvbs_vdac_port {
status = "disabled";
};
+
+&usb {
+ dr_mode = "host";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts
index 6509c4950950..ecc9df7ca023 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts
@@ -20,3 +20,7 @@
reg = <0x0 0x0 0x0 0x40000000>;
};
};
+
+&usb {
+ dr_mode = "host";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts
index dd729ac2300d..6705c2082a78 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts
@@ -24,3 +24,7 @@
&ir {
linux,rc-map-name = "rc-tanix-tx3mini";
};
+
+&usb {
+ dr_mode = "host";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
index 440bc23c7342..8bcdffdf55d0 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
@@ -207,3 +207,7 @@
pinctrl-0 = <&uart_ao_b_pins>;
pinctrl-names = "default";
};
+
+&usb {
+ dr_mode = "peripheral";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
index e8348b2728db..e493831a80f0 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
@@ -272,8 +272,9 @@
pinctrl-names = "default";
};
-&usb0 {
+&usb {
status = "okay";
+ dr_mode = "host";
};
&usb2_phy0 {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
index 62dd87821ce5..f1acca5c4434 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
@@ -218,6 +218,7 @@
pinctrl-names = "default";
};
-&usb0 {
+&usb {
status = "okay";
+ dr_mode = "host";
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
index 6ac678f88bd8..05cb2f5e5c36 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
@@ -195,8 +195,9 @@
pinctrl-names = "default";
};
-&usb0 {
+&usb {
status = "okay";
+ dr_mode = "host";
};
&usb2_phy0 {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index 259d86399390..95b301a7c725 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -14,26 +14,43 @@
compatible = "amlogic,meson-gxl";
soc {
- usb0: usb@c9000000 {
- status = "disabled";
- compatible = "amlogic,meson-gxl-dwc3";
+ usb: usb@d0078080 {
+ compatible = "amlogic,meson-gxl-usb-ctrl";
+ reg = <0x0 0xd0078080 0x0 0x20>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
- clocks = <&clkc CLKID_USB>;
- clock-names = "usb_general";
+ clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
+ clock-names = "usb_ctrl", "ddr";
resets = <&reset RESET_USB_OTG>;
- reset-names = "usb_otg";
- dwc3: dwc3@c9000000 {
+ dr_mode = "otg";
+
+ phys = <&usb2_phy0>, <&usb2_phy1>;
+ phy-names = "usb2-phy0", "usb2-phy1";
+
+ dwc2: usb@c9100000 {
+ compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
+ reg = <0x0 0xc9100000 0x0 0x40000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc CLKID_USB1>;
+ clock-names = "otg";
+ phys = <&usb2_phy1>;
+ dr_mode = "peripheral";
+ g-rx-fifo-size = <192>;
+ g-np-tx-fifo-size = <128>;
+ g-tx-fifo-size = <128 128 16 16 16>;
+ };
+
+ dwc3: usb@c9000000 {
compatible = "snps,dwc3";
reg = <0x0 0xc9000000 0x0 0x100000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
maximum-speed = "high-speed";
snps,dis_u2_susphy_quirk;
- phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>;
};
};
@@ -71,18 +88,6 @@
reset-names = "phy";
status = "okay";
};
-
- usb3_phy: phy@78080 {
- compatible = "amlogic,meson-gxl-usb3-phy";
- #phy-cells = <0>;
- reg = <0x0 0x78080 0x0 0x20>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>;
- clock-names = "phy", "peripheral";
- resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>;
- reset-names = "phy", "peripheral";
- status = "okay";
- };
};
&efuse {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
index 27eeab71ec77..bff8ec2c1c70 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
@@ -380,6 +380,7 @@
vref-supply = <&vddio_ao18>;
};
-&usb0 {
+&usb {
status = "okay";
+ dr_mode = "peripheral";
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
index c2bd4dbbf38c..83eca3af44ce 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
@@ -179,6 +179,7 @@
pinctrl-names = "default";
};
-&usb0 {
+&usb {
status = "okay";
+ dr_mode = "host";
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts
index 0bdf51d041ae..d3fdba4da9a6 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts
@@ -39,3 +39,7 @@
&ir {
linux,rc-map-name = "rc-vega-s9x";
};
+
+&usb {
+ dr_mode = "host";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
index b6f89f108e28..40e3e123e05b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
@@ -169,8 +169,11 @@
compatible = "amlogic,meson-gxm-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
};
-&dwc3 {
- phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>;
+&usb {
+ compatible = "amlogic,meson-gxm-usb-ctrl";
+
+ phy-names = "usb2-phy0", "usb2-phy1", "usb2-phy2";
+ phys = <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>;
};
&vdec {
--
2.22.0
On Thu, Apr 16, 2020 at 2:19 PM Neil Armstrong <[email protected]> wrote:
>
> On the Amlogic GXL/GXM SoCs, the OTG PHY status signals are always
> connected to the DWC3 controller, thus crashing the controller when
> switching to OTG mode when port is not populated with a device/cable to
> Host.
>
> Amlogic added a bit to disconnect the OTG PHY status signals from the DWC3
> to be used when switching the OTG PHY as Device to the DWC2 controller.
>
> The drawback is that it makes the DWC3 port state machine stall and needs
> a full reset of the DWC3 controller to get connect status to the port
> connected to the OTG PHY, but not the other one.
>
> Signed-off-by: Neil Armstrong <[email protected]>
one nit-pick below. apart from that:
Reviewed-by: Martin Blumenstingl <[email protected]>
[...]
> if (mode == PHY_MODE_USB_DEVICE) {
> + if (priv->otg_mode != USB_DR_MODE_OTG &&
> + priv->drvdata->otg_phy_host_port_disable)
> + /* Isolate the OTG PHY port from the Host Controller */
> + regmap_update_bits(priv->usb_glue_regmap, USB_R1,
> + USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK,
> + FIELD_PREP(USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK,
> + BIT(USB2_OTG_PHY)));
if you have to re-send for whatever reason then I would like an empty
line here to make the code easier to read
> regmap_update_bits(priv->usb_glue_regmap, USB_R0,
> USB_R0_U2D_ACT, USB_R0_U2D_ACT);
> regmap_update_bits(priv->usb_glue_regmap, USB_R0,
> @@ -297,6 +318,12 @@ static void dwc3_meson_g12a_usb_otg_apply_mode(struct dwc3_meson_g12a *priv,
> regmap_update_bits(priv->usb_glue_regmap, USB_R4,
> USB_R4_P21_SLEEP_M0, USB_R4_P21_SLEEP_M0);
> } else {
> + if (priv->otg_mode != USB_DR_MODE_OTG &&
> + priv->drvdata->otg_phy_host_port_disable) {
> + regmap_update_bits(priv->usb_glue_regmap, USB_R1,
> + USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK, 0);
> + msleep(500);
> + }
same as above - if you have to re-send for whatever reason then please
add an empty line here
On Thu, Apr 16, 2020 at 2:19 PM Neil Armstrong <[email protected]> wrote:
>
> In order to add support for the Amlogic GXL/GXM USB Glue, this adds
> the corresponding :
super nit-pick: if you have to re-send this for whatever reason, then
please add "new compatible strings with" before "the corresponding"
> - PHY names
> - clock names
> - USB2 PHY init and mode set
> - regmap setup
>
> Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Martin Blumenstingl <[email protected]>