The CPU on Qualcomm's IPQ6018 devices are primarily fed by APSS PLL and XO,
these are connected to a clock mux and enable block.
This patch series adds support for these clocks and inturn enables clocks
required for CPU freq.
[V4]
* Re-written PLL found on IPQ platforms as a separate driver
* Addressed stephen's comments on apss clock controller and pll
* Addressed Rob's review comments on bindings
* moved a53 pll binding from this series as it is not applicable, will send
it separately.
[V3]
* Fixed dt binding check error in patch2
dt-bindings: clock: Add YAML schemas for QCOM A53 PLL
[V2]
* Restructred the patch series as there are two different HW blocks,
the mux and enable belongs to the apcs block and PLL has a separate HW
block.
* Converted qcom mailbox and qcom a53 pll documentation to yaml.
* Addressed review comments from Stephen, Rob and Sibi where it is applicable.
* Changed this cover letter to state the purpose of this patch series
Sivaprakash Murugesan (8):
dt-bindings: mailbox: Add YAML schemas for QCOM APCS global block
dt-bindings: clock: Add schema for QCOM IPQ apss pll
clk: qcom: Add ipq apss pll driver
clk: qcom: Add DT bindings for ipq6018 apss clock controller
clk: qcom: Add ipq apss clock controller
dt-bindings: mailbox: Add dt-bindings for ipq6018 apcs global block
mailbox: qcom: Add ipq6018 apcs compatible
arm64: dts: ipq6018: Add a53 pll and apcs clock
.../bindings/clock/qcom,ipq-apsspll.yaml | 49 ++++++++++
.../bindings/mailbox/qcom,apcs-kpss-global.txt | 88 -----------------
.../bindings/mailbox/qcom,apcs-kpss-global.yaml | 99 +++++++++++++++++++
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 +++-
drivers/clk/qcom/Kconfig | 19 ++++
drivers/clk/qcom/Makefile | 2 +
drivers/clk/qcom/apss-ipq-pll.c | 97 +++++++++++++++++++
drivers/clk/qcom/apss-ipq.c | 106 +++++++++++++++++++++
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 26 +++--
include/dt-bindings/clock/qcom,apss-ipq.h | 12 +++
10 files changed, 414 insertions(+), 100 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq-apsspll.yaml
delete mode 100644 Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
create mode 100644 Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
create mode 100644 drivers/clk/qcom/apss-ipq-pll.c
create mode 100644 drivers/clk/qcom/apss-ipq.c
create mode 100644 include/dt-bindings/clock/qcom,apss-ipq.h
--
2.7.4
Add dt-binding for apss pll found on QCOM IPQ platforms
Signed-off-by: Sivaprakash Murugesan <[email protected]>
---
.../bindings/clock/qcom,ipq-apsspll.yaml | 49 ++++++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq-apsspll.yaml
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq-apsspll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq-apsspll.yaml
new file mode 100644
index 0000000..dd12ec4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq-apsspll.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,ipq-apsspll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm IPQ APSS PLL Binding
+
+maintainers:
+ - Sivaprakash Murugesan <[email protected]>
+
+description:
+ The APSS PLL is the main clock that feds the CPUs on QCOM IPQ platforms.
+ It can support frequencies above 1GHz.
+
+properties:
+ compatible:
+ const: qcom,ipq-apss-pll
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 0
+
+ clocks:
+ items:
+ - description: board XO clock
+
+ clock-names:
+ items:
+ - const: xo
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ a53pll_ipq: clock@b116000 {
+ compatible = "qcom,ipq-apss-pll";
+ reg = <0x0b116000 0x40>;
+ #clock-cells = <0>;
+ clocks = <&xo>;
+ clock-names = "xo";
+ };
--
2.7.4
add support for apps pll and apcs clock.
Signed-off-by: Sivaprakash Murugesan <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 1aa8d85..af2ceeb 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -294,12 +294,22 @@
};
apcs_glb: mailbox@b111000 {
- compatible = "qcom,ipq8074-apcs-apps-global";
- reg = <0x0b111000 0xc>;
-
+ compatible = "qcom,ipq6018-apcs-apps-global";
+ reg = <0x0b111000 0x1000>;
+ #clock-cells = <1>;
+ clocks = <&apsspll>, <&xo>;
+ clock-names = "pll", "xo";
#mbox-cells = <1>;
};
+ apsspll: clock@b116000 {
+ compatible = "qcom,ipq-apss-pll";
+ reg = <0x0b116000 0x40>;
+ #clock-cells = <0>;
+ clocks = <&xo>;
+ clock-names = "xo";
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
--
2.7.4
On Sun 03 May 23:20 PDT 2020, Sivaprakash Murugesan wrote:
> Add dt-binding for apss pll found on QCOM IPQ platforms
>
> Signed-off-by: Sivaprakash Murugesan <[email protected]>
This seems quite similar to the existing qcom,a53pll binding, can't you
just describe both in the same binding?
> ---
> .../bindings/clock/qcom,ipq-apsspll.yaml | 49 ++++++++++++++++++++++
> 1 file changed, 49 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq-apsspll.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq-apsspll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq-apsspll.yaml
> new file mode 100644
> index 0000000..dd12ec4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq-apsspll.yaml
> @@ -0,0 +1,49 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,ipq-apsspll.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm IPQ APSS PLL Binding
> +
> +maintainers:
> + - Sivaprakash Murugesan <[email protected]>
> +
> +description:
> + The APSS PLL is the main clock that feds the CPUs on QCOM IPQ platforms.
> + It can support frequencies above 1GHz.
> +
> +properties:
> + compatible:
> + const: qcom,ipq-apss-pll
Allow me to claim that this is not the last IPQ, with an APSS PLL, which
means that this compatible is no good.
I think you want a compatible on the format qcom,ipq<numbers>-a53pll.
Regards,
Bjorn
> +
> + reg:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 0
> +
> + clocks:
> + items:
> + - description: board XO clock
> +
> + clock-names:
> + items:
> + - const: xo
> +
> +required:
> + - compatible
> + - reg
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + a53pll_ipq: clock@b116000 {
> + compatible = "qcom,ipq-apss-pll";
> + reg = <0x0b116000 0x40>;
> + #clock-cells = <0>;
> + clocks = <&xo>;
> + clock-names = "xo";
> + };
> --
> 2.7.4
>
On Sun 03 May 23:20 PDT 2020, Sivaprakash Murugesan wrote:
> add support for apps pll and apcs clock.
>
> Signed-off-by: Sivaprakash Murugesan <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 +++++++++++++---
> 1 file changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> index 1aa8d85..af2ceeb 100644
> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> @@ -294,12 +294,22 @@
> };
>
> apcs_glb: mailbox@b111000 {
> - compatible = "qcom,ipq8074-apcs-apps-global";
> - reg = <0x0b111000 0xc>;
> -
> + compatible = "qcom,ipq6018-apcs-apps-global";
> + reg = <0x0b111000 0x1000>;
My documentation states that IPQ8074 indeed has this block at
0x0b111000, but IPQ6018 it's at 0x6b111000. Can you confirm this is
correct? Same with the pll below.
Apart from that the patch looks good.
Regards,
Bjorn
> + #clock-cells = <1>;
> + clocks = <&apsspll>, <&xo>;
> + clock-names = "pll", "xo";
> #mbox-cells = <1>;
> };
>
> + apsspll: clock@b116000 {
> + compatible = "qcom,ipq-apss-pll";
> + reg = <0x0b116000 0x40>;
> + #clock-cells = <0>;
> + clocks = <&xo>;
> + clock-names = "xo";
> + };
> +
> timer {
> compatible = "arm,armv8-timer";
> interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> --
> 2.7.4
>
Hi Bjorn,
On 5/13/2020 1:54 AM, Bjorn Andersson wrote:
> On Sun 03 May 23:20 PDT 2020, Sivaprakash Murugesan wrote:
>
>> add support for apps pll and apcs clock.
>>
>> Signed-off-by: Sivaprakash Murugesan <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 +++++++++++++---
>> 1 file changed, 13 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>> index 1aa8d85..af2ceeb 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>> @@ -294,12 +294,22 @@
>> };
>>
>> apcs_glb: mailbox@b111000 {
>> - compatible = "qcom,ipq8074-apcs-apps-global";
>> - reg = <0x0b111000 0xc>;
>> -
>> + compatible = "qcom,ipq6018-apcs-apps-global";
>> + reg = <0x0b111000 0x1000>;
> My documentation states that IPQ8074 indeed has this block at
> 0x0b111000, but IPQ6018 it's at 0x6b111000. Can you confirm this is
> correct? Same with the pll below.
The address 0x6b111000 is how the RPM sees this block. For A53 it is
still 0xb111000
>
> Apart from that the patch looks good.
>
> Regards,
> Bjorn
On Tue 12 May 20:55 PDT 2020, Sivaprakash Murugesan wrote:
> Hi Bjorn,
>
> On 5/13/2020 1:54 AM, Bjorn Andersson wrote:
> > On Sun 03 May 23:20 PDT 2020, Sivaprakash Murugesan wrote:
> >
> > > add support for apps pll and apcs clock.
> > >
> > > Signed-off-by: Sivaprakash Murugesan <[email protected]>
> > > ---
> > > arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 +++++++++++++---
> > > 1 file changed, 13 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> > > index 1aa8d85..af2ceeb 100644
> > > --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> > > @@ -294,12 +294,22 @@
> > > };
> > > apcs_glb: mailbox@b111000 {
> > > - compatible = "qcom,ipq8074-apcs-apps-global";
> > > - reg = <0x0b111000 0xc>;
> > > -
> > > + compatible = "qcom,ipq6018-apcs-apps-global";
> > > + reg = <0x0b111000 0x1000>;
> > My documentation states that IPQ8074 indeed has this block at
> > 0x0b111000, but IPQ6018 it's at 0x6b111000. Can you confirm this is
> > correct? Same with the pll below.
> The address 0x6b111000 is how the RPM sees this block. For A53 it is still
> 0xb111000
Okay, thanks for confirming.
Regards,
Bjorn
On 5/13/2020 1:26 AM, Bjorn Andersson wrote:
> On Sun 03 May 23:20 PDT 2020, Sivaprakash Murugesan wrote:
>
>> Add dt-binding for apss pll found on QCOM IPQ platforms
>>
>> Signed-off-by: Sivaprakash Murugesan <[email protected]>
> This seems quite similar to the existing qcom,a53pll binding, can't you
> just describe both in the same binding?
ok.