From: Anurag Kumar Vulisha <[email protected]>
Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed
Processing System Gigabit Transceiver which provides PHY capabilities to
USB, SATA, PCIE, Display Port and Ehernet SGMII controllers.
Signed-off-by: Anurag Kumar Vulisha <[email protected]>
Signed-off-by: Laurent Pinchart <[email protected]>
---
Changes since v7:
- Switch to GPL-2.0-only OR BSD-2-Clause
Changes since v6:
- Fixed specification of compatible-dependent xlnx,tx-termination-fix
property
- Dropped status property from example
- Use 4 spaces to indent example
Changes since v5:
- Document clocks and clock-names properties
- Document resets and reset-names properties
- Replace subnodes with an additional entry in the PHY cells
- Drop lane frequency PHY cell, replaced by reference clock phandle
- Convert bindings to YAML
- Reword the subject line
- Drop Rob's R-b as the bindings have significantly changed
- Drop resets and reset-names properties
---
.../bindings/phy/xlnx,zynqmp-psgtr.yaml | 105 ++++++++++++++++++
include/dt-bindings/phy/phy.h | 1 +
2 files changed, 106 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
diff --git a/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml b/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
new file mode 100644
index 000000000000..09e3cde7ebca
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx ZynqMP Gigabit Transceiver PHY Device Tree Bindings
+
+maintainers:
+ - Laurent Pinchart <[email protected]>
+
+description: |
+ This binding describes the Xilinx ZynqMP Gigabit Transceiver (GTR) PHY. The
+ GTR provides four lanes and is used by USB, SATA, PCIE, Display port and
+ Ethernet SGMII controllers.
+
+properties:
+ "#phy-cells":
+ const: 4
+ description: |
+ The cells contain the following arguments.
+
+ - description: The GTR lane
+ minimum: 0
+ maximum: 3
+ - description: The PHY type
+ enum:
+ - PHY_TYPE_DP
+ - PHY_TYPE_PCIE
+ - PHY_TYPE_SATA
+ - PHY_TYPE_SGMII
+ - PHY_TYPE_USB
+ - description: The PHY instance
+ minimum: 0
+ maximum: 1 # for DP, SATA or USB
+ maximum: 3 # for PCIE or SGMII
+ - description: The reference clock number
+ minimum: 0
+ maximum: 3
+
+ compatible:
+ enum:
+ - xlnx,zynqmp-psgtr-v1.1
+ - xlnx,zynqmp-psgtr
+
+ clocks:
+ minItems: 1
+ maxItems: 4
+ description: |
+ Clock for each PS_MGTREFCLK[0-3] reference clock input. Unconnected
+ inputs shall not have an entry.
+
+ clock-names:
+ minItems: 1
+ maxItems: 4
+ items:
+ pattern: "^ref[0-3]$"
+
+ reg:
+ items:
+ - description: SERDES registers block
+ - description: SIOU registers block
+
+ reg-names:
+ items:
+ - const: serdes
+ - const: siou
+
+ xlnx,tx-termination-fix:
+ description: |
+ Include this for fixing functional issue with the TX termination
+ resistance in GT, which can be out of spec for the XCZU9EG silicon
+ version.
+ type: boolean
+
+required:
+ - "#phy-cells"
+ - compatible
+ - reg
+ - reg-names
+
+if:
+ properties:
+ compatible:
+ const: xlnx,zynqmp-psgtr-v1.1
+
+then:
+ properties:
+ xlnx,tx-termination-fix: false
+
+additionalProperties: false
+
+examples:
+ - |
+ phy: phy@fd400000 {
+ compatible = "xlnx,zynqmp-psgtr-v1.1";
+ reg = <0x0 0xfd400000 0x0 0x40000>,
+ <0x0 0xfd3d0000 0x0 0x1000>;
+ reg-names = "serdes", "siou";
+ clocks = <&refclks 3>, <&refclks 2>, <&refclks 0>;
+ clock-names = "ref1", "ref2", "ref3";
+ #phy-cells = <4>;
+ };
+
+...
diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h
index 1f3f866fae7b..f6bc83b66ae9 100644
--- a/include/dt-bindings/phy/phy.h
+++ b/include/dt-bindings/phy/phy.h
@@ -17,5 +17,6 @@
#define PHY_TYPE_USB3 4
#define PHY_TYPE_UFS 5
#define PHY_TYPE_DP 6
+#define PHY_TYPE_SGMII 7
#endif /* _DT_BINDINGS_PHY */
--
Regards,
Laurent Pinchart
On 5/13/2020 10:52 PM, Laurent Pinchart wrote:
> From: Anurag Kumar Vulisha <[email protected]>
>
> Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed
> Processing System Gigabit Transceiver which provides PHY capabilities to
> USB, SATA, PCIE, Display Port and Ehernet SGMII controllers.
>
> Signed-off-by: Anurag Kumar Vulisha <[email protected]>
> Signed-off-by: Laurent Pinchart <[email protected]>
Need RobH Ack for this to be merged.
Thanks
Kishon
> ---
> Changes since v7:
>
> - Switch to GPL-2.0-only OR BSD-2-Clause
>
> Changes since v6:
>
> - Fixed specification of compatible-dependent xlnx,tx-termination-fix
> property
> - Dropped status property from example
> - Use 4 spaces to indent example
>
> Changes since v5:
>
> - Document clocks and clock-names properties
> - Document resets and reset-names properties
> - Replace subnodes with an additional entry in the PHY cells
> - Drop lane frequency PHY cell, replaced by reference clock phandle
> - Convert bindings to YAML
> - Reword the subject line
> - Drop Rob's R-b as the bindings have significantly changed
> - Drop resets and reset-names properties
> ---
> .../bindings/phy/xlnx,zynqmp-psgtr.yaml | 105 ++++++++++++++++++
> include/dt-bindings/phy/phy.h | 1 +
> 2 files changed, 106 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml b/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
> new file mode 100644
> index 000000000000..09e3cde7ebca
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
> @@ -0,0 +1,105 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx ZynqMP Gigabit Transceiver PHY Device Tree Bindings
> +
> +maintainers:
> + - Laurent Pinchart <[email protected]>
> +
> +description: |
> + This binding describes the Xilinx ZynqMP Gigabit Transceiver (GTR) PHY. The
> + GTR provides four lanes and is used by USB, SATA, PCIE, Display port and
> + Ethernet SGMII controllers.
> +
> +properties:
> + "#phy-cells":
> + const: 4
> + description: |
> + The cells contain the following arguments.
> +
> + - description: The GTR lane
> + minimum: 0
> + maximum: 3
> + - description: The PHY type
> + enum:
> + - PHY_TYPE_DP
> + - PHY_TYPE_PCIE
> + - PHY_TYPE_SATA
> + - PHY_TYPE_SGMII
> + - PHY_TYPE_USB
> + - description: The PHY instance
> + minimum: 0
> + maximum: 1 # for DP, SATA or USB
> + maximum: 3 # for PCIE or SGMII
> + - description: The reference clock number
> + minimum: 0
> + maximum: 3
> +
> + compatible:
> + enum:
> + - xlnx,zynqmp-psgtr-v1.1
> + - xlnx,zynqmp-psgtr
> +
> + clocks:
> + minItems: 1
> + maxItems: 4
> + description: |
> + Clock for each PS_MGTREFCLK[0-3] reference clock input. Unconnected
> + inputs shall not have an entry.
> +
> + clock-names:
> + minItems: 1
> + maxItems: 4
> + items:
> + pattern: "^ref[0-3]$"
> +
> + reg:
> + items:
> + - description: SERDES registers block
> + - description: SIOU registers block
> +
> + reg-names:
> + items:
> + - const: serdes
> + - const: siou
> +
> + xlnx,tx-termination-fix:
> + description: |
> + Include this for fixing functional issue with the TX termination
> + resistance in GT, which can be out of spec for the XCZU9EG silicon
> + version.
> + type: boolean
> +
> +required:
> + - "#phy-cells"
> + - compatible
> + - reg
> + - reg-names
> +
> +if:
> + properties:
> + compatible:
> + const: xlnx,zynqmp-psgtr-v1.1
> +
> +then:
> + properties:
> + xlnx,tx-termination-fix: false
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + phy: phy@fd400000 {
> + compatible = "xlnx,zynqmp-psgtr-v1.1";
> + reg = <0x0 0xfd400000 0x0 0x40000>,
> + <0x0 0xfd3d0000 0x0 0x1000>;
> + reg-names = "serdes", "siou";
> + clocks = <&refclks 3>, <&refclks 2>, <&refclks 0>;
> + clock-names = "ref1", "ref2", "ref3";
> + #phy-cells = <4>;
> + };
> +
> +...
> diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h
> index 1f3f866fae7b..f6bc83b66ae9 100644
> --- a/include/dt-bindings/phy/phy.h
> +++ b/include/dt-bindings/phy/phy.h
> @@ -17,5 +17,6 @@
> #define PHY_TYPE_USB3 4
> #define PHY_TYPE_UFS 5
> #define PHY_TYPE_DP 6
> +#define PHY_TYPE_SGMII 7
>
> #endif /* _DT_BINDINGS_PHY */
>
On Wed, 13 May 2020 20:22:37 +0300, Laurent Pinchart wrote:
> From: Anurag Kumar Vulisha <[email protected]>
>
> Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed
> Processing System Gigabit Transceiver which provides PHY capabilities to
> USB, SATA, PCIE, Display Port and Ehernet SGMII controllers.
>
> Signed-off-by: Anurag Kumar Vulisha <[email protected]>
> Signed-off-by: Laurent Pinchart <[email protected]>
> ---
> Changes since v7:
>
> - Switch to GPL-2.0-only OR BSD-2-Clause
>
> Changes since v6:
>
> - Fixed specification of compatible-dependent xlnx,tx-termination-fix
> property
> - Dropped status property from example
> - Use 4 spaces to indent example
>
> Changes since v5:
>
> - Document clocks and clock-names properties
> - Document resets and reset-names properties
> - Replace subnodes with an additional entry in the PHY cells
> - Drop lane frequency PHY cell, replaced by reference clock phandle
> - Convert bindings to YAML
> - Reword the subject line
> - Drop Rob's R-b as the bindings have significantly changed
> - Drop resets and reset-names properties
> ---
> .../bindings/phy/xlnx,zynqmp-psgtr.yaml | 105 ++++++++++++++++++
> include/dt-bindings/phy/phy.h | 1 +
> 2 files changed, 106 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
>
Reviewed-by: Rob Herring <[email protected]>
On Tue, May 26, 2020 at 12:32:01PM -0600, Rob Herring wrote:
> On Wed, 13 May 2020 20:22:37 +0300, Laurent Pinchart wrote:
> > From: Anurag Kumar Vulisha <[email protected]>
> >
> > Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed
> > Processing System Gigabit Transceiver which provides PHY capabilities to
> > USB, SATA, PCIE, Display Port and Ehernet SGMII controllers.
> >
> > Signed-off-by: Anurag Kumar Vulisha <[email protected]>
> > Signed-off-by: Laurent Pinchart <[email protected]>
> > ---
> > Changes since v7:
> >
> > - Switch to GPL-2.0-only OR BSD-2-Clause
> >
> > Changes since v6:
> >
> > - Fixed specification of compatible-dependent xlnx,tx-termination-fix
> > property
> > - Dropped status property from example
> > - Use 4 spaces to indent example
> >
> > Changes since v5:
> >
> > - Document clocks and clock-names properties
> > - Document resets and reset-names properties
> > - Replace subnodes with an additional entry in the PHY cells
> > - Drop lane frequency PHY cell, replaced by reference clock phandle
> > - Convert bindings to YAML
> > - Reword the subject line
> > - Drop Rob's R-b as the bindings have significantly changed
> > - Drop resets and reset-names properties
> > ---
> > .../bindings/phy/xlnx,zynqmp-psgtr.yaml | 105 ++++++++++++++++++
> > include/dt-bindings/phy/phy.h | 1 +
> > 2 files changed, 106 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
>
> Reviewed-by: Rob Herring <[email protected]>
Thank you Rob.
Kishon, now that the bindings have been acked, could you please take the
series in your tree (which I assume to tbe
https://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git/) ?
Is it too late for v5.8 ?
--
Regards,
Laurent Pinchart
Hi Kishon,
On Thu, May 28, 2020 at 04:55:38AM +0300, Laurent Pinchart wrote:
> On Tue, May 26, 2020 at 12:32:01PM -0600, Rob Herring wrote:
> > On Wed, 13 May 2020 20:22:37 +0300, Laurent Pinchart wrote:
> > > From: Anurag Kumar Vulisha <[email protected]>
> > >
> > > Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed
> > > Processing System Gigabit Transceiver which provides PHY capabilities to
> > > USB, SATA, PCIE, Display Port and Ehernet SGMII controllers.
> > >
> > > Signed-off-by: Anurag Kumar Vulisha <[email protected]>
> > > Signed-off-by: Laurent Pinchart <[email protected]>
> > > ---
> > > Changes since v7:
> > >
> > > - Switch to GPL-2.0-only OR BSD-2-Clause
> > >
> > > Changes since v6:
> > >
> > > - Fixed specification of compatible-dependent xlnx,tx-termination-fix
> > > property
> > > - Dropped status property from example
> > > - Use 4 spaces to indent example
> > >
> > > Changes since v5:
> > >
> > > - Document clocks and clock-names properties
> > > - Document resets and reset-names properties
> > > - Replace subnodes with an additional entry in the PHY cells
> > > - Drop lane frequency PHY cell, replaced by reference clock phandle
> > > - Convert bindings to YAML
> > > - Reword the subject line
> > > - Drop Rob's R-b as the bindings have significantly changed
> > > - Drop resets and reset-names properties
> > > ---
> > > .../bindings/phy/xlnx,zynqmp-psgtr.yaml | 105 ++++++++++++++++++
> > > include/dt-bindings/phy/phy.h | 1 +
> > > 2 files changed, 106 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
> >
> > Reviewed-by: Rob Herring <[email protected]>
>
> Thank you Rob.
>
> Kishon, now that the bindings have been acked, could you please take the
> series in your tree (which I assume to tbe
> https://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git/) ?
> Is it too late for v5.8 ?
Gentle ping.
--
Regards,
Laurent Pinchart