Add the CPU PMU to get perf support for hardware events.
Signed-off-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8994.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi
index 8af01ebe73f7..b3c01ebc5c67 100644
--- a/arch/arm64/boot/dts/qcom/msm8994.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi
@@ -154,6 +154,11 @@ memory {
reg = <0 0 0 0>;
};
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
--
2.27.0
On Tue 23 Jun 15:48 PDT 2020, Konrad Dybcio wrote:
> Add the CPU PMU to get perf support for hardware events.
>
> Signed-off-by: Konrad Dybcio <[email protected]>
Applied, thanks.
> ---
> arch/arm64/boot/dts/qcom/msm8994.dtsi | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi
> index 8af01ebe73f7..b3c01ebc5c67 100644
> --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi
> @@ -154,6 +154,11 @@ memory {
> reg = <0 0 0 0>;
> };
>
> + pmu {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> reserved-memory {
> #address-cells = <2>;
> #size-cells = <2>;
> --
> 2.27.0
>