changes since v2:
- fix commit messages (sorry!)
changes since v1:
- drop some superseeded patches
- reduce the amount of commits
- modernize the 8992 dts
- add libra and talkman DTSes
- do some housekeeping and fix minor issues
Tested on Libra and Talkman. Bullhead *shouldn't* break.
Depends on my 8994 patchset [1] (because of compatibles
and 8992-related SMD RPM patches) and my RPMCC patch [2].
[1] https://patchwork.kernel.org/project/linux-arm-msm/list/?series=307939
[2] https://patchwork.kernel.org/patch/11622057/
Konrad Dybcio (13):
arm64: dts: qcom: msm8992: Modernize the DTS style
arm64: dts: qcom: msm8992: Fix SDHCI1
arm64: dts: qcom: bullhead: Add qcom,msm-id
arm64: dts: qcom: bullhead: Move UART pinctrl to SoC
arm64: dts: qcom: msm8992: Add a proper CPU map
arm64: dts: qcom: msm8992: Add a SCM node
arm64: dts: qcom: msm8992: Add SPMI PMIC arbiter device
arm64: dts: qcom: msm8992: Add BLSP2_UART2 and I2C nodes
arm64: dts: qcom: msm8992: Add PMU node
arm64: dts: qcom: msm8992: Add PSCI support.
arm64: dts: qcom: msm8992: Add RPMCC node
arm64: dts: qcom: Add Xiaomi Libra (Mi 4C) device tree
arm64: dts: qcom: Add Microsoft Lumia 950 (Talkman) device tree
arch/arm64/boot/dts/qcom/Makefile | 2 +
.../dts/qcom/msm8992-bullhead-rev-101.dts | 20 +-
.../dts/qcom/msm8992-msft-lumia-talkman.dts | 39 ++
arch/arm64/boot/dts/qcom/msm8992-pins.dtsi | 90 ---
.../boot/dts/qcom/msm8992-xiaomi-libra.dts | 364 ++++++++++++
arch/arm64/boot/dts/qcom/msm8992.dtsi | 522 +++++++++++++++---
6 files changed, 852 insertions(+), 185 deletions(-)
create mode 100644 arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts
delete mode 100644 arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts
--
2.27.0
Following changes have been made:
- remove name, compatible and msm-id
- wrap clocks in clocks{}
- order nodes by name and by address
- clock_gcc -> gcc
- msmgpio -> tlmm
- retire msm8992-pins.dtsi
- add some of the missing pins
- make comments C-style
- make apcs a mailbox
Signed-off-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8992-pins.dtsi | 90 --------
arch/arm64/boot/dts/qcom/msm8992.dtsi | 246 ++++++++++++++-------
2 files changed, 168 insertions(+), 168 deletions(-)
delete mode 100644 arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
diff --git a/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
deleted file mode 100644
index c543c718c22d..000000000000
--- a/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
+++ /dev/null
@@ -1,90 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
- */
-
-&msmgpio {
- blsp1_uart2_default: blsp1_uart2_default {
- pinmux {
- function = "blsp_uart2";
- pins = "gpio4", "gpio5";
- };
- pinconf {
- pins = "gpio4", "gpio5";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- blsp1_uart2_sleep: blsp1_uart2_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio4", "gpio5";
- };
- pinconf {
- pins = "gpio4", "gpio5";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- /* 0-3 for sdc1 4-6 for sdc2 */
- /* Order of pins */
- /* SDC1: CLK -> 0, CMD -> 1, DATA -> 2, RCLK -> 3 */
- /* SDC2: CLK -> 4, CMD -> 5, DATA -> 6 */
- sdc1_clk_on: clk-on {
- pinconf {
- pins = "sdc1_clk";
- bias-disable = <0>; /* No pull */
- drive-strength = <16>; /* 16mA */
- };
- };
-
- sdc1_clk_off: clk-off {
- pinconf {
- pins = "sdc1_clk";
- bias-disable = <0>; /* No pull */
- drive-strength = <2>; /* 2mA */
- };
- };
-
- sdc1_cmd_on: cmd-on {
- pinconf {
- pins = "sdc1_cmd";
- bias-pull-up;
- drive-strength = <8>;
- };
- };
-
- sdc1_cmd_off: cmd-off {
- pinconf {
- pins = "sdc1_cmd";
- bias-pull-up = <0x3>; /* same as 3.10 ?? */
- drive-strength = <2>; /* 2mA */
- };
- };
-
- sdc1_data_on: data-on {
- pinconf {
- pins = "sdc1_data";
- bias-pull-up;
- drive-strength = <8>; /* 8mA */
- };
- };
-
- sdc1_data_off: data-off {
- pinconf {
- pins = "sdc1_data";
- bias-pull-up;
- drive-strength = <2>;
- };
- };
-
- sdc1_rclk_on: rclk-on {
- bias-pull-down; /* pull down */
- };
-
- sdc1_rclk_off: rclk-off {
- bias-pull-down; /* pull down */
- };
-};
diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi
index d41ba1ef687a..43b2e4cd26f0 100644
--- a/arch/arm64/boot/dts/qcom/msm8992.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi
@@ -6,10 +6,6 @@
#include <dt-bindings/clock/qcom,gcc-msm8994.h>
/ {
- model = "Qualcomm Technologies, Inc. MSM 8992";
- compatible = "qcom,msm8992";
- // msm-id needed by bootloader for selecting correct blob
- qcom,msm-id = <251 0>, <252 0>;
interrupt-parent = <&intc>;
#address-cells = <2>;
@@ -40,35 +36,35 @@ L2_0: l2-cache {
};
};
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- };
+ clocks {
+ xo_board: xo_board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ };
- xo_board: xo_board {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <19200000>;
+ sleep_clk: sleep_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
};
- sleep_clk: sleep_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
+ memory {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0 0 0 0>;
};
- vreg_vph_pwr: vreg-vph-pwr {
- compatible = "regulator-fixed";
- status = "okay";
- regulator-name = "vph-pwr";
-
- regulator-min-microvolt = <3600000>;
- regulator-max-microvolt = <3600000>;
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
- regulator-always-on;
+ smem_region: smem@6a00000 {
+ reg = <0x0 0x6a00000 0x0 0x200000>;
+ no-map;
+ };
};
sfpb_mutex: hwmutex {
@@ -98,9 +94,10 @@ intc: interrupt-controller@f9000000 {
<0xf9002000 0x1000>;
};
- apcs: syscon@f900d000 {
- compatible = "syscon";
+ apcs: mailbox@f900d000 {
+ compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
reg = <0xf900d000 0x2000>;
+ #mbox-cells = <1>;
};
timer@f9020000 {
@@ -161,40 +158,6 @@ frame@f9028000 {
};
};
- restart@fc4ab000 {
- compatible = "qcom,pshold";
- reg = <0xfc4ab000 0x4>;
- };
-
- msmgpio: pinctrl@fd510000 {
- compatible = "qcom,msm8994-pinctrl";
- reg = <0xfd510000 0x4000>;
- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- gpio-ranges = <&msmgpio 0 0 146>;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- blsp1_uart2: serial@f991e000 {
- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
- reg = <0xf991e000 0x1000>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>;
- status = "disabled";
- clock-names = "core", "iface";
- clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
- <&clock_gcc GCC_BLSP1_AHB_CLK>;
- };
-
- clock_gcc: clock-controller@fc400000 {
- compatible = "qcom,gcc-msm8994";
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- reg = <0xfc400000 0x2000>;
- };
-
sdhci1: mmc@f9824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
@@ -204,8 +167,8 @@ sdhci1: mmc@f9824900 {
<GIC_SPI 138 IRQ_TYPE_NONE>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&clock_gcc GCC_SDCC1_APPS_CLK>,
- <&clock_gcc GCC_SDCC1_AHB_CLK>;
+ clocks = <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
@@ -220,32 +183,141 @@ sdhci1: mmc@f9824900 {
status = "okay";
};
+ blsp1_uart2: serial@f991e000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0xf991e000 0x1000>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>;
+ clock-names = "core", "iface";
+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_uart2_default>;
+ pinctrl-1 = <&blsp1_uart2_sleep>;
+ status = "disabled";
+ };
+
+ gcc: clock-controller@fc400000 {
+ compatible = "qcom,gcc-msm8994";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ reg = <0xfc400000 0x2000>;
+ };
+
rpm_msg_ram: memory@fc428000 {
compatible = "qcom,rpm-msg-ram";
reg = <0xfc428000 0x4000>;
};
+ restart@fc4ab000 {
+ compatible = "qcom,pshold";
+ reg = <0xfc4ab000 0x4>;
+ };
+
sfpb_mutex_regs: syscon@fd484000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "syscon";
reg = <0xfd484000 0x400>;
};
- };
- memory {
- device_type = "memory";
- reg = <0 0 0 0>; // bootloader will update
- };
+ tlmm: pinctrl@fd510000 {
+ compatible = "qcom,msm8994-pinctrl";
+ reg = <0xfd510000 0x4000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ gpio-ranges = <&tlmm 0 0 146>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ blsp1_uart2_default: blsp1-uart2-default {
+ function = "blsp_uart2";
+ pins = "gpio4", "gpio5";
+ drive-strength = <16>;
+ bias-disable;
+ };
- smem_region: smem@6a00000 {
- reg = <0x0 0x6a00000 0x0 0x200000>;
- no-map;
+ blsp1_uart2_sleep: blsp1-uart2-sleep {
+ function = "gpio";
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ sdc1_clk_on: clk-on {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <6>;
+ };
+
+ sdc1_clk_off: clk-off {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ sdc1_cmd_on: cmd-on {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <6>;
+ };
+
+ sdc1_cmd_off: cmd-off {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ sdc1_data_on: data-on {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <6>;
+ };
+
+ sdc1_data_off: data-off {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ sdc1_rclk_on: rclk-on {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+
+ sdc1_rclk_off: rclk-off {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+
+ i2c2_default: i2c2-default {
+ function = "blsp_i2c2";
+ pins = "gpio6", "gpio7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c2_sleep: i2c2-sleep {
+ function = "gpio";
+ pins = "gpio6", "gpio7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c6_default: i2c6-default {
+ function = "blsp_i2c6";
+ pins = "gpio28", "gpio27";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c6_sleep: i2c6-sleep {
+ function = "gpio";
+ pins = "gpio28", "gpio27";
+ drive-strength = <2>;
+ bias-disable;
+ };
};
};
@@ -264,6 +336,24 @@ rpm_requests: rpm-requests {
};
};
};
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ vreg_vph_pwr: vreg-vph-pwr {
+ compatible = "regulator-fixed";
+ status = "okay";
+ regulator-name = "vph-pwr";
+
+ regulator-min-microvolt = <3600000>;
+ regulator-max-microvolt = <3600000>;
+
+ regulator-always-on;
+ };
};
-#include "msm8992-pins.dtsi"
--
2.27.0
This pinout is common for every 8992-based device and
should therefore reside in the SoC device tree.
Also convert addresses into phandles.
Signed-off-by: Konrad Dybcio <[email protected]>
---
.../boot/dts/qcom/msm8992-bullhead-rev-101.dts | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts
index 4f70681e730d..5969b5cfdc85 100644
--- a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts
+++ b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts
@@ -23,15 +23,6 @@ chosen {
stdout-path = "serial0:115200n8";
};
- soc {
- serial@f991e000 {
- status = "okay";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp1_uart2_default>;
- pinctrl-1 = <&blsp1_uart2_sleep>;
- };
- };
-
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -48,6 +39,10 @@ ramoops@1ff00000 {
};
};
+&blsp1_uart2 {
+ status = "okay";
+};
+
&rpm_requests {
pm8994-regulators {
compatible = "qcom,rpm-pm8994-regulators";
--
2.27.0
Add the property required for the bootloader to select
the correct device tree blob. It has been removed from
the SoC device tree as it should be set on a per-device
basis.
Signed-off-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts
index 1061fd5404aa..4f70681e730d 100644
--- a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts
+++ b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts
@@ -11,6 +11,7 @@ / {
model = "LG Nexus 5X";
compatible = "lg,bullhead", "qcom,msm8992";
/* required for bootloader to select correct board */
+ qcom,msm-id = <251 0>, <252 0>;
qcom,board-id = <0xb64 0>;
qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
--
2.27.0
Signed-off-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8992.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi
index f780cd39ded6..aee33ed61858 100644
--- a/arch/arm64/boot/dts/qcom/msm8992.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi
@@ -118,6 +118,12 @@ sleep_clk: sleep_clk {
};
};
+ firmware {
+ scm {
+ compatible = "qcom,scm-msm8994", "qcom,scm";
+ };
+ };
+
memory {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
--
2.27.0
Add device tree support for the Microsoft Lumia 950 smartphone.
It is based on msm8992 and supports booting Linux via a custom
EDK2 port.
Currently it supports:
* Screen console via EFIFB
* Booting via EFI_STUB
* SDHCI
* I2C
* PSCI core bringup
Please note that there is an implementation of EL2 startup
on this board, but it requires the user to resign from
PSCI and use spin-table instead. This revision sticks with
PSCI.
Signed-off-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../dts/qcom/msm8992-msft-lumia-talkman.dts | 39 +++++++++++++++++++
2 files changed, 40 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 344cdeb68b16..77256eef9520 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
+dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-talkman.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8992-xiaomi-libra.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
diff --git a/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts b/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts
new file mode 100644
index 000000000000..3cc01f02219d
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2020, Konrad Dybcio
+ */
+
+/dts-v1/;
+
+#include "msm8992.dtsi"
+#include "pm8994.dtsi"
+#include "pmi8994.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/gpio-keys.h>
+
+/ {
+ model = "Microsoft Lumia 950";
+ compatible = "microsoft,talkman", "qcom,msm8992";
+
+ /* Most Lumia 950 users use GRUB to load their kernels,
+ * hence there is no need for msm-id and friends.
+ */
+
+ /* This enables graphical output via bootloader-enabled display.
+ * acpi=no is required due to WP platforms having ACPI support, but
+ * only for Windows-based OSes.
+ */
+ chosen {
+ bootargs = "earlycon=efifb console=efifb acpi=no";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ };
+};
+
+&sdhc_1 {
+ status = "okay";
+
+ mmc-hs200-1_8v;
+};
--
2.27.0
Add support for I2C to enable support for peripherals
such as touchscreens or sensors. Also add BLSP_UART2 interface.
Please note that the naming scheme follows downstream and as
abominable as it is, that's what we get.
Signed-off-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8992.dtsi | 153 ++++++++++++++++++++++++++
1 file changed, 153 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi
index acce7be22e50..e8b801813f14 100644
--- a/arch/arm64/boot/dts/qcom/msm8992.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi
@@ -272,6 +272,101 @@ blsp1_uart2: serial@f991e000 {
status = "disabled";
};
+ blsp_i2c2: i2c@f9924000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0xf9924000 0x500>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c2_default>;
+ pinctrl-1 = <&i2c2_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ /* Somebody was very creative with their numbering scheme downstream... */
+
+ blsp_i2c13: i2c@f9927000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0xf9927000 0x500>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c13_default>;
+ pinctrl-1 = <&i2c13_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp_i2c6: i2c@f9928000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0xf9928000 0x500>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c6_default>;
+ pinctrl-1 = <&i2c6_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp2_uart2: serial@f995e000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0xf995e000 0x1000>;
+ interrupt = <GIC_SPI 146 IRQ_TYPE_LEVEL_LOW>;
+ clock-names = "core", "iface";
+ clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp2_uart2_default>;
+ pinctrl-1 = <&blsp2_uart2_sleep>;
+ status = "disabled";
+ };
+
+ blsp_i2c7: i2c@f9963000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0xf9963000 0x500>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>,
+ <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c7_default>;
+ pinctrl-1 = <&i2c7_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp_i2c5: i2c@f9967000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0xf9967000 0x500>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>,
+ <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c5_default>;
+ pinctrl-1 = <&i2c5_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
gcc: clock-controller@fc400000 {
compatible = "qcom,gcc-msm8994";
#clock-cells = <1>;
@@ -337,6 +432,20 @@ blsp1_uart2_sleep: blsp1-uart2-sleep {
bias-pull-down;
};
+ blsp2_uart2_default: blsp2-uart2-default {
+ function = "blsp_uart8";
+ pins = "gpio45", "gpio46", "gpio47", "gpio48";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp2_uart2_sleep: blsp2-uart2-sleep {
+ function = "gpio";
+ pins = "gpio45", "gpio46", "gpio47", "gpio48";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
sdc1_clk_on: clk-on {
pins = "sdc1_clk";
bias-disable;
@@ -397,6 +506,21 @@ i2c2_sleep: i2c2-sleep {
bias-disable;
};
+ i2c5_default: i2c5-default {
+ /* Don't be fooled! Nobody knows the reason why though... */
+ function = "blsp_i2c11";
+ pins = "gpio83", "gpio84";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c5_sleep: i2c5-sleep {
+ function = "gpio";
+ pins = "gpio83", "gpio84";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
i2c6_default: i2c6-default {
function = "blsp_i2c6";
pins = "gpio28", "gpio27";
@@ -410,6 +534,35 @@ i2c6_sleep: i2c6-sleep {
drive-strength = <2>;
bias-disable;
};
+
+ i2c7_default: i2c7-default {
+ function = "blsp_i2c7";
+ pins = "gpio43", "gpio44";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c7_sleep: i2c7-sleep {
+ function = "gpio";
+ pins = "gpio43", "gpio44";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c13_default: i2c13-default {
+ /* Not a typo either. */
+ function = "blsp_i2c5";
+ pins = "gpio23", "gpio24";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c13_sleep: i2c13-sleep {
+ function = "gpio";
+ pins = "gpio23", "gpio24";
+ drive-strength = <2>;
+ bias-disable;
+ };
};
};
--
2.27.0
This SoC's firmware does not fully support the PSCI
spec, but it's good enough to bring the cores up.
Signed-off-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8992.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi
index c4c9a108ae1e..bc3acc0cf9bf 100644
--- a/arch/arm64/boot/dts/qcom/msm8992.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi
@@ -135,6 +135,11 @@ pmu {
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
};
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "hvc";
+ };
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
--
2.27.0
This commit adds support for the Xiaomi Libra (Mi 4C)
smartphone. It's based on the Qualcomm msm8992 SoC.
It currently supports:
* Screen console from bootloader
* SDHCI
* Regulator configuration
* Serial console
* I2C
Signed-off-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/msm8992-xiaomi-libra.dts | 364 ++++++++++++++++++
2 files changed, 365 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 0f2c33d611df..344cdeb68b16 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
+dtb-$(CONFIG_ARCH_QCOM) += msm8992-xiaomi-libra.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb
diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts
new file mode 100644
index 000000000000..ac9b2f325fc1
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts
@@ -0,0 +1,364 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2020, Konrad Dybcio
+ */
+
+/dts-v1/;
+
+#include "msm8992.dtsi"
+#include "pm8994.dtsi"
+#include "pmi8994.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/gpio-keys.h>
+
+/ {
+ model = "Xiaomi Mi 4C";
+ compatible = "xiaomi,libra", "qcom,msm8992";
+ /* required for bootloader to select correct board */
+ qcom,msm-id = <251 0 252 0>;
+ qcom,pmic-id = <65545 65546 0 0>;
+ qcom,board-id = <12 0>;
+
+ /* This enables graphical output via bootloader-enabled display */
+ chosen {
+ bootargs = "earlycon=tty0 console=tty0";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer0: framebuffer@3404000 {
+ status= "okay";
+ compatible = "simple-framebuffer";
+ reg = <0 0x3404000 0 (1080 * 1920 * 3)>;
+ width = <1080>;
+ height = <1920>;
+ stride = <(1080 * 3)>;
+ format = "r8g8b8";
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ input-name = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+
+ button@0 {
+ label = "Volume Up";
+ gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ wakeup-source;
+ debounce-interval = <15>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* This is for getting crash logs using Android downstream kernels */
+ ramoops@dfc00000 {
+ compatible = "ramoops";
+ reg = <0x0 0xdfc00000 0x0 0x40000>;
+ console-size = <0x10000>;
+ record-size = <0x10000>;
+ ftrace-size = <0x10000>;
+ pmsg-size = <0x20000>;
+ };
+
+ continuous_splash: framebuffer@3401000{
+ reg = <0x0 0x3401000 0x0 0x2200000>;
+ no-map;
+ };
+
+ dfps_data_mem: dfps_data_mem@3400000 {
+ reg = <0x0 0x3400000 0x0 0x1000>;
+ no-map;
+ };
+
+ peripheral_region: peripheral_region@7400000 {
+ reg = <0x0 0x7400000 0x0 0x1c00000>;
+ no-map;
+ };
+
+ modem_region: modem_region@9000000 {
+ reg = <0x0 0x9000000 0x0 0x5a00000>;
+ no-map;
+ };
+
+ tzapp: modem_region@ea00000 {
+ reg = <0x0 0xea00000 0x0 0x1900000>;
+ no-map;
+ };
+ };
+};
+
+&blsp_i2c2 {
+ status = "okay";
+
+ /* Atmel or Synaptics touchscreen */
+};
+
+&blsp_i2c5 {
+ status = "okay";
+
+ /* Silabs si4705 FM transmitter */
+};
+
+&blsp_i2c6 {
+ status = "okay";
+
+ /* NCI NFC,
+ * TI USB320 Type-C controller,
+ * Pericom 30216a USB (de)mux switch
+ */
+};
+
+&blsp_i2c7 {
+ status = "okay";
+
+ /* cm36686 proximity and ambient light sensor */
+};
+
+&blsp_i2c13 {
+ status = "okay";
+
+ /* ST lsm6db0 gyro/accelerometer */
+};
+
+&blsp2_uart2 {
+ status = "okay";
+};
+
+&rpm_requests {
+ pm8994-regulators {
+ compatible = "qcom,rpm-pm8994-regulators";
+
+ vdd_l1-supply = <&pm8994_s7>;
+ vdd_l2_26_28-supply = <&pm8994_s3>;
+ vdd_l3_11-supply = <&pm8994_s3>;
+ vdd_l4_27_31-supply = <&pm8994_s3>;
+ vdd_l5_7-supply = <&pm8994_s3>;
+ vdd_l6_12_32-supply = <&pm8994_s5>;
+ vdd_l8_16_30-supply = <&vreg_vph_pwr>;
+ vdd_l9_10_18_22-supply = <&vreg_vph_pwr>;
+ vdd_l13_19_23_24-supply = <&vreg_vph_pwr>;
+ vdd_l14_15-supply = <&pm8994_s5>;
+ vdd_l17_29-supply = <&vreg_vph_pwr>;
+ vdd_l20_21-supply = <&vreg_vph_pwr>;
+ vdd_l25-supply = <&pm8994_s5>;
+ vdd_lvs1_2 = <&pm8994_s4>;
+
+ pm8994_s1: s1 {
+ /* unused */
+ status = "disabled";
+ };
+
+ pm8994_s2: s2 {
+ /* unused */
+ status = "disabled";
+ };
+
+ pm8994_s3: s3 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pm8994_s4: s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-allow-set-load;
+ regulator-always-on;
+ regulator-system-load = <325000>;
+ };
+
+ pm8994_s5: s5 {
+ regulator-min-microvolt = <2150000>;
+ regulator-max-microvolt = <2150000>;
+ };
+
+ pm8994_s7: s7 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ pm8994_l1: l1 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ pm8994_l2: l2 {
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ };
+
+ pm8994_l3: l3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8994_l4: l4 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8994_l5: l5 {
+ /* unused */
+ status = "disabled";
+ };
+
+ pm8994_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8994_l7: l7 {
+ /* unused */
+ status = "disabled";
+ };
+
+ pm8994_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8994_l9: l9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8994_l10: l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8994_l11: l11 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8994_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8994_l13: l13 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8994_l14: l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8994_l15: l15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8994_l16: l16 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+
+ pm8994_l17: l17 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+
+ pm8994_l18: l18 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ pm8994_l19: l19 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ pm8994_l20: l20 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-allow-set-load;
+ regulator-system-load = <570000>;
+ };
+
+ pm8994_l21: l21 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-always-on;
+ };
+
+ pm8994_l22: l22 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pm8994_l23: l23 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ pm8994_l24: l24 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3150000>;
+ };
+
+ pm8994_l25: l25 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ pm8994_l26: l26 {
+ regulator-min-microvolt = <987500>;
+ regulator-max-microvolt = <987500>;
+
+ };
+
+ pm8994_l27: l27 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pm8994_l28: l28 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ pm8994_l29: l29 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ pm8994_l30: l30 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8994_l31: l31 {
+ regulator-min-microvolt = <1262500>;
+ regulator-max-microvolt = <1262500>;
+ };
+
+ pm8994_l32: l32 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ };
+};
+
+&sdhc_1 {
+ status = "okay";
+
+ mmc-hs400-1_8v;
+ vmmc-supply = <&pm8994_l20>;
+ vqmmc-supply = <&pm8994_s4>;
+};
--
2.27.0
This commit adds cpu nodes for all 6 cores
present on this SoC and the cpu-map.
Signed-off-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8992.dtsi | 82 ++++++++++++++++++++++++---
1 file changed, 75 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi
index 8ef1cb8ba8ef..f780cd39ded6 100644
--- a/arch/arm64/boot/dts/qcom/msm8992.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi
@@ -16,24 +16,92 @@ / {
cpus {
#address-cells = <2>;
#size-cells = <0>;
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&CPU0>;
- };
- };
- };
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
+ enable-method = "psci";
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x1>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x2>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CPU3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x3>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CPU4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x100>;
+ next-level-cache = <&L2_1>;
+ enable-method = "psci";
+ L2_1: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ CPU5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x101>;
+ next-level-cache = <&L2_1>;
+ enable-method = "psci";
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&CPU4>;
+ };
+
+ core1 {
+ cpu = <&CPU5>;
+ };
+ };
+ };
};
clocks {
--
2.27.0
Add the PMU so we can get proper perf event support on this SoC.
Signed-off-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8992.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi
index e8b801813f14..c4c9a108ae1e 100644
--- a/arch/arm64/boot/dts/qcom/msm8992.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi
@@ -130,6 +130,11 @@ memory {
reg = <0 0 0 0>;
};
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
--
2.27.0
This lets us use clocks provided by RPM.
Signed-off-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8992.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi
index bc3acc0cf9bf..188fff2095f1 100644
--- a/arch/arm64/boot/dts/qcom/msm8992.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi
@@ -588,6 +588,11 @@ rpm {
rpm_requests: rpm-requests {
compatible = "qcom,rpm-msm8994";
qcom,smd-channels = "rpm_requests";
+
+ rpmcc: rpmcc {
+ compatible = "qcom,rpmcc-msm8992";
+ #clock-cells = <1>;
+ };
};
};
};
--
2.27.0
Add SPMI PMIC arbiter device to communicate with PMICs
attached to SPMI bus.
Signed-off-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8992.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi
index aee33ed61858..acce7be22e50 100644
--- a/arch/arm64/boot/dts/qcom/msm8992.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi
@@ -290,6 +290,22 @@ restart@fc4ab000 {
reg = <0xfc4ab000 0x4>;
};
+ spmi_bus: spmi@fc4c0000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0xfc4cf000 0x1000>,
+ <0xfc4cb000 0x1000>,
+ <0xfc4ca000 0x1000>;
+ reg-names = "core", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
+
sfpb_mutex_regs: syscon@fd484000 {
#address-cells = <1>;
#size-cells = <1>;
--
2.27.0
This commit ensures the correct IRQ type is set
and disables the device by default.
The mmc-hs400-1_8v property is also moved to
Bullhead as it might not be present on all boards.
The node has been renamed to sdhci@ instead of mmc@
and the phandle was changed to sdhc_1 to comply with
the newer DTS style.
Signed-off-by: Konrad Dybcio <[email protected]>
---
.../boot/dts/qcom/msm8992-bullhead-rev-101.dts | 6 ++++++
arch/arm64/boot/dts/qcom/msm8992.dtsi | 16 +++++++++-------
2 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts
index a2de69292d28..1061fd5404aa 100644
--- a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts
+++ b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts
@@ -271,3 +271,9 @@ pm8994_l32: l32 {
};
};
};
+
+&sdhc_1 {
+ status = "okay";
+
+ mmc-hs400-1_8v;
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi
index 43b2e4cd26f0..8ef1cb8ba8ef 100644
--- a/arch/arm64/boot/dts/qcom/msm8992.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi
@@ -158,18 +158,19 @@ frame@f9028000 {
};
};
- sdhci1: mmc@f9824900 {
+ sdhc_1: sdhci@f9824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
reg-names = "hc_mem", "core_mem";
- interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>,
- <GIC_SPI 138 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
- <&gcc GCC_SDCC1_AHB_CLK>;
- clock-names = "core", "iface";
+ <&gcc GCC_SDCC1_AHB_CLK>,
+ <&xo_board>;
+ clock-names = "core", "iface", "xo";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
@@ -179,8 +180,9 @@ sdhci1: mmc@f9824900 {
regulator-always-on;
bus-width = <8>;
- mmc-hs400-1_8v;
- status = "okay";
+ non-removable;
+
+ status = "disabled";
};
blsp1_uart2: serial@f991e000 {
--
2.27.0
Bumping this up, in case it just got overlooked.
Konrad
On Mon 27 Jul 11:20 PDT 2020, Konrad Dybcio wrote:
> Bumping this up, in case it just got overlooked.
>
It was just overlooked, thanks for the bump!
I think it looks good, will pick up the patches, and the previous series
that it depends on.
Thanks,
Bjorn