On 29-06-20, 15:00, Laurent Pinchart wrote:
> Hello,
>
> The patch series adds a PHY driver for the Xilinx ZynqMP gigabit serial
> transceivers (PS-GTR). The PS-GTR is a set of 4 PHYs that can be used by
> the PCIe, USB 3.0, DisplayPort, SATA and Ethernet controllers that are
> part of the Serial I/O Unit (SIOU).
>
> The code is based on a previous version sent by Anurag Kumar Vulisha and
> available at [1]. The DT bindings have been converted to YAML, and both
> the bindings and the driver have been considerably reworked (and
> simplified). The most notable changes is the removal of manual handling
> of the reset lines of the PHY users (which belongs to the PHY users
> themselves), and moving to the standard PHY .power_on() and .configure()
> operations to replace functions that were previously exported by the
> driver. Please see individual patches for a more detailed changelog.
>
> Compared to v8, the series has been rebased on phy/next, and a minor
> issue in MAINTAINERS has been fixed.
Thanks for quick rebase, Applied 1 & 2 now
>
> [1] https://patchwork.kernel.org/cover/10735681/
>
> Anurag Kumar Vulisha (2):
> dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY
> phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver
>
> Laurent Pinchart (1):
> arm64: dts: zynqmp: Add GTR transceivers
>
> .../bindings/phy/xlnx,zynqmp-psgtr.yaml | 105 ++
> MAINTAINERS | 9 +
> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 10 +
> drivers/phy/Kconfig | 1 +
> drivers/phy/Makefile | 3 +-
> drivers/phy/xilinx/Kconfig | 13 +
> drivers/phy/xilinx/Makefile | 3 +
> drivers/phy/xilinx/phy-zynqmp.c | 995 ++++++++++++++++++
> include/dt-bindings/phy/phy.h | 1 +
> 9 files changed, 1139 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
> create mode 100644 drivers/phy/xilinx/Kconfig
> create mode 100644 drivers/phy/xilinx/Makefile
> create mode 100644 drivers/phy/xilinx/phy-zynqmp.c
>
> --
> Regards,
>
> Laurent Pinchart
--
~Vinod
Hi Vinod,
On Mon, Jun 29, 2020 at 06:49:17PM +0530, Vinod Koul wrote:
> On 29-06-20, 15:00, Laurent Pinchart wrote:
> > Hello,
> >
> > The patch series adds a PHY driver for the Xilinx ZynqMP gigabit serial
> > transceivers (PS-GTR). The PS-GTR is a set of 4 PHYs that can be used by
> > the PCIe, USB 3.0, DisplayPort, SATA and Ethernet controllers that are
> > part of the Serial I/O Unit (SIOU).
> >
> > The code is based on a previous version sent by Anurag Kumar Vulisha and
> > available at [1]. The DT bindings have been converted to YAML, and both
> > the bindings and the driver have been considerably reworked (and
> > simplified). The most notable changes is the removal of manual handling
> > of the reset lines of the PHY users (which belongs to the PHY users
> > themselves), and moving to the standard PHY .power_on() and .configure()
> > operations to replace functions that were previously exported by the
> > driver. Please see individual patches for a more detailed changelog.
> >
> > Compared to v8, the series has been rebased on phy/next, and a minor
> > issue in MAINTAINERS has been fixed.
>
> Thanks for quick rebase, Applied 1 & 2 now
Thank you. Michal, could you apply 3/3 to your tree ?
> > [1] https://patchwork.kernel.org/cover/10735681/
> >
> > Anurag Kumar Vulisha (2):
> > dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY
> > phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver
> >
> > Laurent Pinchart (1):
> > arm64: dts: zynqmp: Add GTR transceivers
> >
> > .../bindings/phy/xlnx,zynqmp-psgtr.yaml | 105 ++
> > MAINTAINERS | 9 +
> > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 10 +
> > drivers/phy/Kconfig | 1 +
> > drivers/phy/Makefile | 3 +-
> > drivers/phy/xilinx/Kconfig | 13 +
> > drivers/phy/xilinx/Makefile | 3 +
> > drivers/phy/xilinx/phy-zynqmp.c | 995 ++++++++++++++++++
> > include/dt-bindings/phy/phy.h | 1 +
> > 9 files changed, 1139 insertions(+), 1 deletion(-)
> > create mode 100644 Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
> > create mode 100644 drivers/phy/xilinx/Kconfig
> > create mode 100644 drivers/phy/xilinx/Makefile
> > create mode 100644 drivers/phy/xilinx/phy-zynqmp.c
--
Regards,
Laurent Pinchart
On 29. 06. 20 15:49, Laurent Pinchart wrote:
> Hi Vinod,
>
> On Mon, Jun 29, 2020 at 06:49:17PM +0530, Vinod Koul wrote:
>> On 29-06-20, 15:00, Laurent Pinchart wrote:
>>> Hello,
>>>
>>> The patch series adds a PHY driver for the Xilinx ZynqMP gigabit serial
>>> transceivers (PS-GTR). The PS-GTR is a set of 4 PHYs that can be used by
>>> the PCIe, USB 3.0, DisplayPort, SATA and Ethernet controllers that are
>>> part of the Serial I/O Unit (SIOU).
>>>
>>> The code is based on a previous version sent by Anurag Kumar Vulisha and
>>> available at [1]. The DT bindings have been converted to YAML, and both
>>> the bindings and the driver have been considerably reworked (and
>>> simplified). The most notable changes is the removal of manual handling
>>> of the reset lines of the PHY users (which belongs to the PHY users
>>> themselves), and moving to the standard PHY .power_on() and .configure()
>>> operations to replace functions that were previously exported by the
>>> driver. Please see individual patches for a more detailed changelog.
>>>
>>> Compared to v8, the series has been rebased on phy/next, and a minor
>>> issue in MAINTAINERS has been fixed.
>>
>> Thanks for quick rebase, Applied 1 & 2 now
>
> Thank you. Michal, could you apply 3/3 to your tree ?
Will take care about this one.
Thanks,
Michal