This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8 supported. Data register used to support the read/write
operation from/to device.
NAND controller also supports in-built HW ECC engine.
NAND controller driver implements ->exec_op() to replace legacy hooks,
these specific call-back method to execute NAND operations.
Thanks Miquel, Boris, Andy, Arnd and Rob for the review comments and suggestions.
---
v14:
- Address Andy's review comments
- align the headers and revome Duplicates
- replcace numerical const values by HZ_PER_MHZ and USEC_PER_SEC
defined macros
- add dev_err_probe() api instead of legacy err check
- add get_unaligned_le32() api instead of manual endiness
- remove redudent check
- split the lines logically in between and add require spaces
v13:
- Address Miquel Raynal review comments
- update the return type with variable 'ret'
- handle err check statement properly
- change the naming convention aligned with recently changed the naming
around the data interface
data structure and function names
- replace by div 8 instead of <<4 in ecc calculation better code readability
- handle check_only properly like existing drivers
v12-resend:
- No Change
v12:
- address Miquel Raynal review comments update
- add/modify the comments for better understanding
- handle the check_only variable
- update the ecc function based on the existing drivers
- add newline
- verify that mtd->name is set after nand_set_flash_node()
- add the check WARN_ON(ret);
v11-resend:
- Rebase to v5.8-rc1
v11:
- No Change
v10:
- No Change
v9:
- No change
v8:
- fix the kbuild bot warnings
- correct the typo's
v7:
- indentation issue is fixed
- add error check for retrieve the resource from dt
v6:
- update EBU_ADDR_SELx register base value build it from DT
- Add tabs in in Kconfig
v5:
- replace by 'HSNAND_CLE_OFFS | HSNAND_CS_OFFS' to NAND_WRITE_CMD and NAND_WRITE_ADDR
- remove the unused macros
- update EBU_ADDR_MASK(x) macro
- update the EBU_ADDR_SELx register values to be written
v4:
- add ebu_nand_cs structure for multiple-CS support
- mask/offset encoding for 0x51 value
- update macro HSNAND_CTL_ENABLE_ECC
- drop the op argument and un-used macros.
- updated the datatype and macros
- add function disable nand module
- remove ebu_host->dma_rx = NULL;
- rename MMIO address range variables to ebu and hsnand
- implement ->setup_data_interface()
- update label err_cleanup_nand and err_cleanup_dma
- add return value check in the nand_remove function
- add/remove tabs and spaces as per coding standard
- encoded CS ids by reg property
v3:
- Add depends on MACRO in Kconfig
- file name update in Makefile
- file name update to intel-nand-controller
- modification of MACRO divided like EBU, HSNAND and NAND
- add NAND_ALE_OFFS, NAND_CLE_OFFS and NAND_CS_OFFS
- rename lgm_ to ebu_ and _va suffix is removed in the whole file
- rename structure and varaibles as per review comments.
- remove lgm_read_byte(), lgm_dev_ready() and cmd_ctrl() un-used function
- update in exec_op() as per review comments
- rename function lgm_dma_exit() by lgm_dma_cleanup()
- hardcoded magic value for base and offset replaced by MACRO defined
- mtd_device_unregister() + nand_cleanup() instead of nand_release()
v2:
- implement the ->exec_op() to replaces the legacy hook-up.
- update the commit message
- add MIPS maintainers and xway_nand driver author in CC
v1:
- initial version
dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC
---
v14:
- No change
v13:
- No change
v12-Resend:
- No Change
v12:
- No change
v11-resend:
- No change
v11:
- Fixed the compatible issue with example
10:
- fix bot errors
v9:
- Rob's review comments address
- dual licensed
- compatible change
- add reg-names
- drop clock-names and clock-cells
- correct typo's
v8:
No change
v7:
- Rob's review comments addressed
- dt-schema build issue fixed with upgraded dt-schema
v6:
- Rob's review comments addressed in YAML file
- add addr_sel0 and addr_sel1 reg-names in YAML example
v5:
- add the example in YAML file
v4:
- No change
v3:
- No change
v2:
YAML compatible string update to intel, lgm-nand-controller
v1:
- initial version
Ramuthevar Vadivel Murugan (2):
dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC
mtd: rawnand: Add NAND controller support on Intel LGM SoC
.../devicetree/bindings/mtd/intel,lgm-nand.yaml | 99 +++
drivers/mtd/nand/raw/Kconfig | 8 +
drivers/mtd/nand/raw/Makefile | 1 +
drivers/mtd/nand/raw/intel-nand-controller.c | 750 +++++++++++++++++++++
4 files changed, 858 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml
create mode 100644 drivers/mtd/nand/raw/intel-nand-controller.c
--
2.11.0
Hello,
"Ramuthevar,Vadivel MuruganX"
<[email protected]> wrote on Thu, 24 Sep 2020
16:48:40 +0800:
> This patch adds the new IP of Nand Flash Controller(NFC) support
> on Intel's Lightning Mountain(LGM) SoC.
>
> DMA is used for burst data transfer operation, also DMA HW supports
> aligned 32bit memory address and aligned data access by default.
> DMA burst of 8 supported. Data register used to support the read/write
> operation from/to device.
>
> NAND controller also supports in-built HW ECC engine.
>
> NAND controller driver implements ->exec_op() to replace legacy hooks,
> these specific call-back method to execute NAND operations.
>
> Thanks Miquel, Boris, Andy, Arnd and Rob for the review comments and suggestions.
> ---
> v14:
> - Address Andy's review comments
> - align the headers and revome Duplicates
> - replcace numerical const values by HZ_PER_MHZ and USEC_PER_SEC
> defined macros
> - add dev_err_probe() api instead of legacy err check
> - add get_unaligned_le32() api instead of manual endiness
> - remove redudent check
> - split the lines logically in between and add require spaces
> v13:
> - Address Miquel Raynal review comments
> - update the return type with variable 'ret'
> - handle err check statement properly
> - change the naming convention aligned with recently changed the naming
> around the data interface
> data structure and function names
> - replace by div 8 instead of <<4 in ecc calculation better code readability
> - handle check_only properly like existing drivers
I am sorry but there are two to three comments which you did not
address or addressed partially while not so impacting on the logic,
can you please review and address them all? (please note that I checked
the patch adding the driver before telling you that).
Thanks,
Miquèl
Hi Miquel,
On 28/9/2020 10:25 pm, Miquel Raynal wrote:
> Hello,
>
> "Ramuthevar,Vadivel MuruganX"
> <[email protected]> wrote on Thu, 24 Sep 2020
> 16:48:40 +0800:
>
>> This patch adds the new IP of Nand Flash Controller(NFC) support
>> on Intel's Lightning Mountain(LGM) SoC.
>>
>> DMA is used for burst data transfer operation, also DMA HW supports
>> aligned 32bit memory address and aligned data access by default.
>> DMA burst of 8 supported. Data register used to support the read/write
>> operation from/to device.
>>
>> NAND controller also supports in-built HW ECC engine.
>>
>> NAND controller driver implements ->exec_op() to replace legacy hooks,
>> these specific call-back method to execute NAND operations.
>>
>> Thanks Miquel, Boris, Andy, Arnd and Rob for the review comments and suggestions.
>> ---
>> v14:
>> - Address Andy's review comments
>> - align the headers and revome Duplicates
>> - replcace numerical const values by HZ_PER_MHZ and USEC_PER_SEC
>> defined macros
>> - add dev_err_probe() api instead of legacy err check
>> - add get_unaligned_le32() api instead of manual endiness
>> - remove redudent check
>> - split the lines logically in between and add require spaces
>> v13:
>> - Address Miquel Raynal review comments
>> - update the return type with variable 'ret'
>> - handle err check statement properly
>> - change the naming convention aligned with recently changed the naming
>> around the data interface
>> data structure and function names
>> - replace by div 8 instead of <<4 in ecc calculation better code readability
>> - handle check_only properly like existing drivers
>
> I am sorry but there are two to three comments which you did not
> address or addressed partially while not so impacting on the logic,
> can you please review and address them all? (please note that I checked
> the patch adding the driver before telling you that).
Thank you for your comments...!
Sure, I will review once again all your comments in the previous patch
sent if anything is missed then will add it and send the updated patch.
Regards
Vadivel
>
> Thanks,
> Miquèl
>