2020-09-25 23:51:10

by Lubomir Rintel

Subject: [PATCH] clk: mmp2: Fix the display clock divider base

The LCD clock dividers are apparently based on one. No datasheet,
determined empirically, but seems to be confirmed by line 19 of lcd.fth in
OLPC laptop's Open Firmware [1]:

h# 00000700 value pmua-disp-clk-sel \ PLL1 / 7 -> 113.86 MHz

[1] https://raw.githubusercontent.com/quozl/openfirmware/65a08a73b2cac/cpu/arm/olpc/lcd.fth

Signed-off-by: Lubomir Rintel <[email protected]>
---
drivers/clk/mmp/clk-of-mmp2.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c
index 67208aea94c5c..0839fb2049e94 100644
--- a/drivers/clk/mmp/clk-of-mmp2.c
+++ b/drivers/clk/mmp/clk-of-mmp2.c
@@ -347,9 +347,9 @@ static struct mmp_param_mux_clk mmp3_apmu_mux_clks[] = {
};

static struct mmp_param_div_clk apmu_div_clks[] = {
- {0, "disp0_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 8, 4, 0, &disp0_lock},
+ {0, "disp0_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 8, 4, CLK_DIVIDER_ONE_BASED, &disp0_lock},
{0, "disp0_sphy_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 15, 5, 0, &disp0_lock},
- {0, "disp1_div", "disp1_mux", CLK_SET_RATE_PARENT, APMU_DISP1, 8, 4, 0, &disp1_lock},
+ {0, "disp1_div", "disp1_mux", CLK_SET_RATE_PARENT, APMU_DISP1, 8, 4, CLK_DIVIDER_ONE_BASED, &disp1_lock},
{0, "ccic0_sphy_div", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
{0, "ccic1_sphy_div", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 10, 5, 0, &ccic1_lock},
};
--
2.26.2

2020-10-14 08:31:10

by Stephen Boyd

Subject: Re: [PATCH] clk: mmp2: Fix the display clock divider base

Quoting Lubomir Rintel (2020-09-25 16:39:14)
> The LCD clock dividers are apparently based on one. No datasheet,
> determined empirically, but seems to be confirmed by line 19 of lcd.fth in
> OLPC laptop's Open Firmware [1]:
>
> h# 00000700 value pmua-disp-clk-sel \ PLL1 / 7 -> 113.86 MHz
>
> [1] https://raw.githubusercontent.com/quozl/openfirmware/65a08a73b2cac/cpu/arm/olpc/lcd.fth
>
> Signed-off-by: Lubomir Rintel <[email protected]>
> ---

Applied to clk-next