Those are the remaining patches of the SP804/SP805 DT fixes. [1][2]
ARM, Broadcom and Freescale have their respective fixes queued through
their maintainers already, but I haven't heard back from LG or HiSilicon
so far.
So can those patches be taken through armsoc directly?
---------------------
Some DTs in the kernel tree were not conforming to the SP804 and SP805
binding.
Fix those DTs to correctly describe the clocks, while making sure that
the devices stay functional with the current Linux driver.
Thanks,
Andre
[1] http://lkml.iu.edu/hypermail/linux/kernel/2008.3/07072.html
[2] http://lkml.iu.edu/hypermail/linux/kernel/2008.3/07167.html
Andre Przywara (6):
ARM: dts: hisilicon: Fix SP804 users
ARM: dts: nspire: Fix SP804 users
arm64: dts: lg: Fix SP804 users
arm64: dts: hisilicon: Fix SP805 clocks
arm64: dts: lg: Fix SP805 clocks
ARM: dts: hisilicon: Fix SP805 clocks
arch/arm/boot/dts/hi3620.dtsi | 30 +++++++++++++++--------
arch/arm/boot/dts/hip04.dtsi | 4 +--
arch/arm/boot/dts/hisi-x5hd2.dtsi | 5 ++--
arch/arm/boot/dts/nspire.dtsi | 12 ++++++---
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 10 +++++---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 5 ++--
arch/arm64/boot/dts/lg/lg1312.dtsi | 10 ++++----
arch/arm64/boot/dts/lg/lg1313.dtsi | 10 ++++----
8 files changed, 52 insertions(+), 34 deletions(-)
--
2.17.1
The SP805 DT binding requires two clocks to be specified, but
Hisilicon platform DTs currently only specify one clock.
In practice, Linux would pick a clock named "apb_pclk" for the bus
clock, and the Linux and U-Boot SP805 driver would use the first clock
to derive the actual watchdog counter frequency.
Since currently both are the very same clock, we can just double the
clock reference, and add the correct clock-names, to match the binding.
Signed-off-by: Andre Przywara <[email protected]>
---
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 10 ++++++----
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 5 +++--
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index d25aac5e0bf8..994140fbc916 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -1089,16 +1089,18 @@
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xe8a06000 0x0 0x1000>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&crg_ctrl HI3660_OSC32K>;
- clock-names = "apb_pclk";
+ clocks = <&crg_ctrl HI3660_OSC32K>,
+ <&crg_ctrl HI3660_OSC32K>;
+ clock-names = "wdog_clk", "apb_pclk";
};
watchdog1: watchdog@e8a07000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xe8a07000 0x0 0x1000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&crg_ctrl HI3660_OSC32K>;
- clock-names = "apb_pclk";
+ clocks = <&crg_ctrl HI3660_OSC32K>,
+ <&crg_ctrl HI3660_OSC32K>;
+ clock-names = "wdog_clk", "apb_pclk";
};
tsensor: tsensor@fff30000 {
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 3d189d9f0d24..6578f8191d71 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -843,8 +843,9 @@
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xf8005000 0x0 0x1000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ao_ctrl HI6220_WDT0_PCLK>;
- clock-names = "apb_pclk";
+ clocks = <&ao_ctrl HI6220_WDT0_PCLK>,
+ <&ao_ctrl HI6220_WDT0_PCLK>;
+ clock-names = "wdog_clk", "apb_pclk";
};
tsensor: tsensor@0,f7030700 {
--
2.17.1
The SP804 binding only specifies one or three clocks, but does not allow
just two clocks.
The HiSi 3620 .dtsi specified two clocks for the two timers, plus gave
one "apb_pclk" clock-name to appease the primecell bus driver.
Extend the clocks by duplicating the first clock to the end of the clock
list, and add two dummy clock-names to make the primecell driver happy.
I don't know what the real APB clock for the IP is, but with the current
DT the first timer clock was used for that, so this change keeps the
current status.
Signed-off-by: Andre Przywara <[email protected]>
---
arch/arm/boot/dts/hi3620.dtsi | 30 ++++++++++++++++++++----------
arch/arm/boot/dts/hip04.dtsi | 4 ++--
2 files changed, 22 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index f0af1bf2b4d8..355175b25fd6 100644
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -111,8 +111,10 @@
reg = <0x800000 0x1000>;
/* timer00 & timer01 */
interrupts = <0 0 4>, <0 1 4>;
- clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>;
- clock-names = "apb_pclk";
+ clocks = <&clock HI3620_TIMER0_MUX>,
+ <&clock HI3620_TIMER1_MUX>,
+ <&clock HI3620_TIMER0_MUX>;
+ clock-names = "timer0clk", "timer1clk", "apb_pclk";
status = "disabled";
};
@@ -121,8 +123,10 @@
reg = <0x801000 0x1000>;
/* timer10 & timer11 */
interrupts = <0 2 4>, <0 3 4>;
- clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>;
- clock-names = "apb_pclk";
+ clocks = <&clock HI3620_TIMER2_MUX>,
+ <&clock HI3620_TIMER3_MUX>,
+ <&clock HI3620_TIMER2_MUX>;
+ clock-names = "timer0clk", "timer1clk", "apb_pclk";
status = "disabled";
};
@@ -131,8 +135,10 @@
reg = <0xa01000 0x1000>;
/* timer20 & timer21 */
interrupts = <0 4 4>, <0 5 4>;
- clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>;
- clock-names = "apb_pclk";
+ clocks = <&clock HI3620_TIMER4_MUX>,
+ <&clock HI3620_TIMER5_MUX>,
+ <&clock HI3620_TIMER4_MUX>;
+ clock-names = "timer0lck", "timer1clk", "apb_pclk";
status = "disabled";
};
@@ -141,8 +147,10 @@
reg = <0xa02000 0x1000>;
/* timer30 & timer31 */
interrupts = <0 6 4>, <0 7 4>;
- clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>;
- clock-names = "apb_pclk";
+ clocks = <&clock HI3620_TIMER6_MUX>,
+ <&clock HI3620_TIMER7_MUX>,
+ <&clock HI3620_TIMER6_MUX>;
+ clock-names = "timer0clk", "timer1clk", "apb_pclk";
status = "disabled";
};
@@ -151,8 +159,10 @@
reg = <0xa03000 0x1000>;
/* timer40 & timer41 */
interrupts = <0 96 4>, <0 97 4>;
- clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>;
- clock-names = "apb_pclk";
+ clocks = <&clock HI3620_TIMER8_MUX>,
+ <&clock HI3620_TIMER9_MUX>,
+ <&clock HI3620_TIMER8_MUX>;
+ clock-names = "timer0clk", "timer1clk", "apb_pclk";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
index 4263a9339c2e..f5871b1d1ec4 100644
--- a/arch/arm/boot/dts/hip04.dtsi
+++ b/arch/arm/boot/dts/hip04.dtsi
@@ -226,8 +226,8 @@
compatible = "arm,sp804", "arm,primecell";
reg = <0x3000000 0x1000>;
interrupts = <0 224 4>;
- clocks = <&clk_50m>, <&clk_50m>;
- clock-names = "apb_pclk";
+ clocks = <&clk_50m>, <&clk_50m>, <&clk_50m>;
+ clock-names = "timer0clk", "timer1clk", "apb_pclk";
};
arm-pmu {
--
2.17.1
Even though the SP804 binding allows to specify only one clock, the
primecell driver requires a named clock to activate the bus clock.
Specify the one clock three times and provide some clock-names, to
make the DT match the SP804 and primecell binding.
Also add the missing arm,primecell compatible string.
Signed-off-by: Andre Przywara <[email protected]>
---
arch/arm64/boot/dts/lg/lg1312.dtsi | 6 +++---
arch/arm64/boot/dts/lg/lg1313.dtsi | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi
index 64f3b135068d..e2a1564597c8 100644
--- a/arch/arm64/boot/dts/lg/lg1312.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1312.dtsi
@@ -131,11 +131,11 @@
ranges;
timers: timer@fd100000 {
- compatible = "arm,sp804";
+ compatible = "arm,sp804", "arm,primecell";
reg = <0x0 0xfd100000 0x1000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
+ clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>;
+ clock-names = "timer0clk", "timer1clk", "apb_pclk";
};
wdog: watchdog@fd200000 {
compatible = "arm,sp805", "arm,primecell";
diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi
index ac23592ab011..a54d14d7ae6f 100644
--- a/arch/arm64/boot/dts/lg/lg1313.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1313.dtsi
@@ -131,11 +131,11 @@
ranges;
timers: timer@fd100000 {
- compatible = "arm,sp804";
+ compatible = "arm,sp804", "arm,primecell";
reg = <0x0 0xfd100000 0x1000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
+ clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>;
+ clock-names = "timer0clk", "timer1clk", "apb_pclk";
};
wdog: watchdog@fd200000 {
compatible = "arm,sp805", "arm,primecell";
--
2.17.1
Even though the SP804 binding allows to specify only one clock, the
primecell driver requires a named clock to activate the bus clock.
Specify the one clock three times and provide some clock-names, to
make the DT match the SP804 and primecell binding.
Signed-off-by: Andre Przywara <[email protected]>
---
arch/arm/boot/dts/nspire.dtsi | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi
index d9a0fd7524dc..90e033d9141f 100644
--- a/arch/arm/boot/dts/nspire.dtsi
+++ b/arch/arm/boot/dts/nspire.dtsi
@@ -145,15 +145,19 @@
timer0: timer@900C0000 {
reg = <0x900C0000 0x1000>;
-
- clocks = <&timer_clk>;
+ clocks = <&timer_clk>, <&timer_clk>,
+ <&timer_clk>;
+ clock-names = "timer0clk", "timer1clk",
+ "apb_pclk";
};
timer1: timer@900D0000 {
reg = <0x900D0000 0x1000>;
interrupts = <19>;
-
- clocks = <&timer_clk>;
+ clocks = <&timer_clk>, <&timer_clk>,
+ <&timer_clk>;
+ clock-names = "timer0clk", "timer1clk",
+ "apb_pclk";
};
watchdog: watchdog@90060000 {
--
2.17.1
The SP805 DT binding requires two clocks to be specified, but
Hisilicon platform DTs currently only specify one clock.
In practice, Linux would pick a clock named "apb_pclk" for the bus
clock, and the Linux and U-Boot SP805 driver would use the first clock
to derive the actual watchdog counter frequency.
Since currently both are the very same clock, we can just double the
clock reference, and add the correct clock-names, to match the binding.
Signed-off-by: Andre Przywara <[email protected]>
---
arch/arm/boot/dts/hisi-x5hd2.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index 3ee7967c202d..e2dbf1d8a67b 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -370,8 +370,9 @@
arm,primecell-periphid = <0x00141805>;
reg = <0xa2c000 0x1000>;
interrupts = <0 29 4>;
- clocks = <&clock HIX5HD2_WDG0_RST>;
- clock-names = "apb_pclk";
+ clocks = <&clock HIX5HD2_WDG0_RST>,
+ <&clock HIX5HD2_WDG0_RST>;
+ clock-names = "wdog_clk", "apb_pclk";
};
};
--
2.17.1
On 2020/9/7 20:18, Andre Przywara wrote:
> The SP805 DT binding requires two clocks to be specified, but
> Hisilicon platform DTs currently only specify one clock.
>
> In practice, Linux would pick a clock named "apb_pclk" for the bus
> clock, and the Linux and U-Boot SP805 driver would use the first clock
> to derive the actual watchdog counter frequency.
>
> Since currently both are the very same clock, we can just double the
> clock reference, and add the correct clock-names, to match the binding.
>
> Signed-off-by: Andre Przywara <[email protected]>
Thanks!
Applied to the hisilicon arm32 dt tree.
Best Regards,
Wei
> ---
> arch/arm/boot/dts/hisi-x5hd2.dtsi | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi
> index 3ee7967c202d..e2dbf1d8a67b 100644
> --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
> +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
> @@ -370,8 +370,9 @@
> arm,primecell-periphid = <0x00141805>;
> reg = <0xa2c000 0x1000>;
> interrupts = <0 29 4>;
> - clocks = <&clock HIX5HD2_WDG0_RST>;
> - clock-names = "apb_pclk";
> + clocks = <&clock HIX5HD2_WDG0_RST>,
> + <&clock HIX5HD2_WDG0_RST>;
> + clock-names = "wdog_clk", "apb_pclk";
> };
> };
>
>
Hi Andre,
On 2020/9/7 20:18, Andre Przywara wrote:
> The SP804 binding only specifies one or three clocks, but does not allow
> just two clocks.
> The HiSi 3620 .dtsi specified two clocks for the two timers, plus gave
> one "apb_pclk" clock-name to appease the primecell bus driver.
>
> Extend the clocks by duplicating the first clock to the end of the clock
> list, and add two dummy clock-names to make the primecell driver happy.
>
> I don't know what the real APB clock for the IP is, but with the current
> DT the first timer clock was used for that, so this change keeps the
> current status.
>
> Signed-off-by: Andre Przywara <[email protected]>
Thanks!
Applied to the hisilicon arm32 dt tree.
Best Regards,
Wei
> ---
> arch/arm/boot/dts/hi3620.dtsi | 30 ++++++++++++++++++++----------
> arch/arm/boot/dts/hip04.dtsi | 4 ++--
> 2 files changed, 22 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
> index f0af1bf2b4d8..355175b25fd6 100644
> --- a/arch/arm/boot/dts/hi3620.dtsi
> +++ b/arch/arm/boot/dts/hi3620.dtsi
> @@ -111,8 +111,10 @@
> reg = <0x800000 0x1000>;
> /* timer00 & timer01 */
> interrupts = <0 0 4>, <0 1 4>;
> - clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>;
> - clock-names = "apb_pclk";
> + clocks = <&clock HI3620_TIMER0_MUX>,
> + <&clock HI3620_TIMER1_MUX>,
> + <&clock HI3620_TIMER0_MUX>;
> + clock-names = "timer0clk", "timer1clk", "apb_pclk";
> status = "disabled";
> };
>
> @@ -121,8 +123,10 @@
> reg = <0x801000 0x1000>;
> /* timer10 & timer11 */
> interrupts = <0 2 4>, <0 3 4>;
> - clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>;
> - clock-names = "apb_pclk";
> + clocks = <&clock HI3620_TIMER2_MUX>,
> + <&clock HI3620_TIMER3_MUX>,
> + <&clock HI3620_TIMER2_MUX>;
> + clock-names = "timer0clk", "timer1clk", "apb_pclk";
> status = "disabled";
> };
>
> @@ -131,8 +135,10 @@
> reg = <0xa01000 0x1000>;
> /* timer20 & timer21 */
> interrupts = <0 4 4>, <0 5 4>;
> - clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>;
> - clock-names = "apb_pclk";
> + clocks = <&clock HI3620_TIMER4_MUX>,
> + <&clock HI3620_TIMER5_MUX>,
> + <&clock HI3620_TIMER4_MUX>;
> + clock-names = "timer0lck", "timer1clk", "apb_pclk";
> status = "disabled";
> };
>
> @@ -141,8 +147,10 @@
> reg = <0xa02000 0x1000>;
> /* timer30 & timer31 */
> interrupts = <0 6 4>, <0 7 4>;
> - clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>;
> - clock-names = "apb_pclk";
> + clocks = <&clock HI3620_TIMER6_MUX>,
> + <&clock HI3620_TIMER7_MUX>,
> + <&clock HI3620_TIMER6_MUX>;
> + clock-names = "timer0clk", "timer1clk", "apb_pclk";
> status = "disabled";
> };
>
> @@ -151,8 +159,10 @@
> reg = <0xa03000 0x1000>;
> /* timer40 & timer41 */
> interrupts = <0 96 4>, <0 97 4>;
> - clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>;
> - clock-names = "apb_pclk";
> + clocks = <&clock HI3620_TIMER8_MUX>,
> + <&clock HI3620_TIMER9_MUX>,
> + <&clock HI3620_TIMER8_MUX>;
> + clock-names = "timer0clk", "timer1clk", "apb_pclk";
> status = "disabled";
> };
>
> diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
> index 4263a9339c2e..f5871b1d1ec4 100644
> --- a/arch/arm/boot/dts/hip04.dtsi
> +++ b/arch/arm/boot/dts/hip04.dtsi
> @@ -226,8 +226,8 @@
> compatible = "arm,sp804", "arm,primecell";
> reg = <0x3000000 0x1000>;
> interrupts = <0 224 4>;
> - clocks = <&clk_50m>, <&clk_50m>;
> - clock-names = "apb_pclk";
> + clocks = <&clk_50m>, <&clk_50m>, <&clk_50m>;
> + clock-names = "timer0clk", "timer1clk", "apb_pclk";
> };
>
> arm-pmu {
>
Hi Andre,
On 2020/9/7 20:18, Andre Przywara wrote:
> The SP805 DT binding requires two clocks to be specified, but
> Hisilicon platform DTs currently only specify one clock.
>
> In practice, Linux would pick a clock named "apb_pclk" for the bus
> clock, and the Linux and U-Boot SP805 driver would use the first clock
> to derive the actual watchdog counter frequency.
>
> Since currently both are the very same clock, we can just double the
> clock reference, and add the correct clock-names, to match the binding.
>
> Signed-off-by: Andre Przywara <[email protected]>
Thanks!
Applied to the hisilicon arm64 dt tree.
Best Regards,
Wei
> ---
> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 10 ++++++----
> arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 5 +++--
> 2 files changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> index d25aac5e0bf8..994140fbc916 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> @@ -1089,16 +1089,18 @@
> compatible = "arm,sp805-wdt", "arm,primecell";
> reg = <0x0 0xe8a06000 0x0 0x1000>;
> interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&crg_ctrl HI3660_OSC32K>;
> - clock-names = "apb_pclk";
> + clocks = <&crg_ctrl HI3660_OSC32K>,
> + <&crg_ctrl HI3660_OSC32K>;
> + clock-names = "wdog_clk", "apb_pclk";
> };
>
> watchdog1: watchdog@e8a07000 {
> compatible = "arm,sp805-wdt", "arm,primecell";
> reg = <0x0 0xe8a07000 0x0 0x1000>;
> interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&crg_ctrl HI3660_OSC32K>;
> - clock-names = "apb_pclk";
> + clocks = <&crg_ctrl HI3660_OSC32K>,
> + <&crg_ctrl HI3660_OSC32K>;
> + clock-names = "wdog_clk", "apb_pclk";
> };
>
> tsensor: tsensor@fff30000 {
> diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> index 3d189d9f0d24..6578f8191d71 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> @@ -843,8 +843,9 @@
> compatible = "arm,sp805-wdt", "arm,primecell";
> reg = <0x0 0xf8005000 0x0 0x1000>;
> interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&ao_ctrl HI6220_WDT0_PCLK>;
> - clock-names = "apb_pclk";
> + clocks = <&ao_ctrl HI6220_WDT0_PCLK>,
> + <&ao_ctrl HI6220_WDT0_PCLK>;
> + clock-names = "wdog_clk", "apb_pclk";
> };
>
> tsensor: tsensor@0,f7030700 {
>
On Mon, Sep 07, 2020 at 01:18:25PM +0100, Andre Przywara wrote:
> Those are the remaining patches of the SP804/SP805 DT fixes. [1][2]
> ARM, Broadcom and Freescale have their respective fixes queued through
> their maintainers already, but I haven't heard back from LG or HiSilicon
> so far.
> So can those patches be taken through armsoc directly?
I've applied the ones who didn't have replies from platform maintainers yet.
Thanks!
-Olof