The series add support for the serial GPIO controller used by
Microchip Sparx5, as well as (MSCC) ocelot/jaguar2 SoCs.
The driver now register two separate banks (per instance), one for
input pins (the first) and one for output direction. This eliminates
the need for specifying the direction as part of the gpio
arguments. The (fixed) direction is thus inherent from the gpio
handle.
v3 changes:
- Renamed all usage of "mchp" abbrevation with "microchip".
- Split the in/output directions into (two) separate banks.
- Eliminated the bindings include file (from above)
- Changed SPDX license to "GPL-2.0-or-later"
- Change -ENOTSUPP to -EOPNOTSUPP
- Minor type/symbol naming changes
v2 changes:
- Adds both in and output modes.
- Use direct adressing of the individual banks (#gpio-cells = <4>),
also osoleting need for addressing macros in bindings include file.
- Property 'microchip,sgpio-ports' (uint32, bitmask) replaced by
proper range set (array of [start,end]) 'microchip,sgpio-port-ranges'.
- Fixes whitespace issues in Kconfig file
Lars Povlsen (3):
dt-bindings: pinctrl: Add bindings for pinctrl-mchp-sgpio driver
pinctrl: pinctrl-mchp-sgpio: Add pinctrl driver for Microsemi Serial
GPIO
arm64: dts: sparx5: Add SGPIO devices
.../pinctrl/microchip,sparx5-sgpio.yaml | 127 ++++
MAINTAINERS | 1 +
arch/arm64/boot/dts/microchip/sparx5.dtsi | 91 +++
.../boot/dts/microchip/sparx5_pcb125.dts | 5 +
.../dts/microchip/sparx5_pcb134_board.dtsi | 262 +++++++
.../dts/microchip/sparx5_pcb135_board.dtsi | 57 ++
drivers/pinctrl/Kconfig | 18 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-microchip-sgpio.c | 676 ++++++++++++++++++
9 files changed, 1238 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml
create mode 100644 drivers/pinctrl/pinctrl-microchip-sgpio.c
--
2.25.1
This adds SGPIO devices for the Sparx5 SoC and configures it for the
applicable reference boards.
Signed-off-by: Lars Povlsen <[email protected]>
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 91 ++++++
.../boot/dts/microchip/sparx5_pcb125.dts | 5 +
.../dts/microchip/sparx5_pcb134_board.dtsi | 262 ++++++++++++++++++
.../dts/microchip/sparx5_pcb135_board.dtsi | 57 ++++
4 files changed, 415 insertions(+)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index fc1c7807249f..326ace6d35a3 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -232,6 +232,22 @@ si2_pins: si2-pins {
function = "si2";
};
+ sgpio0_pins: sgpio-pins {
+ pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
+ function = "sg0";
+ };
+
+ sgpio1_pins: sgpio1-pins {
+ pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13";
+ function = "sg1";
+ };
+
+ sgpio2_pins: sgpio2-pins {
+ pins = "GPIO_30", "GPIO_31", "GPIO_32",
+ "GPIO_33";
+ function = "sg2";
+ };
+
uart_pins: uart-pins {
pins = "GPIO_10", "GPIO_11";
function = "uart";
@@ -262,6 +278,81 @@ emmc_pins: emmc-pins {
};
};
+ sgpio0: gpio@61101036c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "microchip,sparx5-sgpio";
+ status = "disabled";
+ clocks = <&sys_clk>;
+ pinctrl-0 = <&sgpio0_pins>;
+ pinctrl-names = "default";
+ reg = <0x6 0x1101036c 0x100>;
+ sgpio_in0: gpio-controller@0 {
+ compatible = "microchip,sparx5-sgpio-bank";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ ngpios = <96>;
+ };
+ sgpio_out0: gpio-controller@1 {
+ compatible = "microchip,sparx5-sgpio-bank";
+ reg = <1>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ ngpios = <96>;
+ };
+ };
+
+ sgpio1: gpio@611010484 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "microchip,sparx5-sgpio";
+ status = "disabled";
+ clocks = <&sys_clk>;
+ pinctrl-0 = <&sgpio1_pins>;
+ pinctrl-names = "default";
+ reg = <0x6 0x11010484 0x100>;
+ sgpio_in1: gpio-controller@0 {
+ compatible = "microchip,sparx5-sgpio-bank";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ ngpios = <96>;
+ };
+ sgpio_out1: gpio-controller@1 {
+ compatible = "microchip,sparx5-sgpio-bank";
+ reg = <1>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ ngpios = <96>;
+ };
+ };
+
+ sgpio2: gpio@61101059c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "microchip,sparx5-sgpio";
+ status = "disabled";
+ clocks = <&sys_clk>;
+ pinctrl-0 = <&sgpio2_pins>;
+ pinctrl-names = "default";
+ reg = <0x6 0x1101059c 0x100>;
+ sgpio_in2: gpio-controller@0 {
+ reg = <0>;
+ compatible = "microchip,sparx5-sgpio-bank";
+ gpio-controller;
+ #gpio-cells = <3>;
+ ngpios = <96>;
+ };
+ sgpio_out2: gpio-controller@1 {
+ compatible = "microchip,sparx5-sgpio-bank";
+ reg = <1>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ ngpios = <96>;
+ };
+ };
+
i2c0: i2c@600101000 {
compatible = "snps,designware-i2c";
status = "disabled";
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
index 6b2da7c7520c..9baa085d7861 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
@@ -69,6 +69,11 @@ spi-flash@9 {
};
};
+&sgpio0 {
+ status = "okay";
+ microchip,sgpio-port-ranges = <0 23>;
+};
+
&i2c1 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
index 35984785d611..9571f14ba51e 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
@@ -36,6 +36,242 @@ gpio-restart {
gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
priority = <200>;
};
+
+ leds {
+ compatible = "gpio-leds";
+ led@0 {
+ label = "twr0:green";
+ gpios = <&sgpio_out0 8 0 GPIO_ACTIVE_LOW>;
+ };
+ led@1 {
+ label = "twr0:yellow";
+ gpios = <&sgpio_out0 8 1 GPIO_ACTIVE_LOW>;
+ };
+ led@2 {
+ label = "twr1:green";
+ gpios = <&sgpio_out0 9 0 GPIO_ACTIVE_LOW>;
+ };
+ led@3 {
+ label = "twr1:yellow";
+ gpios = <&sgpio_out0 9 1 GPIO_ACTIVE_LOW>;
+ };
+ led@4 {
+ label = "twr2:green";
+ gpios = <&sgpio_out0 10 0 GPIO_ACTIVE_LOW>;
+ };
+ led@5 {
+ label = "twr2:yellow";
+ gpios = <&sgpio_out0 10 1 GPIO_ACTIVE_LOW>;
+ };
+ led@6 {
+ label = "twr3:green";
+ gpios = <&sgpio_out0 11 0 GPIO_ACTIVE_LOW>;
+ };
+ led@7 {
+ label = "twr3:yellow";
+ gpios = <&sgpio_out0 11 1 GPIO_ACTIVE_LOW>;
+ };
+ led@8 {
+ label = "eth12:green";
+ gpios = <&sgpio_out0 12 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@9 {
+ label = "eth12:yellow";
+ gpios = <&sgpio_out0 12 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@10 {
+ label = "eth13:green";
+ gpios = <&sgpio_out0 13 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@11 {
+ label = "eth13:yellow";
+ gpios = <&sgpio_out0 13 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@12 {
+ label = "eth14:green";
+ gpios = <&sgpio_out0 14 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@13 {
+ label = "eth14:yellow";
+ gpios = <&sgpio_out0 14 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@14 {
+ label = "eth15:green";
+ gpios = <&sgpio_out0 15 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@15 {
+ label = "eth15:yellow";
+ gpios = <&sgpio_out0 15 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@16 {
+ label = "eth48:green";
+ gpios = <&sgpio_out1 16 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@17 {
+ label = "eth48:yellow";
+ gpios = <&sgpio_out1 16 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@18 {
+ label = "eth49:green";
+ gpios = <&sgpio_out1 17 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@19 {
+ label = "eth49:yellow";
+ gpios = <&sgpio_out1 17 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@20 {
+ label = "eth50:green";
+ gpios = <&sgpio_out1 18 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@21 {
+ label = "eth50:yellow";
+ gpios = <&sgpio_out1 18 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@22 {
+ label = "eth51:green";
+ gpios = <&sgpio_out1 19 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@23 {
+ label = "eth51:yellow";
+ gpios = <&sgpio_out1 19 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@24 {
+ label = "eth52:green";
+ gpios = <&sgpio_out1 20 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@25 {
+ label = "eth52:yellow";
+ gpios = <&sgpio_out1 20 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@26 {
+ label = "eth53:green";
+ gpios = <&sgpio_out1 21 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@27 {
+ label = "eth53:yellow";
+ gpios = <&sgpio_out1 21 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@28 {
+ label = "eth54:green";
+ gpios = <&sgpio_out1 22 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@29 {
+ label = "eth54:yellow";
+ gpios = <&sgpio_out1 22 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@30 {
+ label = "eth55:green";
+ gpios = <&sgpio_out1 23 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@31 {
+ label = "eth55:yellow";
+ gpios = <&sgpio_out1 23 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@32 {
+ label = "eth56:green";
+ gpios = <&sgpio_out1 24 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@33 {
+ label = "eth56:yellow";
+ gpios = <&sgpio_out1 24 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@34 {
+ label = "eth57:green";
+ gpios = <&sgpio_out1 25 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@35 {
+ label = "eth57:yellow";
+ gpios = <&sgpio_out1 25 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@36 {
+ label = "eth58:green";
+ gpios = <&sgpio_out1 26 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@37 {
+ label = "eth58:yellow";
+ gpios = <&sgpio_out1 26 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@38 {
+ label = "eth59:green";
+ gpios = <&sgpio_out1 27 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@39 {
+ label = "eth59:yellow";
+ gpios = <&sgpio_out1 27 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@40 {
+ label = "eth60:green";
+ gpios = <&sgpio_out1 28 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@41 {
+ label = "eth60:yellow";
+ gpios = <&sgpio_out1 28 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@42 {
+ label = "eth61:green";
+ gpios = <&sgpio_out1 29 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@43 {
+ label = "eth61:yellow";
+ gpios = <&sgpio_out1 29 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@44 {
+ label = "eth62:green";
+ gpios = <&sgpio_out1 30 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@45 {
+ label = "eth62:yellow";
+ gpios = <&sgpio_out1 30 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@46 {
+ label = "eth63:green";
+ gpios = <&sgpio_out1 31 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led@47 {
+ label = "eth63:yellow";
+ gpios = <&sgpio_out1 31 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
};
&spi0 {
@@ -54,6 +290,32 @@ spi-flash@9 {
};
};
+&sgpio0 {
+ status = "okay";
+ microchip,sgpio-port-ranges = <8 15>;
+};
+
+&sgpio_in0 {
+ ngpios = <64>;
+};
+
+&sgpio_out0 {
+ ngpios = <64>;
+};
+
+&sgpio1 {
+ status = "okay";
+ microchip,sgpio-port-ranges = <24 31>;
+};
+
+&sgpio_in1 {
+ ngpios = <64>;
+};
+
+&sgpio_out1 {
+ ngpios = <64>;
+};
+
&gpio {
i2cmux_pins_i: i2cmux-pins-i {
pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19",
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
index 7de66806b14b..c85e4d6900b6 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
@@ -20,6 +20,50 @@ gpio-restart {
gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
priority = <200>;
};
+
+ leds {
+ compatible = "gpio-leds";
+ led@0 {
+ label = "eth60:yellow";
+ gpios = <&sgpio_out1 28 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ led@1 {
+ label = "eth60:green";
+ gpios = <&sgpio_out1 28 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ led@2 {
+ label = "eth61:yellow";
+ gpios = <&sgpio_out1 29 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ led@3 {
+ label = "eth61:green";
+ gpios = <&sgpio_out1 29 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ led@4 {
+ label = "eth62:yellow";
+ gpios = <&sgpio_out1 30 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ led@5 {
+ label = "eth62:green";
+ gpios = <&sgpio_out1 30 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ led@6 {
+ label = "eth63:yellow";
+ gpios = <&sgpio_out1 31 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ led@7 {
+ label = "eth63:green";
+ gpios = <&sgpio_out1 31 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
};
&gpio {
@@ -67,6 +111,19 @@ spi-flash@9 {
};
};
+&sgpio1 {
+ status = "okay";
+ microchip,sgpio-port-ranges = <24 31>;
+};
+
+&sgpio_in1 {
+ ngpios = <64>;
+};
+
+&sgpio_out1 {
+ ngpios = <64>;
+};
+
&axi {
i2c0_imux: i2c0-imux@0 {
compatible = "i2c-mux-pinctrl";
--
2.25.1
This adds DT bindings for the Microsemi/Microchip SGPIO controller,
bindings microchip,sparx5-sgpio, mscc,ocelot-sgpio and
mscc,luton-sgpio.
Signed-off-by: Lars Povlsen <[email protected]>
---
.../pinctrl/microchip,sparx5-sgpio.yaml | 127 ++++++++++++++++++
1 file changed, 127 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml
new file mode 100644
index 000000000000..e3618ed28165
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microsemi/Microchip Serial GPIO controller
+
+maintainers:
+ - Lars Povlsen <[email protected]>
+
+description: |
+ By using a serial interface, the SIO controller significantly extend
+ the number of available GPIOs with a minimum number of additional
+ pins on the device. The primary purpose of the SIO controllers is to
+ connect control signals from SFP modules and to act as an LED
+ controller.
+
+properties:
+ $nodename:
+ pattern: "^gpio@[0-9a-f]+$"
+
+ compatible:
+ enum:
+ - microchip,sparx5-sgpio
+ - mscc,ocelot-sgpio
+ - mscc,luton-sgpio
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ microchip,sgpio-port-ranges:
+ description: This is a sequence of tuples, defining intervals of
+ enabled ports in the serial input stream. The enabled ports must
+ match the hardware configuration in order for signals to be
+ properly written/read to/from the controller holding
+ registers. Being tuples, then number of arguments must be
+ even. The tuples mast be ordered (low, high) and are
+ inclusive. Arguments must be between 0 and 31.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 2
+ maxItems: 64
+
+ microchip,sgpio-frequency:
+ description: The sgpio controller frequency (Hz). This dictates
+ the serial bitstream speed, which again affects the latency in
+ getting control signals back and forth between external shift
+ registers. The speed must be no larger than half the system
+ clock, and larger than zero.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ default: 12500000
+
+patternProperties:
+ "^gpio-(port|controller)@[01]$":
+ type: object
+ properties:
+ compatible:
+ const: microchip,sparx5-sgpio-bank
+
+ reg:
+ maxItems: 1
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 3
+
+ ngpios:
+ minimum: 1
+ maximum: 128
+
+ required:
+ - compatible
+ - reg
+ - gpio-controller
+ - '#gpio-cells'
+ - ngpios
+
+ additionalProperties: false
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - microchip,sgpio-port-ranges
+ - "#address-cells"
+ - "#size-cells"
+
+examples:
+ - |
+ sgpio2: gpio@1101059c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "microchip,sparx5-sgpio";
+ clocks = <&sys_clk>;
+ pinctrl-0 = <&sgpio2_pins>;
+ pinctrl-names = "default";
+ reg = <0x1101059c 0x100>;
+ microchip,sgpio-port-ranges = <0 0 16 18 28 31>;
+ microchip,sgpio-frequency = <25000000>;
+ sgpio_in2: gpio-controller@0 {
+ reg = <0>;
+ compatible = "microchip,sparx5-sgpio-bank";
+ gpio-controller;
+ #gpio-cells = <3>;
+ ngpios = <96>;
+ };
+ sgpio_out2: gpio-controller@1 {
+ compatible = "microchip,sparx5-sgpio-bank";
+ reg = <1>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ ngpios = <96>;
+ };
+ };
--
2.25.1
On Tue, Oct 06, 2020 at 04:25:30PM +0200, Lars Povlsen wrote:
> This adds DT bindings for the Microsemi/Microchip SGPIO controller,
> bindings microchip,sparx5-sgpio, mscc,ocelot-sgpio and
> mscc,luton-sgpio.
>
> Signed-off-by: Lars Povlsen <[email protected]>
> ---
> .../pinctrl/microchip,sparx5-sgpio.yaml | 127 ++++++++++++++++++
> 1 file changed, 127 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml
> new file mode 100644
> index 000000000000..e3618ed28165
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml
> @@ -0,0 +1,127 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microsemi/Microchip Serial GPIO controller
> +
> +maintainers:
> + - Lars Povlsen <[email protected]>
> +
> +description: |
> + By using a serial interface, the SIO controller significantly extend
> + the number of available GPIOs with a minimum number of additional
> + pins on the device. The primary purpose of the SIO controllers is to
> + connect control signals from SFP modules and to act as an LED
> + controller.
> +
> +properties:
> + $nodename:
> + pattern: "^gpio@[0-9a-f]+$"
> +
> + compatible:
> + enum:
> + - microchip,sparx5-sgpio
> + - mscc,ocelot-sgpio
> + - mscc,luton-sgpio
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 0
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + microchip,sgpio-port-ranges:
> + description: This is a sequence of tuples, defining intervals of
> + enabled ports in the serial input stream. The enabled ports must
> + match the hardware configuration in order for signals to be
> + properly written/read to/from the controller holding
> + registers. Being tuples, then number of arguments must be
> + even. The tuples mast be ordered (low, high) and are
> + inclusive. Arguments must be between 0 and 31.
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + minItems: 2
> + maxItems: 64
> +
> + microchip,sgpio-frequency:
> + description: The sgpio controller frequency (Hz). This dictates
> + the serial bitstream speed, which again affects the latency in
> + getting control signals back and forth between external shift
> + registers. The speed must be no larger than half the system
> + clock, and larger than zero.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 1
> + default: 12500000
> +
> +patternProperties:
> + "^gpio-(port|controller)@[01]$":
gpio@... is correct here as the node is a gpio-controller (no, we're
not consistent).
> + type: object
> + properties:
> + compatible:
> + const: microchip,sparx5-sgpio-bank
> +
> + reg:
> + maxItems: 1
> +
> + gpio-controller: true
> +
> + '#gpio-cells':
> + const: 3
> +
> + ngpios:
> + minimum: 1
> + maximum: 128
> +
> + required:
> + - compatible
> + - reg
> + - gpio-controller
> + - '#gpio-cells'
> + - ngpios
> +
> + additionalProperties: false
> +
> +additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - microchip,sgpio-port-ranges
> + - "#address-cells"
> + - "#size-cells"
> +
> +examples:
> + - |
> + sgpio2: gpio@1101059c {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "microchip,sparx5-sgpio";
> + clocks = <&sys_clk>;
> + pinctrl-0 = <&sgpio2_pins>;
> + pinctrl-names = "default";
> + reg = <0x1101059c 0x100>;
> + microchip,sgpio-port-ranges = <0 0 16 18 28 31>;
Since it's tuples, do:
<0 0>, <16 18>, <28 31>
> + microchip,sgpio-frequency = <25000000>;
Some whitespace issues here.
> + sgpio_in2: gpio-controller@0 {
> + reg = <0>;
> + compatible = "microchip,sparx5-sgpio-bank";
> + gpio-controller;
> + #gpio-cells = <3>;
> + ngpios = <96>;
> + };
> + sgpio_out2: gpio-controller@1 {
> + compatible = "microchip,sparx5-sgpio-bank";
> + reg = <1>;
> + gpio-controller;
> + #gpio-cells = <3>;
> + ngpios = <96>;
> + };
> + };
> --
> 2.25.1
Hi Rob!
Rob Herring writes:
> On Tue, Oct 06, 2020 at 04:25:30PM +0200, Lars Povlsen wrote:
>> This adds DT bindings for the Microsemi/Microchip SGPIO controller,
>> bindings microchip,sparx5-sgpio, mscc,ocelot-sgpio and
>> mscc,luton-sgpio.
>>
>> Signed-off-by: Lars Povlsen <[email protected]>
>> ---
>> .../pinctrl/microchip,sparx5-sgpio.yaml | 127 ++++++++++++++++++
>> 1 file changed, 127 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml
>> new file mode 100644
>> index 000000000000..e3618ed28165
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml
>> @@ -0,0 +1,127 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Microsemi/Microchip Serial GPIO controller
>> +
>> +maintainers:
>> + - Lars Povlsen <[email protected]>
>> +
>> +description: |
>> + By using a serial interface, the SIO controller significantly extend
>> + the number of available GPIOs with a minimum number of additional
>> + pins on the device. The primary purpose of the SIO controllers is to
>> + connect control signals from SFP modules and to act as an LED
>> + controller.
>> +
>> +properties:
>> + $nodename:
>> + pattern: "^gpio@[0-9a-f]+$"
>> +
>> + compatible:
>> + enum:
>> + - microchip,sparx5-sgpio
>> + - mscc,ocelot-sgpio
>> + - mscc,luton-sgpio
>> +
>> + "#address-cells":
>> + const: 1
>> +
>> + "#size-cells":
>> + const: 0
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + maxItems: 1
>> +
>> + microchip,sgpio-port-ranges:
>> + description: This is a sequence of tuples, defining intervals of
>> + enabled ports in the serial input stream. The enabled ports must
>> + match the hardware configuration in order for signals to be
>> + properly written/read to/from the controller holding
>> + registers. Being tuples, then number of arguments must be
>> + even. The tuples mast be ordered (low, high) and are
>> + inclusive. Arguments must be between 0 and 31.
>> + $ref: /schemas/types.yaml#/definitions/uint32-array
>> + minItems: 2
>> + maxItems: 64
>> +
>> + microchip,sgpio-frequency:
>> + description: The sgpio controller frequency (Hz). This dictates
>> + the serial bitstream speed, which again affects the latency in
>> + getting control signals back and forth between external shift
>> + registers. The speed must be no larger than half the system
>> + clock, and larger than zero.
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + minimum: 1
>> + default: 12500000
>> +
>> +patternProperties:
>> + "^gpio-(port|controller)@[01]$":
>
> gpio@... is correct here as the node is a gpio-controller (no, we're
> not consistent).
OK, fine by me.
>
>> + type: object
>> + properties:
>> + compatible:
>> + const: microchip,sparx5-sgpio-bank
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + gpio-controller: true
>> +
>> + '#gpio-cells':
>> + const: 3
>> +
>> + ngpios:
>> + minimum: 1
>> + maximum: 128
>> +
>> + required:
>> + - compatible
>> + - reg
>> + - gpio-controller
>> + - '#gpio-cells'
>> + - ngpios
>> +
>> + additionalProperties: false
>> +
>> +additionalProperties: false
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - microchip,sgpio-port-ranges
>> + - "#address-cells"
>> + - "#size-cells"
>> +
>> +examples:
>> + - |
>> + sgpio2: gpio@1101059c {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "microchip,sparx5-sgpio";
>> + clocks = <&sys_clk>;
>> + pinctrl-0 = <&sgpio2_pins>;
>> + pinctrl-names = "default";
>> + reg = <0x1101059c 0x100>;
>> + microchip,sgpio-port-ranges = <0 0 16 18 28 31>;
>
> Since it's tuples, do:
>
> <0 0>, <16 18>, <28 31>
Yes, that will add clarity.
>
>> + microchip,sgpio-frequency = <25000000>;
>
> Some whitespace issues here.
>
Will fix that.
>
>> + sgpio_in2: gpio-controller@0 {
>> + reg = <0>;
>> + compatible = "microchip,sparx5-sgpio-bank";
>> + gpio-controller;
>> + #gpio-cells = <3>;
>> + ngpios = <96>;
>> + };
>> + sgpio_out2: gpio-controller@1 {
>> + compatible = "microchip,sparx5-sgpio-bank";
>> + reg = <1>;
>> + gpio-controller;
>> + #gpio-cells = <3>;
>> + ngpios = <96>;
>> + };
>> + };
>> --
>> 2.25.1
Thank you for your comments, I will refresh the series shortly.
---Lars
--
Lars Povlsen,
Microchip