Add QSPI controller support for Intel LGM SoC.
Note from Vignesh(mtd subsystem maintainer):
This series is a subset of "[PATCH v12 0/4] spi: cadence-quadspi: Add
support for the Cadence QSPI controller" by Ramuthevar,Vadivel MuruganX
<[email protected]> that intended to move
cadence-quadspi driver to spi-mem framework
Those patches were trying to accomplish too many things in a single set
of patches and need to split into smaller patches. This is reduced
version of above series.
Changes that are intended to make migration easy are split into separate
patches. Patches 1 to 3 drop features that cannot be supported under
spi-mem at the moment (backward compatibility is maintained).
Patch 4-5 are trivial cleanups. Patch 6 does the actual conversion to
spi-mem and patch 7 moves the driver to drivers/spi folder.
I have tested both INDAC mode (used by non TI platforms like Altera
SoCFPGA) and DAC mode (used by TI platforms) on TI EVMs.
Patches to move move bindings over to
"Documentation/devicetree/bindings/spi/" directory and also conversion
of bindig doc to YAML will be posted separately. Support for Intel
platform would follow that.
Reference:
https://lkml.org/lkml/2020/6/1/50
Ramuthevar Vadivel Murugan (6):
spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi
dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml
dt-bindings: spi: Add compatible for Intel LGM SoC
spi: cadence-quadspi: Add QSPI support for Intel LGM SoC
spi: cadence-quadspi: Disable the DAC for Intel LGM SoC
spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC
.../devicetree/bindings/mtd/cadence-quadspi.txt | 67 ---------
.../devicetree/bindings/spi/cadence-quadspi.yaml | 149 +++++++++++++++++++++
drivers/spi/Kconfig | 2 +-
drivers/spi/spi-cadence-quadspi.c | 29 ++++
4 files changed, 179 insertions(+), 68 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
create mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
--
2.11.0
From: Ramuthevar Vadivel Murugan <[email protected]>
Add multiple chipselect support for Intel LGM SoCs,
currently QSPI-NOR and QSPI-NAND supported.
Signed-off-by: Ramuthevar Vadivel Murugan <[email protected]>
---
drivers/spi/spi-cadence-quadspi.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 3d017b484114..3bf6d3697631 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -38,6 +38,7 @@
/* Capabilities */
#define CQSPI_SUPPORTS_OCTAL BIT(0)
+#define CQSPI_SUPPORTS_MULTI_CHIPSELECT BIT(1)
struct cqspi_st;
@@ -75,6 +76,7 @@ struct cqspi_st {
bool is_decoded_cs;
u32 fifo_depth;
u32 fifo_width;
+ u32 num_chipselect;
bool rclk_en;
u32 trigger_address;
u32 wr_delay;
@@ -1070,6 +1072,14 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
return -ENXIO;
}
+ if (!cqspi->use_direct_mode) {
+ if (of_property_read_u32(np, "num-chipselect",
+ &cqspi->num_chipselect)) {
+ dev_err(dev, "couldn't determine number of cs\n");
+ return -ENXIO;
+ }
+ }
+
cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
return 0;
@@ -1307,6 +1317,9 @@ static int cqspi_probe(struct platform_device *pdev)
cqspi->current_cs = -1;
cqspi->sclk = 0;
+ if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT)
+ master->num_chipselect = cqspi->num_chipselect;
+
ret = cqspi_setup_flash(cqspi);
if (ret) {
dev_err(dev, "failed to setup flash parameters %d\n", ret);
@@ -1396,6 +1409,7 @@ static const struct cqspi_driver_platdata am654_ospi = {
};
static const struct cqspi_driver_platdata intel_lgm_qspi = {
+ .hwcaps_mask = CQSPI_SUPPORTS_MULTI_CHIPSELECT,
.quirks = CQSPI_DISABLE_DAC_MODE,
};
--
2.11.0
From: Ramuthevar Vadivel Murugan <[email protected]>
Add QSPI controller support for Intel LGM SoC.
Signed-off-by: Ramuthevar Vadivel Murugan <[email protected]>
---
drivers/spi/Kconfig | 2 +-
drivers/spi/spi-cadence-quadspi.c | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index d2c976e55b8b..926da61eee5a 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -203,7 +203,7 @@ config SPI_CADENCE
config SPI_CADENCE_QUADSPI
tristate "Cadence Quad SPI controller"
- depends on OF && (ARM || ARM64 || COMPILE_TEST)
+ depends on OF && (ARM || ARM64 || X86 || COMPILE_TEST)
help
Enable support for the Cadence Quad SPI Flash controller.
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 40938cf3806d..d7b10c46fa70 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1401,6 +1401,9 @@ static const struct of_device_id cqspi_dt_ids[] = {
.compatible = "ti,am654-ospi",
.data = &am654_ospi,
},
+ {
+ .compatible = "intel,lgm-qspi",
+ },
{ /* end of table */ }
};
--
2.11.0
On Fri, Oct 16, 2020 at 05:31:36PM +0800, Ramuthevar,Vadivel MuruganX wrote:
> + depends on OF && (ARM || ARM64 || X86 || COMPILE_TEST)
> + {
> + .compatible = "intel,lgm-qspi",
> + },
This is an x86 SoC (or SoC series) - is it really going to use DT for
the firmware interfaces? It's not specifically a problem, just
surprising to see something other than ACPI. Or is the intention to use
PRP0001? There's a new comaptible here which wasn't really the use case
for PRP0001. Like I say not really a problem, just curious.
Hi Mark,
On 17/10/2020 12:33 am, Mark Brown wrote:
> On Fri, Oct 16, 2020 at 05:31:36PM +0800, Ramuthevar,Vadivel MuruganX wrote:
>
>> + depends on OF && (ARM || ARM64 || X86 || COMPILE_TEST)
>
>> + {
>> + .compatible = "intel,lgm-qspi",
>> + },
>
> This is an x86 SoC (or SoC series) - is it really going to use DT for
> the firmware interfaces?
Thank you for the review comments...
Intel LGM SoC does uses DT based firmware blob.
It's not specifically a problem, just
> surprising to see something other than ACPI. Or is the intention to use
> PRP0001?
Yes, You're right most of them uses ACPI based, but LGM SoC doesn't.
Regards
Vadivel
There's a new comaptible here which wasn't really the use case
> for PRP0001. Like I say not really a problem, just curious.
>