Hello,
Ocelot SoC belongs to a larger family of SoCs which use the same
interrupt controller with a few variation.
This series of patches add support for Luton, Serval and Jaguar2, they
are all MIPS based.
The first patches of the series also updates the binding documentation
with the new compatible strings.
Gregory
Changelog:
v2 -> v3
- Fix new-line-at-end-of-file error in the yaml file
v1 -> v2:
- Convert the binding to yaml
- Squashed the patches adding new binding in a single one
Gregory CLEMENT (5):
dt-bindings: interrupt-controller: convert icpu intr bindings to
json-schema
dt-bindings: interrupt-controller: Add binding for few Microsemi
interrupt controllers
irqchip: ocelot: Add support for Luton platforms
irqchip: ocelot: Add support for Serval platforms
irqchip: ocelot: Add support for Jaguar2 platforms
.../mscc,ocelot-icpu-intr.txt | 21 --
.../mscc,ocelot-icpu-intr.yaml | 63 ++++++
drivers/irqchip/irq-mscc-ocelot.c | 183 ++++++++++++++++--
3 files changed, 225 insertions(+), 42 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
--
2.29.2
Convert device tree bindings for Microsemi Ocelot SoC ICPU Interrupt
Controller to YAML format
Signed-off-by: Gregory CLEMENT <[email protected]>
---
.../mscc,ocelot-icpu-intr.txt | 21 -------
.../mscc,ocelot-icpu-intr.yaml | 59 +++++++++++++++++++
2 files changed, 59 insertions(+), 21 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
deleted file mode 100644
index f5baeccb689f..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-Microsemi Ocelot SoC ICPU Interrupt Controller
-
-Required properties:
-
-- compatible : should be "mscc,ocelot-icpu-intr"
-- reg : Specifies base physical address and size of the registers.
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
- interrupt source. The value shall be 1.
-- interrupts : Specifies the CPU interrupt the controller is connected to.
-
-Example:
-
- intc: interrupt-controller@70000070 {
- compatible = "mscc,ocelot-icpu-intr";
- reg = <0x70000070 0x70>;
- #interrupt-cells = <1>;
- interrupt-controller;
- interrupt-parent = <&cpuintc>;
- interrupts = <2>;
- };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
new file mode 100644
index 000000000000..3a537635a859
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Microsemi Ocelot SoC ICPU Interrupt Controller
+
+maintainers:
+ - Alexandre Belloni <[email protected]>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+description: |
+ the Microsemi Ocelot interrupt controller that is part of the
+ ICPU. It is connected directly to the MIPS core interrupt
+ controller.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mscc,ocelot-icpu-intr
+
+ '#interrupt-cells':
+ const: 1
+
+ '#address-cells':
+ const: 0
+
+ interrupt-controller: true
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - '#interrupt-cells'
+ - '#address-cells'
+ - interrupt-controller
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ intc: interrupt-controller@70000070 {
+ compatible = "mscc,ocelot-icpu-intr";
+ reg = <0x70000070 0x70>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+...
--
2.29.2
Add the Device Tree binding documentation for the Microsemi Jaguar2,
Luton and Serval interrupt controller that is part of the ICPU. It is
connected directly to the MIPS core interrupt controller.
Signed-off-by: Gregory CLEMENT <[email protected]>
---
.../bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
index 3a537635a859..5483ed7062ba 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
@@ -21,7 +21,11 @@ properties:
compatible:
items:
- enum:
+ - mscc,jaguar2-icpu-intr
+ - mscc,luton-icpu-intr
- mscc,ocelot-icpu-intr
+ - mscc,serval-icpu-intr
+
'#interrupt-cells':
const: 1
--
2.29.2
Hello,
On 16/11/2020 17:24:24+0100, Gregory CLEMENT wrote:
> Add the Device Tree binding documentation for the Microsemi Jaguar2,
> Luton and Serval interrupt controller that is part of the ICPU. It is
> connected directly to the MIPS core interrupt controller.
>
> Signed-off-by: Gregory CLEMENT <[email protected]>
> ---
> .../bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
> index 3a537635a859..5483ed7062ba 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
> @@ -21,7 +21,11 @@ properties:
> compatible:
> items:
> - enum:
> + - mscc,jaguar2-icpu-intr
> + - mscc,luton-icpu-intr
> - mscc,ocelot-icpu-intr
> + - mscc,serval-icpu-intr
> +
Spurious blank line
>
> '#interrupt-cells':
> const: 1
> --
> 2.29.2
>
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
On Mon, 16 Nov 2020 17:24:23 +0100, Gregory CLEMENT wrote:
> Convert device tree bindings for Microsemi Ocelot SoC ICPU Interrupt
> Controller to YAML format
>
> Signed-off-by: Gregory CLEMENT <[email protected]>
> ---
> .../mscc,ocelot-icpu-intr.txt | 21 -------
> .../mscc,ocelot-icpu-intr.yaml | 59 +++++++++++++++++++
> 2 files changed, 59 insertions(+), 21 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.example.dt.yaml: interrupt-controller@70000070: '#address-cells' is a required property
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
See https://patchwork.ozlabs.org/patch/1401029
The base for the patch is generally the last rc1. Any dependencies
should be noted.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.