Hello,
This series first adds new feature to the ocelot reset driver and then
it extends its support for 2 other MIPS based SoCs: Luton and Jaguar 2.
Patches 1, 2 and 4 should be merged through the reset subsystem, while
the device tree changes in patches 3 and 5 should go through the mips
subsystem.
Gregory
Gregory CLEMENT (3):
MIPS: dts: mscc: add reset switch property
power: reset: ocelot: Add support 2 othe MIPS based SoCs
MIPS: dts: mscc: add reset support for Luton and Jaguar2
Lars Povlsen (2):
dt-bindings: reset: ocelot: Add documentation for
'microchip,reset-switch-core' property
power: reset: ocelot: Add support for reset switch on load time
.../bindings/power/reset/ocelot-reset.txt | 6 ++
arch/mips/boot/dts/mscc/jaguar2.dtsi | 6 ++
arch/mips/boot/dts/mscc/luton.dtsi | 5 ++
arch/mips/boot/dts/mscc/ocelot.dtsi | 1 +
drivers/power/reset/ocelot-reset.c | 70 +++++++++++++++++--
5 files changed, 83 insertions(+), 5 deletions(-)
--
2.29.2
From: Lars Povlsen <[email protected]>
This patch add support for resetting the networking switch core at
reset driver load time. It is useful in order to bring the switch core
in a known state after a reboot or after a bootloader may have been
using the switch for network access.
Signed-off-by: Lars Povlsen <[email protected]>
---
drivers/power/reset/ocelot-reset.c | 40 ++++++++++++++++++++++++++++--
1 file changed, 38 insertions(+), 2 deletions(-)
diff --git a/drivers/power/reset/ocelot-reset.c b/drivers/power/reset/ocelot-reset.c
index f74e1dbb4ba3..a203c42e99d4 100644
--- a/drivers/power/reset/ocelot-reset.c
+++ b/drivers/power/reset/ocelot-reset.c
@@ -29,6 +29,7 @@ struct ocelot_reset_context {
struct notifier_block restart_handler;
};
+#define SOFT_SWC_RST BIT(1)
#define SOFT_CHIP_RST BIT(0)
#define ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
@@ -37,6 +38,32 @@ struct ocelot_reset_context {
#define IF_SI_OWNER_SIBM 1
#define IF_SI_OWNER_SIMC 2
+static int ocelot_switch_core_reset(const struct ocelot_reset_context *ctx)
+{
+
+ const char *driver = "ocelot-reset";
+ int timeout;
+
+ pr_notice("%s: Resetting Switch Core\n", driver);
+
+ /* Make sure the core is PROTECTED from reset */
+ regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg,
+ ctx->props->vcore_protect,
+ ctx->props->vcore_protect);
+
+ writel(SOFT_SWC_RST, ctx->base);
+ for (timeout = 0; timeout < 100; timeout++) {
+ if ((readl(ctx->base) & SOFT_SWC_RST) == 0) {
+ pr_debug("%s: Switch Core Reset complete.\n", driver);
+ return 0;
+ }
+ udelay(1);
+ }
+
+ pr_warn("%s: Switch Core Reset timeout!\n", driver);
+ return -ENXIO;
+}
+
static int ocelot_restart_handle(struct notifier_block *this,
unsigned long mode, void *cmd)
{
@@ -66,7 +93,6 @@ static int ocelot_reset_probe(struct platform_device *pdev)
{
struct ocelot_reset_context *ctx;
struct resource *res;
-
struct device *dev = &pdev->dev;
int err;
@@ -87,6 +113,11 @@ static int ocelot_reset_probe(struct platform_device *pdev)
return PTR_ERR(ctx->cpu_ctrl);
}
+ /* Optionally, call switch reset function */
+ if (of_property_read_bool(pdev->dev.of_node,
+ "microchip,reset-switch-core"))
+ ocelot_switch_core_reset(ctx);
+
ctx->restart_handler.notifier_call = ocelot_restart_handle;
ctx->restart_handler.priority = 192;
err = register_restart_handler(&ctx->restart_handler);
@@ -128,4 +159,9 @@ static struct platform_driver ocelot_reset_driver = {
.of_match_table = ocelot_reset_of_match,
},
};
-builtin_platform_driver(ocelot_reset_driver);
+
+static int __init reset_init(void)
+{
+ return platform_driver_register(&ocelot_reset_driver);
+}
+postcore_initcall(reset_init);
--
2.29.2
This adds reset support for Luton and Jaguar2 in the ocelot-reset
driver. They are both MIPS based belonging to the VvoreIII family.
Signed-off-by: Gregory CLEMENT <[email protected]>
---
drivers/power/reset/ocelot-reset.c | 30 +++++++++++++++++++++++++++---
1 file changed, 27 insertions(+), 3 deletions(-)
diff --git a/drivers/power/reset/ocelot-reset.c b/drivers/power/reset/ocelot-reset.c
index a203c42e99d4..0f92416f2907 100644
--- a/drivers/power/reset/ocelot-reset.c
+++ b/drivers/power/reset/ocelot-reset.c
@@ -29,6 +29,8 @@ struct ocelot_reset_context {
struct notifier_block restart_handler;
};
+#define BIT_OFF_INVALID 32
+
#define SOFT_SWC_RST BIT(1)
#define SOFT_CHIP_RST BIT(0)
@@ -77,9 +79,11 @@ static int ocelot_restart_handle(struct notifier_block *this,
ctx->props->vcore_protect, 0);
/* Make the SI back to boot mode */
- regmap_update_bits(ctx->cpu_ctrl, ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL,
- IF_SI_OWNER_MASK << if_si_owner_bit,
- IF_SI_OWNER_SIBM << if_si_owner_bit);
+ if (if_si_owner_bit != BIT_OFF_INVALID)
+ regmap_update_bits(ctx->cpu_ctrl,
+ ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL,
+ IF_SI_OWNER_MASK << if_si_owner_bit,
+ IF_SI_OWNER_SIBM << if_si_owner_bit);
pr_emerg("Resetting SoC\n");
@@ -127,6 +131,20 @@ static int ocelot_reset_probe(struct platform_device *pdev)
return err;
}
+static const struct reset_props reset_props_jaguar2 = {
+ .syscon = "mscc,ocelot-cpu-syscon",
+ .protect_reg = 0x20,
+ .vcore_protect = BIT(2),
+ .if_si_owner_bit = 6,
+};
+
+static const struct reset_props reset_props_luton = {
+ .syscon = "mscc,ocelot-cpu-syscon",
+ .protect_reg = 0x20,
+ .vcore_protect = BIT(2),
+ .if_si_owner_bit = BIT_OFF_INVALID, /* n/a */
+};
+
static const struct reset_props reset_props_ocelot = {
.syscon = "mscc,ocelot-cpu-syscon",
.protect_reg = 0x20,
@@ -143,6 +161,12 @@ static const struct reset_props reset_props_sparx5 = {
static const struct of_device_id ocelot_reset_of_match[] = {
{
+ .compatible = "mscc,jaguar2-chip-reset",
+ .data = &reset_props_jaguar2
+ }, {
+ .compatible = "mscc,luton-chip-reset",
+ .data = &reset_props_luton
+ }, {
.compatible = "mscc,ocelot-chip-reset",
.data = &reset_props_ocelot
}, {
--
2.29.2
Allow Luton and Jaguar2 SoC to use reset feature by adding the reset
node.
Signed-off-by: Gregory CLEMENT <[email protected]>
---
arch/mips/boot/dts/mscc/jaguar2.dtsi | 6 ++++++
arch/mips/boot/dts/mscc/luton.dtsi | 5 +++++
2 files changed, 11 insertions(+)
diff --git a/arch/mips/boot/dts/mscc/jaguar2.dtsi b/arch/mips/boot/dts/mscc/jaguar2.dtsi
index 42b2b0a51ddc..f5f7b81c4044 100644
--- a/arch/mips/boot/dts/mscc/jaguar2.dtsi
+++ b/arch/mips/boot/dts/mscc/jaguar2.dtsi
@@ -60,6 +60,12 @@ cpu_ctrl: syscon@70000000 {
reg = <0x70000000 0x2c>;
};
+ reset@71010008 {
+ compatible = "mscc,luton-chip-reset";
+ reg = <0x71010008 0x4>;
+ microchip,reset-switch-core;
+ };
+
intc: interrupt-controller@70000070 {
compatible = "mscc,jaguar2-icpu-intr";
reg = <0x70000070 0x94>;
diff --git a/arch/mips/boot/dts/mscc/luton.dtsi b/arch/mips/boot/dts/mscc/luton.dtsi
index 2a170b84c5a9..4a26c2874386 100644
--- a/arch/mips/boot/dts/mscc/luton.dtsi
+++ b/arch/mips/boot/dts/mscc/luton.dtsi
@@ -56,6 +56,11 @@ cpu_ctrl: syscon@10000000 {
reg = <0x10000000 0x2c>;
};
+ reset@00070090 {
+ compatible = "mscc,luton-chip-reset";
+ reg = <0x70090 0x4>;
+ };
+
intc: interrupt-controller@10000084 {
compatible = "mscc,luton-icpu-intr";
reg = <0x10000084 0x70>;
--
2.29.2
Hi,
On 16/11/2020 18:11:58+0100, Gregory CLEMENT wrote:
> This adds reset support for Luton and Jaguar2 in the ocelot-reset
> driver. They are both MIPS based belonging to the VvoreIII family.
>
> Signed-off-by: Gregory CLEMENT <[email protected]>
> ---
> drivers/power/reset/ocelot-reset.c | 30 +++++++++++++++++++++++++++---
> 1 file changed, 27 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/power/reset/ocelot-reset.c b/drivers/power/reset/ocelot-reset.c
> index a203c42e99d4..0f92416f2907 100644
> --- a/drivers/power/reset/ocelot-reset.c
> +++ b/drivers/power/reset/ocelot-reset.c
> @@ -29,6 +29,8 @@ struct ocelot_reset_context {
> struct notifier_block restart_handler;
> };
>
> +#define BIT_OFF_INVALID 32
> +
> #define SOFT_SWC_RST BIT(1)
> #define SOFT_CHIP_RST BIT(0)
>
> @@ -77,9 +79,11 @@ static int ocelot_restart_handle(struct notifier_block *this,
> ctx->props->vcore_protect, 0);
>
> /* Make the SI back to boot mode */
> - regmap_update_bits(ctx->cpu_ctrl, ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL,
> - IF_SI_OWNER_MASK << if_si_owner_bit,
> - IF_SI_OWNER_SIBM << if_si_owner_bit);
> + if (if_si_owner_bit != BIT_OFF_INVALID)
> + regmap_update_bits(ctx->cpu_ctrl,
> + ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL,
> + IF_SI_OWNER_MASK << if_si_owner_bit,
> + IF_SI_OWNER_SIBM << if_si_owner_bit);
>
> pr_emerg("Resetting SoC\n");
>
> @@ -127,6 +131,20 @@ static int ocelot_reset_probe(struct platform_device *pdev)
> return err;
> }
>
> +static const struct reset_props reset_props_jaguar2 = {
> + .syscon = "mscc,ocelot-cpu-syscon",
> + .protect_reg = 0x20,
> + .vcore_protect = BIT(2),
> + .if_si_owner_bit = 6,
> +};
> +
> +static const struct reset_props reset_props_luton = {
> + .syscon = "mscc,ocelot-cpu-syscon",
> + .protect_reg = 0x20,
> + .vcore_protect = BIT(2),
> + .if_si_owner_bit = BIT_OFF_INVALID, /* n/a */
> +};
> +
> static const struct reset_props reset_props_ocelot = {
> .syscon = "mscc,ocelot-cpu-syscon",
> .protect_reg = 0x20,
> @@ -143,6 +161,12 @@ static const struct reset_props reset_props_sparx5 = {
>
> static const struct of_device_id ocelot_reset_of_match[] = {
> {
> + .compatible = "mscc,jaguar2-chip-reset",
> + .data = &reset_props_jaguar2
> + }, {
> + .compatible = "mscc,luton-chip-reset",
> + .data = &reset_props_luton
> + }, {
These compatible strings are undocumented. Else,
Acked-by: Alexandre Belloni <[email protected]>
> .compatible = "mscc,ocelot-chip-reset",
> .data = &reset_props_ocelot
> }, {
> --
> 2.29.2
>
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com