This patch adds YAML based device tree binding document for Tegra
Quad SPI driver.
Signed-off-by: Sowjanya Komatineni <[email protected]>
---
.../bindings/spi/nvidia,tegra210-quad.yaml | 130 +++++++++++++++++++++
1 file changed, 130 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
new file mode 100644
index 0000000..0b5fea6
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tegra Quad SPI Controller
+
+maintainers:
+ - Thierry Reding <[email protected]>
+ - Jonathan Hunter <[email protected]>
+
+properties:
+ compatible:
+ enum:
+ - nvidia,tegra210-qspi
+ - nvidia,tegra186-qspi
+ - nvidia,tegra194-qspi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: qspi
+ - const: qspi_out
+
+ clocks:
+ maxItems: 2
+
+ resets:
+ maxItems: 1
+
+ dmas:
+ maxItems: 2
+
+ dma-names:
+ items:
+ - const: rx
+ - const: tx
+
+patternProperties:
+ "^.*@[0-9a-f]+":
+ type: object
+
+ properties:
+ compatible:
+ description:
+ Compatible of the SPI device.
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Maximum Quad SPI clocking speed of the device in Hz.
+
+ spi-rx-bus-width:
+ description:
+ Bus width to the Quad SPI bus used for read transfers.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2, 4]
+
+ spi-tx-bus-width:
+ description:
+ Bus width to the Quad SPI bus used for write transfers.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2, 4]
+
+ nvidia,tx-clk-tap-delay:
+ description:
+ Delays the clock going out to device with this tap value.
+ Tap value varies based on platform design trace lengths from Tegra
+ QSPI to corresponding slave device.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 31
+
+ nvidia,rx-clk-tap-delay:
+ description:
+ Delays the clock coming in from the device with this tap value.
+ Tap value varies based on platform design trace lengths from Tegra
+ QSPI to corresponding slave device.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 255
+
+ required:
+ - reg
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clock-names
+ - clocks
+ - resets
+
+additionalProperties: true
+
+examples:
+ - |
+ #include <dt-bindings/clock/tegra210-car.h>
+ #include <dt-bindings/reset/tegra210-car.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ spi@70410000 {
+ compatible = "nvidia,tegra210-qspi";
+ reg = <0x70410000 0x1000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA210_CLK_QSPI>,
+ <&tegra_car TEGRA210_CLK_QSPI_PM>;
+ clock-names = "qspi", "qspi_out";
+ resets = <&tegra_car 211>;
+ dmas = <&apbdma 5>, <&apbdma 5>;
+ dma-names = "rx", "tx";
+
+ flash@0 {
+ compatible = "spi-nor";
+ reg = <0>;
+ spi-max-frequency = <104000000>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ };
+ };
--
2.7.4
On Fri, Dec 11, 2020 at 01:15:56PM -0800, Sowjanya Komatineni wrote:
> This patch adds YAML based device tree binding document for Tegra
> Quad SPI driver.
>
> Signed-off-by: Sowjanya Komatineni <[email protected]>
> ---
> .../bindings/spi/nvidia,tegra210-quad.yaml | 130 +++++++++++++++++++++
> 1 file changed, 130 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
>
> diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
> new file mode 100644
> index 0000000..0b5fea6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
> @@ -0,0 +1,130 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Tegra Quad SPI Controller
> +
> +maintainers:
> + - Thierry Reding <[email protected]>
> + - Jonathan Hunter <[email protected]>
allOf:
- $ref: spi-controller.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - nvidia,tegra210-qspi
> + - nvidia,tegra186-qspi
> + - nvidia,tegra194-qspi
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clock-names:
> + items:
> + - const: qspi
> + - const: qspi_out
> +
> + clocks:
> + maxItems: 2
> +
> + resets:
> + maxItems: 1
> +
> + dmas:
> + maxItems: 2
> +
> + dma-names:
> + items:
> + - const: rx
> + - const: tx
> +
> +patternProperties:
> + "^.*@[0-9a-f]+":
You can drop '^.*'.
> + type: object
> +
> + properties:
> + compatible:
> + description:
> + Compatible of the SPI device.
> +
> + reg:
> + maxItems: 1
> +
> + spi-max-frequency:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Maximum Quad SPI clocking speed of the device in Hz.
> +
> + spi-rx-bus-width:
> + description:
> + Bus width to the Quad SPI bus used for read transfers.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [1, 2, 4]
> +
> + spi-tx-bus-width:
> + description:
> + Bus width to the Quad SPI bus used for write transfers.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [1, 2, 4]
All of the above 5 properties are covered by spi-controller.yaml. You
only need additional constraints here. As 8-bit mode is not supported,
you need:
spi-tx-bus-width:
enum: [1, 2, 4]
> +
> + nvidia,tx-clk-tap-delay:
> + description:
> + Delays the clock going out to device with this tap value.
> + Tap value varies based on platform design trace lengths from Tegra
> + QSPI to corresponding slave device.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 31
> +
> + nvidia,rx-clk-tap-delay:
> + description:
> + Delays the clock coming in from the device with this tap value.
> + Tap value varies based on platform design trace lengths from Tegra
> + QSPI to corresponding slave device.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 255
Please include these properties in your example.
> +
> + required:
> + - reg
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clock-names
> + - clocks
> + - resets
> +
> +additionalProperties: true
That's generally wrong unless it's a schema to be included by other
schemas.
unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/tegra210-car.h>
> + #include <dt-bindings/reset/tegra210-car.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + spi@70410000 {
> + compatible = "nvidia,tegra210-qspi";
> + reg = <0x70410000 0x1000>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&tegra_car TEGRA210_CLK_QSPI>,
> + <&tegra_car TEGRA210_CLK_QSPI_PM>;
> + clock-names = "qspi", "qspi_out";
> + resets = <&tegra_car 211>;
> + dmas = <&apbdma 5>, <&apbdma 5>;
> + dma-names = "rx", "tx";
> +
> + flash@0 {
> + compatible = "spi-nor";
> + reg = <0>;
> + spi-max-frequency = <104000000>;
> + spi-tx-bus-width = <2>;
> + spi-rx-bus-width = <2>;
> + };
> + };
> --
> 2.7.4
>