MT8195 is a SoC based on 64bit ARMv8 architecture.
It contains 4 CA55 and 4 CA78 cores.
MT8195 share many HW IP with MT65xx series.
This patchset was tested on MT8195 evaluation board to shell.
Based on next-20210318
Changes in v2
Fix make dt_binding_check warning in mediatek,ufs-phy.yaml
Update usb phy and ufs phy nodes in mt8195.dtsi
Seiya Wang (8):
dt-bindings: timer: Add compatible for Mediatek MT8195
dt-bindings: serial: Add compatible for Mediatek MT8195
dt-bindings: watchdog: Add compatible for Mediatek MT8195
dt-bindings: mmc: Add compatible for Mediatek MT8195
dt-bindings: iio: adc: Add compatible for Mediatek MT8195
dt-bindings: arm: Add compatible for Mediatek MT8195
dt-bindings: phy: fix dt_binding_check warning in
mediatek,ufs-phy.yaml
arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and
Makefile
.../devicetree/bindings/arm/mediatek.yaml | 4 +
.../bindings/iio/adc/mediatek,mt2701-auxadc.yaml | 1 +
Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 1 +
.../devicetree/bindings/phy/mediatek,ufs-phy.yaml | 8 +-
.../devicetree/bindings/serial/mtk-uart.txt | 1 +
.../bindings/timer/mediatek,mtk-timer.txt | 1 +
.../devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 29 ++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 464 +++++++++++++++++++++
10 files changed, 509 insertions(+), 2 deletions(-)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8195.dtsi
--
2.14.1
This commit adds dt-binding documentation of timer for Mediatek MT8195 SoC
Platform.
Signed-off-by: Seiya Wang <[email protected]>
---
Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
index 690a9c0966ac..e5c57d6e0186 100644
--- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
+++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
@@ -23,6 +23,7 @@ Required properties:
For those SoCs that use SYST
* "mediatek,mt8183-timer" for MT8183 compatible timers (SYST)
* "mediatek,mt8192-timer" for MT8192 compatible timers (SYST)
+ * "mediatek,mt8195-timer" for MT8195 compatible timers (SYST)
* "mediatek,mt7629-timer" for MT7629 compatible timers (SYST)
* "mediatek,mt6765-timer" for MT6765 and all above compatible timers (SYST)
--
2.14.1
This commit adds dt-binding documentation of uart for Mediatek MT8195 SoC
Platform.
Signed-off-by: Seiya Wang <[email protected]>
---
Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index 647b5aee86f3..64c4fb59acd1 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -20,6 +20,7 @@ Required properties:
* "mediatek,mt8173-uart" for MT8173 compatible UARTS
* "mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS
* "mediatek,mt8192-uart", "mediatek,mt6577-uart" for MT8192 compatible UARTS
+ * "mediatek,mt8195-uart", "mediatek,mt6577-uart" for MT8195 compatible UARTS
* "mediatek,mt8516-uart" for MT8516 compatible UARTS
* "mediatek,mt6577-uart" for MT6577 and all of the above
--
2.14.1
This commit adds dt-binding documentation of mmc for Mediatek MT8195 SoC
Platform.
Signed-off-by: Seiya Wang <[email protected]>
---
Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
index 01630b0ecea7..8648d48dbbfd 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
@@ -31,6 +31,7 @@ properties:
- const: mediatek,mt2701-mmc
- items:
- const: mediatek,mt8192-mmc
+ - const: mediatek,mt8195-mmc
- const: mediatek,mt8183-mmc
clocks:
--
2.14.1
This commit adds dt-binding documentation of auxadc for Mediatek MT8195 SoC
Platform.
Signed-off-by: Seiya Wang <[email protected]>
---
Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml
index 5b21a9fba5dd..b939f9652e3a 100644
--- a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml
@@ -34,6 +34,7 @@ properties:
- items:
- enum:
- mediatek,mt8183-auxadc
+ - mediatek,mt8195-auxadc
- mediatek,mt8516-auxadc
- const: mediatek,mt8173-auxadc
--
2.14.1
This commit adds dt-binding documentation for the Mediatek MT8195
reference board.
Signed-off-by: Seiya Wang <[email protected]>
---
Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index 93b3bdf6eaeb..a95224fcff9f 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -118,6 +118,10 @@ properties:
- enum:
- mediatek,mt8183-evb
- const: mediatek,mt8183
+ - items:
+ - enum:
+ - mediatek,mt8195-evb
+ - const: mediatek,mt8195
- description: Google Krane (Lenovo IdeaPad Duet, 10e,...)
items:
- enum:
--
2.14.1
This commit fixes the warning messages of make dt_binding_check from
newly added mediatek,mt8195-ufsphy in mediatek,ufs-phy.yaml
Signed-off-by: Seiya Wang <[email protected]>
---
Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
index 5235b1a0d188..74cc32c1d2e8 100644
--- a/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
@@ -22,8 +22,12 @@ properties:
pattern: "^ufs-phy@[0-9a-f]+$"
compatible:
- enum: mediatek,mt8195-ufsphy
- const: mediatek,mt8183-ufsphy
+ oneOf:
+ - items:
+ - enum:
+ - mediatek,mt8195-ufsphy
+ - const: mediatek,mt8183-ufsphy
+ - const: mediatek,mt8183-ufsphy
reg:
maxItems: 1
--
2.14.1
Add basic chip support for Mediatek MT8195
Signed-off-by: Seiya Wang <[email protected]>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 29 ++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 464 ++++++++++++++++++++++++++++
3 files changed, 494 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8195.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index deba27ab7657..aee4b9715d2f 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -16,4 +16,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
new file mode 100644
index 000000000000..82bb10e9a531
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ * Author: Seiya Wang <[email protected]>
+ */
+/dts-v1/;
+#include "mt8195.dtsi"
+
+/ {
+ model = "MediaTek MT8195 evaluation board";
+ compatible = "mediatek,mt8195-evb", "mediatek,mt8195";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x80000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
new file mode 100644
index 000000000000..629cd883facf
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -0,0 +1,464 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Seiya Wang <[email protected]>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "mediatek,mt8195";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clocks {
+ clk26m: oscillator0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ clk32k: oscillator1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "clk32k";
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x000>;
+ enable-method = "psci";
+ clock-frequency = <1701000000>;
+ capacity-dmips-mhz = <578>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x100>;
+ enable-method = "psci";
+ clock-frequency = <1701000000>;
+ capacity-dmips-mhz = <578>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x200>;
+ enable-method = "psci";
+ clock-frequency = <1701000000>;
+ capacity-dmips-mhz = <578>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x300>;
+ enable-method = "psci";
+ clock-frequency = <1701000000>;
+ capacity-dmips-mhz = <578>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78", "arm,armv8";
+ reg = <0x400>;
+ enable-method = "psci";
+ clock-frequency = <2171000000>;
+ capacity-dmips-mhz = <1024>;
+ cpu-idle-states = <&cpuoff_b &clusteroff_b>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78", "arm,armv8";
+ reg = <0x500>;
+ enable-method = "psci";
+ clock-frequency = <2171000000>;
+ capacity-dmips-mhz = <1024>;
+ cpu-idle-states = <&cpuoff_b &clusteroff_b>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78", "arm,armv8";
+ reg = <0x600>;
+ enable-method = "psci";
+ clock-frequency = <2171000000>;
+ capacity-dmips-mhz = <1024>;
+ cpu-idle-states = <&cpuoff_b &clusteroff_b>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78", "arm,armv8";
+ reg = <0x700>;
+ enable-method = "psci";
+ clock-frequency = <2171000000>;
+ capacity-dmips-mhz = <1024>;
+ cpu-idle-states = <&cpuoff_b &clusteroff_b>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "arm,psci";
+ cpuoff_l: cpuoff_l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010001>;
+ local-timer-stop;
+ entry-latency-us = <50>;
+ exit-latency-us = <95>;
+ min-residency-us = <580>;
+ };
+ cpuoff_b: cpuoff_b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010001>;
+ local-timer-stop;
+ entry-latency-us = <45>;
+ exit-latency-us = <140>;
+ min-residency-us = <740>;
+ };
+ clusteroff_l: clusteroff_l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010002>;
+ local-timer-stop;
+ entry-latency-us = <55>;
+ exit-latency-us = <155>;
+ min-residency-us = <840>;
+ };
+ clusteroff_b: clusteroff_b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010002>;
+ local-timer-stop;
+ entry-latency-us = <50>;
+ exit-latency-us = <200>;
+ min-residency-us = <1000>;
+ };
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ next-level-cache = <&l3_0>;
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ next-level-cache = <&l3_0>;
+ };
+
+ l3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+
+ dsu-pmu {
+ compatible = "arm,dsu-pmu";
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
+ cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
+ <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
+ };
+
+ pmu-a55 {
+ compatible = "arm,cortex-a55-pmu";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
+ };
+
+ pmu-a78 {
+ compatible = "arm,cortex-a78-pmu";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer: timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-frequency = <13000000>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <4>;
+ #redistributor-regions = <1>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x40000>,
+ <0 0x0c040000 0 0x200000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
+ };
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
+ };
+ };
+ };
+
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt8195-wdt", "mediatek,mt6589-wdt";
+ reg = <0 0x10007000 0 0x100>;
+ };
+
+ systimer: timer@10017000 {
+ compatible = "mediatek,mt8195-timer", "mediatek,mt6765-timer";
+ reg = <0 0x10017000 0 0x1000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>;
+ };
+
+ uart0: serial@11001100 {
+ compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11001100 0 0x100>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart1: serial@11001200 {
+ compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11001200 0 0x100>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ };
+
+ uart2: serial@11001300 {
+ compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11001300 0 0x100>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart3: serial@11001400 {
+ compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11001400 0 0x100>;
+ interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart4: serial@11001500 {
+ compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11001500 0 0x100>;
+ interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart5: serial@11001600 {
+ compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11001600 0 0x100>;
+ interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ auxadc: auxadc@11002000 {
+ compatible = "mediatek,mt8195-auxadc", "mediatek,mt8173-auxadc";
+ reg = <0 0x11002000 0 0x1000>;
+ clocks = <&clk26m>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc";
+ reg = <0 0x11230000 0 0x10000>,
+ <0 0x11f50000 0 0x1000>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&clk26m>, <&clk26m>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11240000 {
+ compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc";
+ reg = <0 0x11240000 0 0x1000>,
+ <0 0x11c70000 0 0x1000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&clk26m>, <&clk26m>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ nor_flash: nor@1132c000 {
+ compatible = "mediatek,mt8195-nor", "mediatek,mt8173-nor";
+ reg = <0 0x1132c000 0 0x1000>;
+ interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "spi", "sf";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ u3phy2: t-phy@11c40000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11c40000 0x700>;
+ status = "disabled";
+
+ u2port2: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ u3phy3: t-phy@11c50000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11c50000 0x700>;
+ status = "disabled";
+
+ u2port3: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ u3phy1: t-phy@11e30000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11e30000 0xe00>;
+ status = "disabled";
+
+ u2port1: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+
+ u3port1: usb-phy@700 {
+ reg = <0x700 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ u3phy0: t-phy@11e40000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11e40000 0xe00>;
+ status = "disabled";
+
+ u2port0: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+
+ u3port0: usb-phy@700 {
+ reg = <0x700 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ ufsphy: phy@11fa0000 {
+ compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
+ reg = <0 0x11fa0000 0 0xc000>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "unipro", "mp";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+};
--
2.14.1
This commit adds dt-binding documentation of watchdog for Mediatek MT8195 SoC
Platform.
Signed-off-by: Seiya Wang <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
---
Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index e36ba60de829..a658a0b92b9a 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -13,6 +13,7 @@ Required properties:
"mediatek,mt8183-wdt": for MT8183
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
"mediatek,mt8192-wdt": for MT8192
+ "mediatek,mt8195-wdt", "mediatek,mt6589-wdt": for MT8195
- reg : Specifies base physical address and size of the registers.
--
2.14.1
On Fri, 19 Mar 2021 at 03:36, Seiya Wang <[email protected]> wrote:
>
> This commit adds dt-binding documentation of mmc for Mediatek MT8195 SoC
> Platform.
>
> Signed-off-by: Seiya Wang <[email protected]>
Applied for next, thanks!
Kind regards
Uffe
> ---
> Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> index 01630b0ecea7..8648d48dbbfd 100644
> --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> @@ -31,6 +31,7 @@ properties:
> - const: mediatek,mt2701-mmc
> - items:
> - const: mediatek,mt8192-mmc
> + - const: mediatek,mt8195-mmc
> - const: mediatek,mt8183-mmc
>
> clocks:
> --
> 2.14.1
>
On Fri, 19 Mar 2021 10:34:24 +0800
Seiya Wang <[email protected]> wrote:
> This commit adds dt-binding documentation of auxadc for Mediatek MT8195 SoC
> Platform.
>
> Signed-off-by: Seiya Wang <[email protected]>
Applied to the togreg branch of iio.git and pushed out as testing for
the normal autobuilder fun and games.
Thanks,
Jonathan
> ---
> Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml
> index 5b21a9fba5dd..b939f9652e3a 100644
> --- a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml
> @@ -34,6 +34,7 @@ properties:
> - items:
> - enum:
> - mediatek,mt8183-auxadc
> + - mediatek,mt8195-auxadc
> - mediatek,mt8516-auxadc
> - const: mediatek,mt8173-auxadc
>
On Fri, 2021-03-19 at 10:34 +0800, Seiya Wang wrote:
> Add basic chip support for Mediatek MT8195
>
> Signed-off-by: Seiya Wang <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 29 ++
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 464 ++++++++++++++++++++++++++++
> 3 files changed, 494 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-evb.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8195.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index deba27ab7657..aee4b9715d2f 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -16,4 +16,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
> new file mode 100644
> index 000000000000..82bb10e9a531
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
> @@ -0,0 +1,29 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2021 MediaTek Inc.
> + * Author: Seiya Wang <[email protected]>
> + */
> +/dts-v1/;
> +#include "mt8195.dtsi"
> +
[...]
> + nor_flash: nor@1132c000 {
> + compatible = "mediatek,mt8195-nor", "mediatek,mt8173-nor";
> + reg = <0 0x1132c000 0 0x1000>;
> + interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "spi", "sf";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + u3phy2: t-phy@11c40000 {
> + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0x11c40000 0x700>;
> + status = "disabled";
> +
> + u2port2: usb-phy@0 {
> + reg = <0x0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + };
> + };
> +
> + u3phy3: t-phy@11c50000 {
> + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0x11c50000 0x700>;
> + status = "disabled";
> +
> + u2port3: usb-phy@0 {
> + reg = <0x0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + };
> + };
> +
> + u3phy1: t-phy@11e30000 {
> + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0x11e30000 0xe00>;
> + status = "disabled";
> +
> + u2port1: usb-phy@0 {
> + reg = <0x0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + };
> +
> + u3port1: usb-phy@700 {
> + reg = <0x700 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + };
> + };
> +
> + u3phy0: t-phy@11e40000 {
> + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0x11e40000 0xe00>;
> + status = "disabled";
> +
> + u2port0: usb-phy@0 {
> + reg = <0x0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + };
> +
> + u3port0: usb-phy@700 {
> + reg = <0x700 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + };
> + };
> +
> + ufsphy: phy@11fa0000 {
> + compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
> + reg = <0 0x11fa0000 0 0xc000>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "unipro", "mp";
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> + };
> +};
phy part:
Reviewed-by: Chunfeng Yun <[email protected]>
Thank you
On Fri, 19 Mar 2021 10:34:22 +0800, Seiya Wang wrote:
> This commit adds dt-binding documentation of watchdog for Mediatek MT8195 SoC
> Platform.
>
> Signed-off-by: Seiya Wang <[email protected]>
> Reviewed-by: Guenter Roeck <[email protected]>
> ---
> Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <[email protected]>
On Fri, 19 Mar 2021 10:34:20 +0800, Seiya Wang wrote:
> This commit adds dt-binding documentation of timer for Mediatek MT8195 SoC
> Platform.
>
> Signed-off-by: Seiya Wang <[email protected]>
> ---
> Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <[email protected]>
On Fri, 19 Mar 2021 10:34:24 +0800, Seiya Wang wrote:
> This commit adds dt-binding documentation of auxadc for Mediatek MT8195 SoC
> Platform.
>
> Signed-off-by: Seiya Wang <[email protected]>
> ---
> Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <[email protected]>
On Fri, 19 Mar 2021 10:34:25 +0800, Seiya Wang wrote:
> This commit adds dt-binding documentation for the Mediatek MT8195
> reference board.
>
> Signed-off-by: Seiya Wang <[email protected]>
> ---
> Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
Acked-by: Rob Herring <[email protected]>
On Fri, 19 Mar 2021 10:34:26 +0800, Seiya Wang wrote:
> This commit fixes the warning messages of make dt_binding_check from
> newly added mediatek,mt8195-ufsphy in mediatek,ufs-phy.yaml
>
> Signed-off-by: Seiya Wang <[email protected]>
> ---
> Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
Acked-by: Rob Herring <[email protected]>
On 19/03/2021 03:34, Seiya Wang wrote:
> This commit adds dt-binding documentation of timer for Mediatek MT8195 SoC
> Platform.
>
> Signed-off-by: Seiya Wang <[email protected]>
Applied to v5.12-next/dts64
Thanks!
> ---
> Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
> index 690a9c0966ac..e5c57d6e0186 100644
> --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
> +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
> @@ -23,6 +23,7 @@ Required properties:
> For those SoCs that use SYST
> * "mediatek,mt8183-timer" for MT8183 compatible timers (SYST)
> * "mediatek,mt8192-timer" for MT8192 compatible timers (SYST)
> + * "mediatek,mt8195-timer" for MT8195 compatible timers (SYST)
> * "mediatek,mt7629-timer" for MT7629 compatible timers (SYST)
> * "mediatek,mt6765-timer" for MT6765 and all above compatible timers (SYST)
>
>
On 19/03/2021 03:34, Seiya Wang wrote:
> This commit adds dt-binding documentation for the Mediatek MT8195
> reference board.
>
> Signed-off-by: Seiya Wang <[email protected]>
Applied to v5.12-next/dts64
Thanks!
> ---
> Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
> index 93b3bdf6eaeb..a95224fcff9f 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
> @@ -118,6 +118,10 @@ properties:
> - enum:
> - mediatek,mt8183-evb
> - const: mediatek,mt8183
> + - items:
> + - enum:
> + - mediatek,mt8195-evb
> + - const: mediatek,mt8195
> - description: Google Krane (Lenovo IdeaPad Duet, 10e,...)
> items:
> - enum:
>
On 19/03/2021 03:34, Seiya Wang wrote:
> This commit adds dt-binding documentation of uart for Mediatek MT8195 SoC
> Platform.
>
> Signed-off-by: Seiya Wang <[email protected]>
Applied to v5.12-next/dts64
Thanks!
> ---
> Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
> index 647b5aee86f3..64c4fb59acd1 100644
> --- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
> +++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
> @@ -20,6 +20,7 @@ Required properties:
> * "mediatek,mt8173-uart" for MT8173 compatible UARTS
> * "mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS
> * "mediatek,mt8192-uart", "mediatek,mt6577-uart" for MT8192 compatible UARTS
> + * "mediatek,mt8195-uart", "mediatek,mt6577-uart" for MT8195 compatible UARTS
> * "mediatek,mt8516-uart" for MT8516 compatible UARTS
> * "mediatek,mt6577-uart" for MT6577 and all of the above
>
>
On 19-03-21, 10:34, Seiya Wang wrote:
> This commit fixes the warning messages of make dt_binding_check from
> newly added mediatek,mt8195-ufsphy in mediatek,ufs-phy.yaml
Applied, thanks
--
~Vinod
On 29/03/2021 13:52, Matthias Brugger wrote:
>
>
> On 19/03/2021 03:34, Seiya Wang wrote:
>> This commit adds dt-binding documentation of timer for Mediatek MT8195 SoC
>> Platform.
>>
>> Signed-off-by: Seiya Wang <[email protected]>
>
> Applied to v5.12-next/dts64
Usually bindings go through the subsystem maintainer.
--
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<http://www.linaro.org/linaro-blog/> Blog
Hi Daniel,
On 04/04/2021 22:33, Daniel Lezcano wrote:
> On 29/03/2021 13:52, Matthias Brugger wrote:
>>
>>
>> On 19/03/2021 03:34, Seiya Wang wrote:
>>> This commit adds dt-binding documentation of timer for Mediatek MT8195 SoC
>>> Platform.
>>>
>>> Signed-off-by: Seiya Wang <[email protected]>
>>
>> Applied to v5.12-next/dts64
>
> Usually bindings go through the subsystem maintainer.
>
Yes I know, although not all maintainers are taking them. I'll coordinate with
you the next time, sorry for any inconvenience caused by this.
Regards,
Matthias
Hi Wim,
On 26/03/2021 02:40, Rob Herring wrote:
> On Fri, 19 Mar 2021 10:34:22 +0800, Seiya Wang wrote:
>> This commit adds dt-binding documentation of watchdog for Mediatek MT8195 SoC
>> Platform.
>>
>> Signed-off-by: Seiya Wang <[email protected]>
>> Reviewed-by: Guenter Roeck <[email protected]>
>> ---
>> Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
>> 1 file changed, 1 insertion(+)
>>
>
> Acked-by: Rob Herring <[email protected]>
>
I suppose you will take this patch through your tree. If you want me to take it
through the MediaTek SoC tree, please let me know.
Regards,
Matthias