Add SMP support for a Cortex-A7 CPU in Qualcomm Snapdragon 200 SoCs:
- MSM8210, MSM8610. MSM8212, MSM8612, MSM8909
and in Snapdragon 400 SoCs:
- APQ8026, MSM8x26, MSM8x28
Bartosz Dudziak (2):
dt-bindings: arm: Document qcom,cpss-acc
arm: qcom: Add SMP support for Cortex-A7
.../devicetree/bindings/arm/cpus.yaml | 7 +-
.../bindings/arm/msm/qcom,cpss-acc.yaml | 41 +++++++++++
arch/arm/mach-qcom/platsmp.c | 72 +++++++++++++++++++
3 files changed, 117 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,cpss-acc.yaml
--
2.25.1
Implement support for Cortex-A7 CPU release sequence.
Signed-off-by: Bartosz Dudziak <[email protected]>
---
arch/arm/mach-qcom/platsmp.c | 72 ++++++++++++++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c
index 630a038f45..10780bf14a 100644
--- a/arch/arm/mach-qcom/platsmp.c
+++ b/arch/arm/mach-qcom/platsmp.c
@@ -29,6 +29,7 @@
#define COREPOR_RST BIT(5)
#define CORE_RST BIT(4)
#define L2DT_SLP BIT(3)
+#define CORE_MEM_CLAMP BIT(1)
#define CLAMP BIT(0)
#define APC_PWR_GATE_CTL 0x14
@@ -75,6 +76,63 @@ static int scss_release_secondary(unsigned int cpu)
return 0;
}
+static int cortex_a7_release_secondary(unsigned int cpu)
+{
+ int ret = 0;
+ void __iomem *reg;
+ struct device_node *cpu_node, *acc_node;
+ u32 reg_val;
+
+ cpu_node = of_get_cpu_node(cpu, NULL);
+ if (!cpu_node)
+ return -ENODEV;
+
+ acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
+ if (!acc_node) {
+ ret = -ENODEV;
+ goto out_acc;
+ }
+
+ reg = of_iomap(acc_node, 0);
+ if (!reg) {
+ ret = -ENOMEM;
+ goto out_acc_map;
+ }
+
+ /* Put the CPU into reset. */
+ reg_val = CORE_RST | COREPOR_RST | CLAMP | CORE_MEM_CLAMP;
+ writel(reg_val, reg + APCS_CPU_PWR_CTL);
+
+ /* Turn on the BHS, set the BHS_CNT to 16 XO clock cycles */
+ writel(BHS_EN | (0x10 << BHS_CNT_SHIFT), reg + APC_PWR_GATE_CTL);
+ /* Wait for the BHS to settle */
+ udelay(2);
+
+ reg_val &= ~CORE_MEM_CLAMP;
+ writel(reg_val, reg + APCS_CPU_PWR_CTL);
+
+ reg_val |= L2DT_SLP;
+ writel(reg_val, reg + APCS_CPU_PWR_CTL);
+ udelay(2);
+
+ reg_val = (reg_val | BIT(17)) & ~CLAMP;
+ writel(reg_val, reg + APCS_CPU_PWR_CTL);
+ udelay(2);
+
+ /* Release CPU out of reset and bring it to life. */
+ reg_val &= ~(CORE_RST | COREPOR_RST);
+ writel(reg_val, reg + APCS_CPU_PWR_CTL);
+ reg_val |= CORE_PWRD_UP;
+ writel(reg_val, reg + APCS_CPU_PWR_CTL);
+
+out_acc_map:
+ of_node_put(acc_node);
+out_acc:
+ of_node_put(cpu_node);
+
+ return ret;
+}
+
static int kpssv1_release_secondary(unsigned int cpu)
{
int ret = 0;
@@ -281,6 +339,11 @@ static int msm8660_boot_secondary(unsigned int cpu, struct task_struct *idle)
return qcom_boot_secondary(cpu, scss_release_secondary);
}
+static int cortex_a7_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ return qcom_boot_secondary(cpu, cortex_a7_release_secondary);
+}
+
static int kpssv1_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
return qcom_boot_secondary(cpu, kpssv1_release_secondary);
@@ -315,6 +378,15 @@ static const struct smp_operations smp_msm8660_ops __initconst = {
};
CPU_METHOD_OF_DECLARE(qcom_smp, "qcom,gcc-msm8660", &smp_msm8660_ops);
+static const struct smp_operations qcom_smp_cortex_a7_ops __initconst = {
+ .smp_prepare_cpus = qcom_smp_prepare_cpus,
+ .smp_boot_secondary = cortex_a7_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+ .cpu_die = qcom_cpu_die,
+#endif
+};
+CPU_METHOD_OF_DECLARE(qcom_smp_cortex_a7, "qcom,cpss-acc", &qcom_smp_cortex_a7_ops);
+
static const struct smp_operations qcom_smp_kpssv1_ops __initconst = {
.smp_prepare_cpus = qcom_smp_prepare_cpus,
.smp_boot_secondary = kpssv1_boot_secondary,
--
2.25.1
The CPSS ACC binding describes the clock, reset, and power domain
controller for a Cortex-A7 CPU.
Signed-off-by: Bartosz Dudziak <[email protected]>
---
.../devicetree/bindings/arm/cpus.yaml | 7 ++--
.../bindings/arm/msm/qcom,cpss-acc.yaml | 41 +++++++++++++++++++
2 files changed, 45 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,cpss-acc.yaml
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index 26b886b20b..f391e15184 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -204,6 +204,7 @@ properties:
- marvell,mmp3-smp
- mediatek,mt6589-smp
- mediatek,mt81xx-tz-smp
+ - qcom,cpss-acc
- qcom,gcc-msm8660
- qcom,kpss-acc-v1
- qcom,kpss-acc-v2
@@ -276,7 +277,7 @@ properties:
Specifies the SAW* node associated with this CPU.
Required for systems that have an "enable-method" property
- value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
+ value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2" or "qcom,cpss-acc"
* arm/msm/qcom,saw2.txt
@@ -286,9 +287,9 @@ properties:
Specifies the ACC* node associated with this CPU.
Required for systems that have an "enable-method" property
- value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
+ value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2" or "qcom,cpss-acc"
- * arm/msm/qcom,kpss-acc.txt
+ * arm/msm/qcom,kpss-acc.txt or arm/msm/qcom,cpss-acc.yaml
rockchip,pmu:
$ref: '/schemas/types.yaml#/definitions/phandle'
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,cpss-acc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,cpss-acc.yaml
new file mode 100644
index 0000000000..54efbc5e3d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,cpss-acc.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/msm/qcom,cpss-acc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cortex-A7 Processor Sub-system (CPSS) Application Clock Controller (ACC)
+
+maintainers:
+ - Kumar Gala <[email protected]>
+
+description: |
+ The CPSS ACC provides clock, power domain, and reset control to a Cortex-A7
+ processor. There is one ACC register region per CPU within the PSS remapped
+ region as well as an alias register region that remaps accesses to the ACC
+ associated with the CPU accessing the region.
+
+properties:
+ compatible:
+ enum:
+ - qcom,cpss-acc
+
+ reg:
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: ACC base register region
+ - description: optional ACC alias register region
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@f9088000 {
+ compatible = "qcom,cpss-acc";
+ reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
+ };
--
2.25.1
On Thu, May 13, 2021 at 05:34:41PM +0200, Bartosz Dudziak wrote:
> The CPSS ACC binding describes the clock, reset, and power domain
> controller for a Cortex-A7 CPU.
>
> Signed-off-by: Bartosz Dudziak <[email protected]>
> ---
> .../devicetree/bindings/arm/cpus.yaml | 7 ++--
> .../bindings/arm/msm/qcom,cpss-acc.yaml | 41 +++++++++++++++++++
> 2 files changed, 45 insertions(+), 3 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,cpss-acc.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
> index 26b886b20b..f391e15184 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.yaml
> +++ b/Documentation/devicetree/bindings/arm/cpus.yaml
> @@ -204,6 +204,7 @@ properties:
> - marvell,mmp3-smp
> - mediatek,mt6589-smp
> - mediatek,mt81xx-tz-smp
> + - qcom,cpss-acc
This should not be the same as the compatible below.
> - qcom,gcc-msm8660
> - qcom,kpss-acc-v1
> - qcom,kpss-acc-v2
> @@ -276,7 +277,7 @@ properties:
> Specifies the SAW* node associated with this CPU.
>
> Required for systems that have an "enable-method" property
> - value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
> + value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2" or "qcom,cpss-acc"
>
> * arm/msm/qcom,saw2.txt
>
> @@ -286,9 +287,9 @@ properties:
> Specifies the ACC* node associated with this CPU.
>
> Required for systems that have an "enable-method" property
> - value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
> + value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2" or "qcom,cpss-acc"
>
> - * arm/msm/qcom,kpss-acc.txt
> + * arm/msm/qcom,kpss-acc.txt or arm/msm/qcom,cpss-acc.yaml
>
> rockchip,pmu:
> $ref: '/schemas/types.yaml#/definitions/phandle'
> diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,cpss-acc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,cpss-acc.yaml
> new file mode 100644
> index 0000000000..54efbc5e3d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/msm/qcom,cpss-acc.yaml
> @@ -0,0 +1,41 @@
> +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/msm/qcom,cpss-acc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Cortex-A7 Processor Sub-system (CPSS) Application Clock Controller (ACC)
> +
> +maintainers:
> + - Kumar Gala <[email protected]>
Not an active email nor is Kumar maintaining QCom stuff any more.
> +
> +description: |
> + The CPSS ACC provides clock, power domain, and reset control to a Cortex-A7
> + processor. There is one ACC register region per CPU within the PSS remapped
> + region as well as an alias register region that remaps accesses to the ACC
> + associated with the CPU accessing the region.
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,cpss-acc
This needs to be SoC specific.
> +
> + reg:
> + minItems: 1
> + maxItems: 2
> + items:
> + - description: ACC base register region
> + - description: optional ACC alias register region
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + clock-controller@f9088000 {
> + compatible = "qcom,cpss-acc";
> + reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
> + };
> --
> 2.25.1
>
Hi,
On Thu, May 13, 2021 at 05:34:42PM +0200, Bartosz Dudziak wrote:
> Implement support for Cortex-A7 CPU release sequence.
>
> Signed-off-by: Bartosz Dudziak <[email protected]>
> ---
> arch/arm/mach-qcom/platsmp.c | 72 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 72 insertions(+)
>
> diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c
> index 630a038f45..10780bf14a 100644
> --- a/arch/arm/mach-qcom/platsmp.c
> +++ b/arch/arm/mach-qcom/platsmp.c
> @@ -29,6 +29,7 @@
> #define COREPOR_RST BIT(5)
> #define CORE_RST BIT(4)
> #define L2DT_SLP BIT(3)
> +#define CORE_MEM_CLAMP BIT(1)
> #define CLAMP BIT(0)
>
> #define APC_PWR_GATE_CTL 0x14
> @@ -75,6 +76,63 @@ static int scss_release_secondary(unsigned int cpu)
> return 0;
> }
>
> +static int cortex_a7_release_secondary(unsigned int cpu)
> +{
> + int ret = 0;
> + void __iomem *reg;
> + struct device_node *cpu_node, *acc_node;
> + u32 reg_val;
> +
> + cpu_node = of_get_cpu_node(cpu, NULL);
> + if (!cpu_node)
> + return -ENODEV;
> +
> + acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
> + if (!acc_node) {
> + ret = -ENODEV;
> + goto out_acc;
> + }
> +
> + reg = of_iomap(acc_node, 0);
> + if (!reg) {
> + ret = -ENOMEM;
> + goto out_acc_map;
> + }
> +
> + /* Put the CPU into reset. */
> + reg_val = CORE_RST | COREPOR_RST | CLAMP | CORE_MEM_CLAMP;
> + writel(reg_val, reg + APCS_CPU_PWR_CTL);
> +
> + /* Turn on the BHS, set the BHS_CNT to 16 XO clock cycles */
> + writel(BHS_EN | (0x10 << BHS_CNT_SHIFT), reg + APC_PWR_GATE_CTL);
> + /* Wait for the BHS to settle */
> + udelay(2);
> +
> + reg_val &= ~CORE_MEM_CLAMP;
> + writel(reg_val, reg + APCS_CPU_PWR_CTL);
> +
> + reg_val |= L2DT_SLP;
> + writel(reg_val, reg + APCS_CPU_PWR_CTL);
> + udelay(2);
> +
> + reg_val = (reg_val | BIT(17)) & ~CLAMP;
> + writel(reg_val, reg + APCS_CPU_PWR_CTL);
> + udelay(2);
> +
> + /* Release CPU out of reset and bring it to life. */
> + reg_val &= ~(CORE_RST | COREPOR_RST);
> + writel(reg_val, reg + APCS_CPU_PWR_CTL);
> + reg_val |= CORE_PWRD_UP;
> + writel(reg_val, reg + APCS_CPU_PWR_CTL);
> +
I think you forgot to add
iounmap(reg);
here :)
> +out_acc_map:
> + of_node_put(acc_node);
> +out_acc:
> + of_node_put(cpu_node);
> +
> + return ret;
> +}
> +
> static int kpssv1_release_secondary(unsigned int cpu)
> {
> int ret = 0;
> @@ -281,6 +339,11 @@ static int msm8660_boot_secondary(unsigned int cpu, struct task_struct *idle)
> return qcom_boot_secondary(cpu, scss_release_secondary);
> }
>
> +static int cortex_a7_boot_secondary(unsigned int cpu, struct task_struct *idle)
> +{
> + return qcom_boot_secondary(cpu, cortex_a7_release_secondary);
> +}
> +
> static int kpssv1_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> return qcom_boot_secondary(cpu, kpssv1_release_secondary);
> @@ -315,6 +378,15 @@ static const struct smp_operations smp_msm8660_ops __initconst = {
> };
> CPU_METHOD_OF_DECLARE(qcom_smp, "qcom,gcc-msm8660", &smp_msm8660_ops);
>
> +static const struct smp_operations qcom_smp_cortex_a7_ops __initconst = {
> + .smp_prepare_cpus = qcom_smp_prepare_cpus,
> + .smp_boot_secondary = cortex_a7_boot_secondary,
> +#ifdef CONFIG_HOTPLUG_CPU
> + .cpu_die = qcom_cpu_die,
> +#endif
> +};
> +CPU_METHOD_OF_DECLARE(qcom_smp_cortex_a7, "qcom,cpss-acc", &qcom_smp_cortex_a7_ops);
> +
I'm a bit curious about the name "CPSS". Is that something you came up
with yourself similar to KPSS? There is a slight naming collision here
with the "Chip peripheral subsystem" (CPSS) on APQ8064E (Snapdragon 600),
see https://developer.qualcomm.com/download/sd600/snapdragon-600-device-spec.pdf
Thanks,
Stephan
Hi,
On Tue, May 25, 2021 at 02:20:59PM +0200, Stephan Gerhold wrote:
> Hi,
>
> On Thu, May 13, 2021 at 05:34:42PM +0200, Bartosz Dudziak wrote:
> > Implement support for Cortex-A7 CPU release sequence.
> >
> > Signed-off-by: Bartosz Dudziak <[email protected]>
> > ---
> > arch/arm/mach-qcom/platsmp.c | 72 ++++++++++++++++++++++++++++++++++++
> > 1 file changed, 72 insertions(+)
> >
> > diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c
> > index 630a038f45..10780bf14a 100644
> > --- a/arch/arm/mach-qcom/platsmp.c
> > +++ b/arch/arm/mach-qcom/platsmp.c
> > @@ -29,6 +29,7 @@
> > #define COREPOR_RST BIT(5)
> > #define CORE_RST BIT(4)
> > #define L2DT_SLP BIT(3)
> > +#define CORE_MEM_CLAMP BIT(1)
> > #define CLAMP BIT(0)
> >
> > #define APC_PWR_GATE_CTL 0x14
> > @@ -75,6 +76,63 @@ static int scss_release_secondary(unsigned int cpu)
> > return 0;
> > }
> >
> > +static int cortex_a7_release_secondary(unsigned int cpu)
> > +{
> > + int ret = 0;
> > + void __iomem *reg;
> > + struct device_node *cpu_node, *acc_node;
> > + u32 reg_val;
> > +
> > + cpu_node = of_get_cpu_node(cpu, NULL);
> > + if (!cpu_node)
> > + return -ENODEV;
> > +
> > + acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
> > + if (!acc_node) {
> > + ret = -ENODEV;
> > + goto out_acc;
> > + }
> > +
> > + reg = of_iomap(acc_node, 0);
> > + if (!reg) {
> > + ret = -ENOMEM;
> > + goto out_acc_map;
> > + }
> > +
> > + /* Put the CPU into reset. */
> > + reg_val = CORE_RST | COREPOR_RST | CLAMP | CORE_MEM_CLAMP;
> > + writel(reg_val, reg + APCS_CPU_PWR_CTL);
> > +
> > + /* Turn on the BHS, set the BHS_CNT to 16 XO clock cycles */
> > + writel(BHS_EN | (0x10 << BHS_CNT_SHIFT), reg + APC_PWR_GATE_CTL);
> > + /* Wait for the BHS to settle */
> > + udelay(2);
> > +
> > + reg_val &= ~CORE_MEM_CLAMP;
> > + writel(reg_val, reg + APCS_CPU_PWR_CTL);
> > +
> > + reg_val |= L2DT_SLP;
> > + writel(reg_val, reg + APCS_CPU_PWR_CTL);
> > + udelay(2);
> > +
> > + reg_val = (reg_val | BIT(17)) & ~CLAMP;
> > + writel(reg_val, reg + APCS_CPU_PWR_CTL);
> > + udelay(2);
> > +
> > + /* Release CPU out of reset and bring it to life. */
> > + reg_val &= ~(CORE_RST | COREPOR_RST);
> > + writel(reg_val, reg + APCS_CPU_PWR_CTL);
> > + reg_val |= CORE_PWRD_UP;
> > + writel(reg_val, reg + APCS_CPU_PWR_CTL);
> > +
>
> I think you forgot to add
>
> iounmap(reg);
>
> here :)
>
Thank you, i have missed it.
> > +out_acc_map:
> > + of_node_put(acc_node);
> > +out_acc:
> > + of_node_put(cpu_node);
> > +
> > + return ret;
> > +}
> > +
> > static int kpssv1_release_secondary(unsigned int cpu)
> > {
> > int ret = 0;
> > @@ -281,6 +339,11 @@ static int msm8660_boot_secondary(unsigned int cpu, struct task_struct *idle)
> > return qcom_boot_secondary(cpu, scss_release_secondary);
> > }
> >
> > +static int cortex_a7_boot_secondary(unsigned int cpu, struct task_struct *idle)
> > +{
> > + return qcom_boot_secondary(cpu, cortex_a7_release_secondary);
> > +}
> > +
> > static int kpssv1_boot_secondary(unsigned int cpu, struct task_struct *idle)
> > {
> > return qcom_boot_secondary(cpu, kpssv1_release_secondary);
> > @@ -315,6 +378,15 @@ static const struct smp_operations smp_msm8660_ops __initconst = {
> > };
> > CPU_METHOD_OF_DECLARE(qcom_smp, "qcom,gcc-msm8660", &smp_msm8660_ops);
> >
> > +static const struct smp_operations qcom_smp_cortex_a7_ops __initconst = {
> > + .smp_prepare_cpus = qcom_smp_prepare_cpus,
> > + .smp_boot_secondary = cortex_a7_boot_secondary,
> > +#ifdef CONFIG_HOTPLUG_CPU
> > + .cpu_die = qcom_cpu_die,
> > +#endif
> > +};
> > +CPU_METHOD_OF_DECLARE(qcom_smp_cortex_a7, "qcom,cpss-acc", &qcom_smp_cortex_a7_ops);
> > +
>
> I'm a bit curious about the name "CPSS". Is that something you came up
> with yourself similar to KPSS? There is a slight naming collision here
> with the "Chip peripheral subsystem" (CPSS) on APQ8064E (Snapdragon 600),
> see https://developer.qualcomm.com/download/sd600/snapdragon-600-device-spec.pdf
>
> Thanks,
> Stephan
Yes, the "CPSS" is something i came up with when i was looking at KPSS bindings.
Sorry that i did not check for a naming collision. I will think about a better
name and send a v2 patch on the weekend with iounmap() included.
Thanks for the review,
Bartosz