Changes in v5:
- Add support in device trees for rv1126
- Support sfc tx_dual, tx_quad
- Simplify the code, such as remove "rockchip_sfc_register_all"
- Support SFC ver4 ver5
Changes in v4:
- Changing patch back to an "RFC". An engineer from Rockchip
reached out to me to let me know they are working on this patch for
upstream, I am submitting this v4 for the community to see however
I expect Jon Lin ([email protected]) will submit new patches
soon and these are the ones we should pursue for mainlining. Jon's
patch series should include support for more hardware than this
series.
- Clean up documentation more and ensure it is correct per
make dt_binding_check.
- Add support in device trees for rk3036, rk3308, and rv1108.
- Add ahb clock (hclk_sfc) support for rk3036.
- Change rockchip_sfc_wait_fifo_ready() to use a switch statement.
- Change IRQ code to only mark IRQ as handled if it handles the
specific IRQ (DMA transfer finish) it is supposed to handle.
Changes in v3:
- Changed the name of the clocks to sfc/ahb (from clk-sfc/clk-hsfc).
- Changed the compatible string from rockchip,sfc to
rockchip,rk3036-sfc. A quick glance at the datasheets suggests this
driver should work for the PX30, RK180x, RK3036, RK312x, RK3308 and
RV1108 SoCs, and possibly more. However, I am currently only able
to test this on a PX30 (an RK3326). The technical reference manuals
appear to list the same registers for each device.
- Corrected devicetree documentation for formatting and to note these
changes.
- Replaced the maintainer with Heiko Stuebner and myself, as we will
take ownership of this going forward.
- Noted that the device (per the reference manual) supports 4 CS, but
I am only able to test a single CS (CS 0).
- Reordered patches to comply with upstream rules.
Changes in v2:
- Reimplemented driver using spi-mem subsystem.
- Removed power management code as I couldn't get it working properly.
- Added device tree bindings for Odroid Go Advance.
Changes in v1:
hanges made in this new series versus the v8 of the old series:
- Added function to read spi-rx-bus-width from device tree, in the
event that the SPI chip supports 4x mode but only has 2 pins
wired (such as the Odroid Go Advance).
- Changed device tree documentation from txt to yaml format.
- Made "reset" message a dev_dbg from a dev_info.
- Changed read and write fifo functions to remove redundant checks.
- Changed the write and read from relaxed to non-relaxed when
starting the DMA transfer or reading the DMA IRQ.
- Changed from dma_coerce_mask_and_coherent to just
dma_set_mask_and_coherent.
- Changed name of get_if_type to rockchip_sfc_get_if_type.
Chris Morgan (8):
dt-bindings: rockchip-sfc: Bindings for Rockchip serial flash
controller
spi: rockchip-sfc: add rockchip serial flash controller
arm64: dts: rockchip: Add SFC to PX30
clk: rockchip: Add support for hclk_sfc on rk3036
arm: dts: rockchip: Add SFC to RK3036
arm: dts: rockchip: Add SFC to RV1108
arm64: dts: rockchip: Add SFC to RK3308
arm64: dts: rockchip: Enable SFC for Odroid Go Advance
.../devicetree/bindings/spi/rockchip-sfc.yaml | 86 ++
arch/arm/boot/dts/rk3036.dtsi | 42 +
arch/arm/boot/dts/rv1108.dtsi | 37 +
arch/arm64/boot/dts/rockchip/px30.dtsi | 38 +
arch/arm64/boot/dts/rockchip/rk3308.dtsi | 37 +
.../boot/dts/rockchip/rk3326-odroid-go2.dts | 16 +
drivers/clk/rockchip/clk-rk3036.c | 2 +-
drivers/spi/Kconfig | 9 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-rockchip-sfc.c | 863 ++++++++++++++++++
include/dt-bindings/clock/rk3036-cru.h | 1 +
11 files changed, 1131 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/spi/rockchip-sfc.yaml
create mode 100644 drivers/spi/spi-rockchip-sfc.c
--
2.17.1
From: Chris Morgan <[email protected]>
Add a devicetree entry for the Rockchip SFC for the PX30 SOC.
Signed-off-by: Chris Morgan <[email protected]>
Signed-off-by: Jon Lin <[email protected]>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
Changes in v1: None
arch/arm64/boot/dts/rockchip/px30.dtsi | 38 ++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index 09baa8a167ce..cc7aced2dde9 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -966,6 +966,18 @@
status = "disabled";
};
+ sfc: spi@ff3a0000 {
+ compatible = "rockchip,px30-sfc","rockchip,rk3036-sfc";
+ reg = <0x0 0xff3a0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SFC>, <&cru SCLK_SFC>;
+ clock-names = "ahb", "sfc";
+ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
+ pinctrl-names = "default";
+ power-domains = <&power PX30_PD_MMC_NAND>;
+ status = "disabled";
+ };
+
nfc: nand-controller@ff3b0000 {
compatible = "rockchip,px30-nfc";
reg = <0x0 0xff3b0000 0x0 0x4000>;
@@ -1967,6 +1979,32 @@
};
};
+ serial_flash {
+ sfc_bus4: sfc-bus4 {
+ rockchip,pins =
+ <1 RK_PA0 3 &pcfg_pull_none>,
+ <1 RK_PA1 3 &pcfg_pull_none>,
+ <1 RK_PA2 3 &pcfg_pull_none>,
+ <1 RK_PA3 3 &pcfg_pull_none>;
+ };
+
+ sfc_bus2: sfc-bus2 {
+ rockchip,pins =
+ <1 RK_PA0 3 &pcfg_pull_none>,
+ <1 RK_PA1 3 &pcfg_pull_none>;
+ };
+
+ sfc_cs0: sfc-cs0 {
+ rockchip,pins =
+ <1 RK_PA4 3 &pcfg_pull_none>;
+ };
+
+ sfc_clk: sfc-clk {
+ rockchip,pins =
+ <1 RK_PB1 3 &pcfg_pull_none>;
+ };
+ };
+
lcdc {
lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
rockchip,pins =
--
2.17.1
From: Chris Morgan <[email protected]>
Add support for the bus clock for the serial flash controller on the
rk3036. Taken from the Rockchip BSP kernel but not tested on real
hardware (as I lack a 3036 based SoC to test).
Signed-off-by: Chris Morgan <[email protected]>
Signed-off-by: Jon Lin <[email protected]>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
Changes in v1: None
drivers/clk/rockchip/clk-rk3036.c | 2 +-
include/dt-bindings/clock/rk3036-cru.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index 91d56ad45817..ebb628733f6d 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -403,7 +403,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS),
GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 3, GFLAGS),
GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
- GATE(0, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS),
+ GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS),
GATE(HCLK_MAC, "hclk_mac", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS),
/* pclk_peri gates */
diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h
index 35a5a01f9697..a96a9870ad59 100644
--- a/include/dt-bindings/clock/rk3036-cru.h
+++ b/include/dt-bindings/clock/rk3036-cru.h
@@ -81,6 +81,7 @@
#define HCLK_OTG0 449
#define HCLK_OTG1 450
#define HCLK_NANDC 453
+#define HCLK_SFC 454
#define HCLK_SDMMC 456
#define HCLK_SDIO 457
#define HCLK_EMMC 459
--
2.17.1
From: Chris Morgan <[email protected]>
Add bindings for the Rockchip serial flash controller. New device
specific parameter of rockchip,sfc-no-dma included in documentation.
Signed-off-by: Chris Morgan <[email protected]>
Signed-off-by: Jon Lin <[email protected]>
---
Changes in v5:
- Add support in device trees for rv1126
- Support sfc tx_dual, tx_quad
- Simplify the code, such as remove "rockchip_sfc_register_all"
- Support SFC ver4 ver5
Changes in v4:
- Changing patch back to an "RFC". An engineer from Rockchip
reached out to me to let me know they are working on this patch for
upstream, I am submitting this v4 for the community to see however
I expect Jon Lin ([email protected]) will submit new patches
soon and these are the ones we should pursue for mainlining. Jon's
patch series should include support for more hardware than this
series.
- Clean up documentation more and ensure it is correct per
make dt_binding_check.
- Add support in device trees for rk3036, rk3308, and rv1108.
- Add ahb clock (hclk_sfc) support for rk3036.
- Change rockchip_sfc_wait_fifo_ready() to use a switch statement.
- Change IRQ code to only mark IRQ as handled if it handles the
specific IRQ (DMA transfer finish) it is supposed to handle.
Changes in v3:
- Changed the name of the clocks to sfc/ahb (from clk-sfc/clk-hsfc).
- Changed the compatible string from rockchip,sfc to
rockchip,rk3036-sfc. A quick glance at the datasheets suggests this
driver should work for the PX30, RK180x, RK3036, RK312x, RK3308 and
RV1108 SoCs, and possibly more. However, I am currently only able
to test this on a PX30 (an RK3326). The technical reference manuals
appear to list the same registers for each device.
- Corrected devicetree documentation for formatting and to note these
changes.
- Replaced the maintainer with Heiko Stuebner and myself, as we will
take ownership of this going forward.
- Noted that the device (per the reference manual) supports 4 CS, but
I am only able to test a single CS (CS 0).
- Reordered patches to comply with upstream rules.
Changes in v2:
- Reimplemented driver using spi-mem subsystem.
- Removed power management code as I couldn't get it working properly.
- Added device tree bindings for Odroid Go Advance.
Changes in v1:
hanges made in this new series versus the v8 of the old series:
- Added function to read spi-rx-bus-width from device tree, in the
event that the SPI chip supports 4x mode but only has 2 pins
wired (such as the Odroid Go Advance).
- Changed device tree documentation from txt to yaml format.
- Made "reset" message a dev_dbg from a dev_info.
- Changed read and write fifo functions to remove redundant checks.
- Changed the write and read from relaxed to non-relaxed when
starting the DMA transfer or reading the DMA IRQ.
- Changed from dma_coerce_mask_and_coherent to just
dma_set_mask_and_coherent.
- Changed name of get_if_type to rockchip_sfc_get_if_type.
.../devicetree/bindings/spi/rockchip-sfc.yaml | 86 +++++++++++++++++++
1 file changed, 86 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/rockchip-sfc.yaml
diff --git a/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml
new file mode 100644
index 000000000000..120c06f86a28
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip Serial Flash Controller (SFC)
+
+maintainers:
+ - Heiko Stuebner <[email protected]>
+ - Chris Morgan <[email protected]>
+
+allOf:
+ - $ref: spi-controller.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - const: rockchip,rk3036-sfc
+ - items:
+ - enum:
+ - rockchip,px30-sfc
+ - rockchip,rk3308-sfc
+ - rockchip,rv1108-sfc
+ - const: rockchip,rk3036-sfc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Bus Clock
+ - description: Module Clock
+
+ clock-names:
+ items:
+ - const: ahb
+ - const: sfc
+
+ power-domains:
+ maxItems: 1
+
+ rockchip,sfc-no-dma:
+ description: Disable DMA and utilize FIFO mode only
+ type: boolean
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/px30-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/px30-power.h>
+
+ sfc: spi@ff3a0000 {
+ compatible = "rockchip,px30-sfc","rockchip,rk3036-sfc";
+ reg = <0xff3a0000 0x4000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SFC>, <&cru SCLK_SFC>;
+ clock-names = "ahb", "sfc";
+ pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>;
+ pinctrl-names = "default";
+ power-domains = <&power PX30_PD_MMC_NAND>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <108000000>;
+ spi-rx-bus-width = <2>;
+ spi-tx-bus-width = <2>;
+ };
+ };
+
+...
--
2.17.1
From: Chris Morgan <[email protected]>
Add a devicetree entry for the Rockchip SFC for the RK3036 SOC.
Signed-off-by: Chris Morgan <[email protected]>
Signed-off-by: Jon Lin <[email protected]>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
Changes in v1: None
arch/arm/boot/dts/rk3036.dtsi | 42 +++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index e24230d50a78..0dba2956dfb8 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -206,6 +206,17 @@
status = "disabled";
};
+ sfc: spi@10208000 {
+ compatible = "rockchip,rk3036-sfc";
+ reg = <0x10208000 0x4000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SFC>, <&cru SCLK_SFC>;
+ clock-names = "ahb", "sfc";
+ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
sdmmc: mmc@10214000 {
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10214000 0x4000>;
@@ -684,6 +695,37 @@
};
};
+ serial_flash {
+ sfc_bus4: sfc-bus4 {
+ rockchip,pins =
+ <1 RK_PD0 3 &pcfg_pull_none>,
+ <1 RK_PD1 3 &pcfg_pull_none>,
+ <1 RK_PD2 3 &pcfg_pull_none>,
+ <1 RK_PD3 3 &pcfg_pull_none>;
+ };
+
+ sfc_bus2: sfc-bus2 {
+ rockchip,pins =
+ <1 RK_PD0 3 &pcfg_pull_none>,
+ <1 RK_PD1 3 &pcfg_pull_none>;
+ };
+
+ sfc_cs0: sfc-cs0 {
+ rockchip,pins =
+ <2 RK_PA2 3 &pcfg_pull_none>;
+ };
+
+ sfc_cs1: sfc-cs1 {
+ rockchip,pins =
+ <2 RK_PA3 3 &pcfg_pull_none>;
+ };
+
+ sfc_clk: sfc-clk {
+ rockchip,pins =
+ <2 RK_PA4 3 &pcfg_pull_none>;
+ };
+ };
+
emac {
emac_xfer: emac-xfer {
rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
--
2.17.1