Do not merge, this series has yet to be properly tested. Work is in
progress for sm8350 display driver support, which will test this series
properly.
This series implements display clock controller (dispcc) & video
clock controller (videocc) support for the Qcom SM8350 SOC.
In order to support these new clock controllers, some changes to the
alpha plls are required. These changes add support to the Lucid 5LPE PLLs.
Robert Foss (11):
clk: qcom: common: Add runtime init/suspend/resume
clk: qcom: rcg2: Add support for flags
clk: qcom: clk-alpha-pll: Fix typo in comment
clk: qcom: clk-alpha-pll: Add configuration support for LUCID 5LPE
dt-bindings: clock: Add QCOM SM8350 display clock bindings
clk: qcom: Add display clock controller driver for SM8350
dt-bindings: clock: Add SM8350 QCOM video clock bindings
clk: qcom: Add video clock controller driver for SM8350
arm64: dts: qcom: sm8350: Power up dispcc & videocc on sm8350 by MMCX
regulator
arm64: dts: qcom: sm8350: Add videocc DT node
arm64: dts: qcom: sm8350: Add dispcc DT node
.../bindings/clock/qcom,dispcc-sm8x50.yaml | 6 +-
.../bindings/clock/qcom,videocc.yaml | 2 +
arch/arm64/boot/dts/qcom/sm8350.dtsi | 46 +
drivers/clk/qcom/Kconfig | 18 +
drivers/clk/qcom/Makefile | 2 +
drivers/clk/qcom/clk-alpha-pll.c | 5 +-
drivers/clk/qcom/clk-alpha-pll.h | 5 +
drivers/clk/qcom/clk-rcg.h | 4 +
drivers/clk/qcom/clk-rcg2.c | 3 +
drivers/clk/qcom/common.c | 92 ++
drivers/clk/qcom/common.h | 6 +
drivers/clk/qcom/dispcc-sm8350.c | 1402 +++++++++++++++++
drivers/clk/qcom/videocc-sm8350.c | 593 +++++++
.../dt-bindings/clock/qcom,dispcc-sm8350.h | 77 +
.../dt-bindings/clock/qcom,videocc-sm8350.h | 44 +
15 files changed, 2302 insertions(+), 3 deletions(-)
create mode 100644 drivers/clk/qcom/dispcc-sm8350.c
create mode 100644 drivers/clk/qcom/videocc-sm8350.c
create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8350.h
create mode 100644 include/dt-bindings/clock/qcom,videocc-sm8350.h
--
2.30.2
Add device tree bindings for display clock controller for
Qualcomm Technology Inc's SM8350 SoC.
Signed-off-by: Robert Foss <[email protected]>
---
.../bindings/clock/qcom,dispcc-sm8x50.yaml | 6 +-
.../dt-bindings/clock/qcom,dispcc-sm8350.h | 77 +++++++++++++++++++
2 files changed, 81 insertions(+), 2 deletions(-)
create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8350.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
index 0cdf53f41f84..c10eefd024f6 100644
--- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
@@ -4,24 +4,26 @@
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250
+title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350
maintainers:
- Jonathan Marek <[email protected]>
description: |
Qualcomm display clock control module which supports the clocks, resets and
- power domains on SM8150 and SM8250.
+ power domains on SM8150, SM8250 and SM8350.
See also:
dt-bindings/clock/qcom,dispcc-sm8150.h
dt-bindings/clock/qcom,dispcc-sm8250.h
+ dt-bindings/clock/qcom,dispcc-sm8350.h
properties:
compatible:
enum:
- qcom,sm8150-dispcc
- qcom,sm8250-dispcc
+ - qcom,sm8350-dispcc
clocks:
items:
diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8350.h b/include/dt-bindings/clock/qcom,dispcc-sm8350.h
new file mode 100644
index 000000000000..361ef27de585
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,dispcc-sm8350.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021, Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8350_H
+#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8350_H
+
+/* DISP_CC clock registers */
+#define DISP_CC_MDSS_AHB_CLK 0
+#define DISP_CC_MDSS_AHB_CLK_SRC 1
+#define DISP_CC_MDSS_BYTE0_CLK 2
+#define DISP_CC_MDSS_BYTE0_CLK_SRC 3
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 4
+#define DISP_CC_MDSS_BYTE0_INTF_CLK 5
+#define DISP_CC_MDSS_BYTE1_CLK 6
+#define DISP_CC_MDSS_BYTE1_CLK_SRC 7
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 8
+#define DISP_CC_MDSS_BYTE1_INTF_CLK 9
+#define DISP_CC_MDSS_DP_AUX1_CLK 10
+#define DISP_CC_MDSS_DP_AUX1_CLK_SRC 11
+#define DISP_CC_MDSS_DP_AUX_CLK 12
+#define DISP_CC_MDSS_DP_AUX_CLK_SRC 13
+#define DISP_CC_MDSS_DP_LINK1_CLK 14
+#define DISP_CC_MDSS_DP_LINK1_CLK_SRC 15
+#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC 16
+#define DISP_CC_MDSS_DP_LINK1_INTF_CLK 17
+#define DISP_CC_MDSS_DP_LINK_CLK 18
+#define DISP_CC_MDSS_DP_LINK_CLK_SRC 19
+#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 20
+#define DISP_CC_MDSS_DP_LINK_INTF_CLK 21
+#define DISP_CC_MDSS_DP_PIXEL1_CLK 22
+#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 23
+#define DISP_CC_MDSS_DP_PIXEL2_CLK 24
+#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC 25
+#define DISP_CC_MDSS_DP_PIXEL_CLK 26
+#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 27
+#define DISP_CC_MDSS_EDP_AUX_CLK 28
+#define DISP_CC_MDSS_EDP_AUX_CLK_SRC 29
+#define DISP_CC_MDSS_EDP_LINK_CLK 30
+#define DISP_CC_MDSS_EDP_LINK_CLK_SRC 31
+#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC 32
+#define DISP_CC_MDSS_EDP_LINK_INTF_CLK 33
+#define DISP_CC_MDSS_EDP_PIXEL_CLK 34
+#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 35
+#define DISP_CC_MDSS_ESC0_CLK 36
+#define DISP_CC_MDSS_ESC0_CLK_SRC 37
+#define DISP_CC_MDSS_ESC1_CLK 38
+#define DISP_CC_MDSS_ESC1_CLK_SRC 39
+#define DISP_CC_MDSS_MDP_CLK 40
+#define DISP_CC_MDSS_MDP_CLK_SRC 41
+#define DISP_CC_MDSS_MDP_LUT_CLK 42
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 43
+#define DISP_CC_MDSS_PCLK0_CLK 44
+#define DISP_CC_MDSS_PCLK0_CLK_SRC 45
+#define DISP_CC_MDSS_PCLK1_CLK 46
+#define DISP_CC_MDSS_PCLK1_CLK_SRC 47
+#define DISP_CC_MDSS_ROT_CLK 48
+#define DISP_CC_MDSS_ROT_CLK_SRC 49
+#define DISP_CC_MDSS_RSCC_AHB_CLK 50
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK 51
+#define DISP_CC_MDSS_VSYNC_CLK 52
+#define DISP_CC_MDSS_VSYNC_CLK_SRC 53
+#define DISP_CC_PLL0 54
+#define DISP_CC_PLL1 55
+#define DISP_CC_SLEEP_CLK 56
+#define DISP_CC_SLEEP_CLK_SRC 57
+#define DISP_CC_XO_CLK_SRC 58
+
+/* DISP_CC Reset */
+#define DISP_CC_MDSS_CORE_BCR 0
+#define DISP_CC_MDSS_RSCC_BCR 1
+
+/* DISP_CC GDSCR */
+#define MDSS_GDSC 0
+
+#endif
--
2.30.2
Add support for the video clock controller found on SM8350 based devices.
Derived from the downstream driver.
Signed-off-by: Robert Foss <[email protected]>
---
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/videocc-sm8350.c | 593 ++++++++++++++++++++++++++++++
3 files changed, 603 insertions(+)
create mode 100644 drivers/clk/qcom/videocc-sm8350.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index f7c99f97fa57..181967e90a8a 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -558,6 +558,15 @@ config SM_VIDEOCC_8250
Say Y if you want to support video devices and functionality such as
video encode and decode.
+config SM_VIDEOCC_8350
+ tristate "SM8350 Video Clock Controller"
+ select SDM_GCC_8350
+ select QCOM_GDSC
+ help
+ Support for the video clock controller on SM8350 devices.
+ Say Y if you want to support video devices and functionality such as
+ video encode and decode.
+
config SPMI_PMIC_CLKDIV
tristate "SPMI PMIC clkdiv Support"
depends on SPMI || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 69dc2a9f43d7..adf644b5c1ba 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -82,6 +82,7 @@ obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o
+obj-$(CONFIG_SM_VIDEOCC_8350) += videocc-sm8350.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/videocc-sm8350.c b/drivers/clk/qcom/videocc-sm8350.c
new file mode 100644
index 000000000000..37e1248454c2
--- /dev/null
+++ b/drivers/clk/qcom/videocc-sm8350.c
@@ -0,0 +1,593 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,videocc-sm8350.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "common.h"
+#include "reset.h"
+#include "gdsc.h"
+
+enum {
+ P_BI_TCXO,
+ P_CORE_BI_PLL_TEST_SE,
+ P_SLEEP_CLK,
+ P_VIDEO_PLL0_OUT_MAIN,
+ P_VIDEO_PLL1_OUT_MAIN,
+};
+
+static struct pll_vco lucid_vco[] = {
+ { 249600000, 1750000000, 0 },
+};
+
+static const struct alpha_pll_config video_pll0_config = {
+ .l = 0x25,
+ .alpha = 0x8000,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00002261,
+ .config_ctl_hi1_val = 0x2A9A699C,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000000,
+ .test_ctl_hi1_val = 0x01800000,
+ .user_ctl_val = 0x00000000,
+ .user_ctl_hi_val = 0x00000805,
+ .user_ctl_hi1_val = 0x00000000,
+};
+
+static struct clk_alpha_pll video_pll0 = {
+ .offset = 0x42c,
+ .vco_table = lucid_vco,
+ .num_vco = ARRAY_SIZE(lucid_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "video_pll0",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ .name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_5lpe_ops,
+ },
+ },
+};
+
+static const struct alpha_pll_config video_pll1_config = {
+ .l = 0x2B,
+ .alpha = 0xC000,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00002261,
+ .config_ctl_hi1_val = 0x2A9A699C,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000000,
+ .test_ctl_hi1_val = 0x01800000,
+ .user_ctl_val = 0x00000000,
+ .user_ctl_hi_val = 0x00000805,
+ .user_ctl_hi1_val = 0x00000000,
+};
+
+static struct clk_alpha_pll video_pll1 = {
+ .offset = 0x7d0,
+ .vco_table = lucid_vco,
+ .num_vco = ARRAY_SIZE(lucid_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "video_pll1",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ .name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_5lpe_ops,
+ },
+ },
+};
+
+static const struct parent_map videocc_parent_map_0[] = {
+ { P_BI_TCXO, 0 },
+ { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const struct clk_parent_data videocc_parent_data_0_ao[] = {
+ { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
+ { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+};
+
+static const struct parent_map videocc_parent_map_1[] = {
+ { P_BI_TCXO, 0 },
+ { P_VIDEO_PLL0_OUT_MAIN, 1 },
+ { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const struct clk_parent_data videocc_parent_data_1[] = {
+ { .fw_name = "bi_tcxo" },
+ { .hw = &video_pll0.clkr.hw },
+ { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+};
+
+static const struct parent_map videocc_parent_map_2[] = {
+ { P_BI_TCXO, 0 },
+ { P_VIDEO_PLL1_OUT_MAIN, 1 },
+ { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const struct clk_parent_data videocc_parent_data_2[] = {
+ { .fw_name = "bi_tcxo" },
+ { .hw = &video_pll1.clkr.hw },
+ { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+};
+
+static const struct parent_map videocc_parent_map_3[] = {
+ { P_SLEEP_CLK, 0 },
+ { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const struct clk_parent_data videocc_parent_data_3[] = {
+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
+ { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+};
+
+static const struct freq_tbl ftbl_videocc_ahb_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 videocc_ahb_clk_src = {
+ .cmd_rcgr = 0xbd4,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = videocc_parent_map_0,
+ .freq_tbl = ftbl_videocc_ahb_clk_src,
+ .flags = HW_CLK_CTRL_MODE,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "videocc_ahb_clk_src",
+ .parent_data = videocc_parent_data_0_ao,
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_videocc_mvs0_clk_src[] = {
+ F(720000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
+ F(1014000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
+ F(1098000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
+ F(1332000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 videocc_mvs0_clk_src = {
+ .cmd_rcgr = 0xb94,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = videocc_parent_map_1,
+ .freq_tbl = ftbl_videocc_mvs0_clk_src,
+ .flags = HW_CLK_CTRL_MODE,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "videocc_mvs0_clk_src",
+ .parent_data = videocc_parent_data_1,
+ .num_parents = ARRAY_SIZE(videocc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_videocc_mvs1_clk_src[] = {
+ F(840000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
+ F(1098000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
+ F(1332000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 videocc_mvs1_clk_src = {
+ .cmd_rcgr = 0xbb4,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = videocc_parent_map_2,
+ .freq_tbl = ftbl_videocc_mvs1_clk_src,
+ .flags = HW_CLK_CTRL_MODE,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "videocc_mvs1_clk_src",
+ .parent_data = videocc_parent_data_2,
+ .num_parents = ARRAY_SIZE(videocc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_videocc_sleep_clk_src[] = {
+ F(32000, P_SLEEP_CLK, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 videocc_sleep_clk_src = {
+ .cmd_rcgr = 0xef0,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = videocc_parent_map_3,
+ .freq_tbl = ftbl_videocc_sleep_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "videocc_sleep_clk_src",
+ .parent_data = videocc_parent_data_3,
+ .num_parents = ARRAY_SIZE(videocc_parent_data_3),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 videocc_xo_clk_src = {
+ .cmd_rcgr = 0xecc,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = videocc_parent_map_0,
+ .freq_tbl = ftbl_videocc_ahb_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "videocc_xo_clk_src",
+ .parent_data = videocc_parent_data_0_ao,
+ .num_parents = ARRAY_SIZE(videocc_parent_data_0_ao),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div videocc_mvs0_div_clk_src = {
+ .reg = 0xd54,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "videocc_mvs0_div_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &videocc_mvs0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div videocc_mvs0c_div2_div_clk_src = {
+ .reg = 0xc54,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "videocc_mvs0c_div2_div_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &videocc_mvs0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div videocc_mvs1_div_clk_src = {
+ .reg = 0xdd4,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "videocc_mvs1_div_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &videocc_mvs1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div videocc_mvs1c_div2_div_clk_src = {
+ .reg = 0xcf4,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "videocc_mvs1c_div2_div_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &videocc_mvs1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_branch videocc_mvs0_clk = {
+ .halt_reg = 0xd34,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0xd34,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0xd34,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "videocc_mvs0_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &videocc_mvs0_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch videocc_mvs0c_clk = {
+ .halt_reg = 0xc34,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc34,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "videocc_mvs0c_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &videocc_mvs0c_div2_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch videocc_mvs1_clk = {
+ .halt_reg = 0xdb4,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0xdb4,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0xdb4,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "videocc_mvs1_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &videocc_mvs1_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch videocc_mvs1_div2_clk = {
+ .halt_reg = 0xdf4,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0xdf4,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0xdf4,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "videocc_mvs1_div2_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &videocc_mvs1c_div2_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch videocc_mvs1c_clk = {
+ .halt_reg = 0xcd4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xcd4,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "videocc_mvs1c_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &videocc_mvs1c_div2_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch videocc_sleep_clk = {
+ .halt_reg = 0xf10,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf10,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "videocc_sleep_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &videocc_sleep_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct gdsc mvs0c_gdsc = {
+ .gdscr = 0xbf8,
+ .pd = {
+ .name = "mvs0c_gdsc",
+ },
+ .flags = 0,
+ .pwrsts = PWRSTS_OFF_ON,
+ .supply = "mmcx",
+};
+
+static struct gdsc mvs1c_gdsc = {
+ .gdscr = 0xc98,
+ .pd = {
+ .name = "mvs1c_gdsc",
+ },
+ .flags = 0,
+ .pwrsts = PWRSTS_OFF_ON,
+ .supply = "mmcx",
+};
+
+static struct gdsc mvs0_gdsc = {
+ .gdscr = 0xd18,
+ .pd = {
+ .name = "mvs0_gdsc",
+ },
+ .flags = HW_CTRL,
+ .pwrsts = PWRSTS_OFF_ON,
+ .supply = "mmcx",
+};
+
+static struct gdsc mvs1_gdsc = {
+ .gdscr = 0xd98,
+ .pd = {
+ .name = "mvs1_gdsc",
+ },
+ .flags = HW_CTRL,
+ .pwrsts = PWRSTS_OFF_ON,
+ .supply = "mmcx",
+};
+
+static struct clk_regmap *videocc_sm8350_clocks[] = {
+ [VIDEO_CC_AHB_CLK_SRC] = &videocc_ahb_clk_src.clkr,
+ [VIDEO_CC_MVS0_CLK] = &videocc_mvs0_clk.clkr,
+ [VIDEO_CC_MVS0_CLK_SRC] = &videocc_mvs0_clk_src.clkr,
+ [VIDEO_CC_MVS0_DIV_CLK_SRC] = &videocc_mvs0_div_clk_src.clkr,
+ [VIDEO_CC_MVS0C_CLK] = &videocc_mvs0c_clk.clkr,
+ [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &videocc_mvs0c_div2_div_clk_src.clkr,
+ [VIDEO_CC_MVS1_CLK] = &videocc_mvs1_clk.clkr,
+ [VIDEO_CC_MVS1_CLK_SRC] = &videocc_mvs1_clk_src.clkr,
+ [VIDEO_CC_MVS1_DIV2_CLK] = &videocc_mvs1_div2_clk.clkr,
+ [VIDEO_CC_MVS1_DIV_CLK_SRC] = &videocc_mvs1_div_clk_src.clkr,
+ [VIDEO_CC_MVS1C_CLK] = &videocc_mvs1c_clk.clkr,
+ [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &videocc_mvs1c_div2_div_clk_src.clkr,
+ [VIDEO_CC_SLEEP_CLK] = &videocc_sleep_clk.clkr,
+ [VIDEO_CC_SLEEP_CLK_SRC] = &videocc_sleep_clk_src.clkr,
+ [VIDEO_CC_XO_CLK_SRC] = &videocc_xo_clk_src.clkr,
+ [VIDEO_PLL0] = &video_pll0.clkr,
+ [VIDEO_PLL1] = &video_pll1.clkr,
+};
+
+static const struct qcom_reset_map videocc_sm8350_resets[] = {
+ [VIDEO_CC_CVP_INTERFACE_BCR] = { 0xe54 },
+ [VIDEO_CC_CVP_MVS0_BCR] = { 0xd14 },
+ [VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, 2 },
+ [VIDEO_CC_CVP_MVS0C_BCR] = { 0xbf4 },
+ [VIDEO_CC_CVP_MVS1_BCR] = { 0xd94 },
+ [VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, 2 },
+ [VIDEO_CC_CVP_MVS1C_BCR] = { 0xc94 },
+};
+
+static struct gdsc *videocc_sm8350_gdscs[] = {
+ [MVS0C_GDSC] = &mvs0c_gdsc,
+ [MVS1C_GDSC] = &mvs1c_gdsc,
+ [MVS0_GDSC] = &mvs0_gdsc,
+ [MVS1_GDSC] = &mvs1_gdsc,
+};
+
+static const struct regmap_config videocc_sm8350_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xf4c,
+ .fast_io = true,
+};
+
+static struct qcom_cc_desc videocc_sm8350_desc = {
+ .config = &videocc_sm8350_regmap_config,
+ .clks = videocc_sm8350_clocks,
+ .num_clks = ARRAY_SIZE(videocc_sm8350_clocks),
+ .resets = videocc_sm8350_resets,
+ .num_resets = ARRAY_SIZE(videocc_sm8350_resets),
+ .gdscs = videocc_sm8350_gdscs,
+ .num_gdscs = ARRAY_SIZE(videocc_sm8350_gdscs),
+};
+
+static const struct of_device_id videocc_sm8350_match_table[] = {
+ { .compatible = "qcom,sm8350-videocc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, videocc_sm8350_match_table);
+
+static int videocc_sm8350_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+ int ret;
+
+ regmap = qcom_cc_map(pdev, &videocc_sm8350_desc);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ ret = qcom_cc_runtime_init(pdev, &videocc_sm8350_desc);
+ if (ret)
+ return ret;
+
+ ret = pm_runtime_resume_and_get(&pdev->dev);
+ if (ret)
+ goto err_pm;
+
+ clk_lucid_5lpe_pll_configure(&video_pll0, regmap, &video_pll0_config);
+ clk_lucid_5lpe_pll_configure(&video_pll1, regmap, &video_pll1_config);
+
+ /*
+ * Keep clocks always enabled:
+ * videocc_ahb_clk
+ * videocc_xo_clk
+ */
+ regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0));
+ regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0));
+
+ ret = qcom_cc_really_probe(pdev, &videocc_sm8350_desc, regmap);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to register VIDEOCC clocks\n");
+ goto err_pm;
+ }
+
+ pm_runtime_put_sync(&pdev->dev);
+ dev_info(&pdev->dev, "Registered VIDEOCC clocks\n");
+
+ return ret;
+
+err_pm:
+ pm_runtime_disable(&pdev->dev);
+
+ return ret;
+}
+
+static const struct dev_pm_ops videocc_sm8350_pm_ops = {
+ SET_RUNTIME_PM_OPS(qcom_cc_runtime_suspend, qcom_cc_runtime_resume, NULL)
+ SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
+};
+
+static struct platform_driver videocc_sm8350_driver = {
+ .probe = videocc_sm8350_probe,
+ .driver = {
+ .name = "sm8350-videocc",
+ .of_match_table = videocc_sm8350_match_table,
+ .pm = &videocc_sm8350_pm_ops,
+ },
+};
+
+static int __init videocc_sm8350_init(void)
+{
+ return platform_driver_register(&videocc_sm8350_driver);
+}
+subsys_initcall(videocc_sm8350_init);
+
+static void __exit videocc_sm8350_exit(void)
+{
+ platform_driver_unregister(&videocc_sm8350_driver);
+}
+module_exit(videocc_sm8350_exit);
+
+MODULE_DESCRIPTION("QTI VIDEOCC SM8350 Driver");
+MODULE_LICENSE("GPL v2");
--
2.30.2
On Wed, Jun 16, 2021 at 04:11:01PM +0200, Robert Foss wrote:
> Add device tree bindings for display clock controller for
> Qualcomm Technology Inc's SM8350 SoC.
>
> Signed-off-by: Robert Foss <[email protected]>
> ---
> .../bindings/clock/qcom,dispcc-sm8x50.yaml | 6 +-
> .../dt-bindings/clock/qcom,dispcc-sm8350.h | 77 +++++++++++++++++++
> 2 files changed, 81 insertions(+), 2 deletions(-)
> create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8350.h
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
> index 0cdf53f41f84..c10eefd024f6 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
> @@ -4,24 +4,26 @@
> $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
> $schema: http://devicetree.org/meta-schemas/core.yaml#
>
> -title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250
> +title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350
>
> maintainers:
> - Jonathan Marek <[email protected]>
>
> description: |
> Qualcomm display clock control module which supports the clocks, resets and
> - power domains on SM8150 and SM8250.
> + power domains on SM8150, SM8250 and SM8350.
>
> See also:
> dt-bindings/clock/qcom,dispcc-sm8150.h
> dt-bindings/clock/qcom,dispcc-sm8250.h
> + dt-bindings/clock/qcom,dispcc-sm8350.h
>
> properties:
> compatible:
> enum:
> - qcom,sm8150-dispcc
> - qcom,sm8250-dispcc
> + - qcom,sm8350-dispcc
>
> clocks:
> items:
> diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8350.h b/include/dt-bindings/clock/qcom,dispcc-sm8350.h
> new file mode 100644
> index 000000000000..361ef27de585
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,dispcc-sm8350.h
> @@ -0,0 +1,77 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
I'm tired of saying this for QCom bindings given it's been QCom I've
gotten complaints on DT licensing, but dual license please. Spread the
word.
I'm sure if someone audited licenses of headers and dts files they'd
find a mess.
Rob
On Thu, 24 Jun 2021 at 23:18, Rob Herring <[email protected]> wrote:
>
> On Wed, Jun 16, 2021 at 04:11:01PM +0200, Robert Foss wrote:
> > Add device tree bindings for display clock controller for
> > Qualcomm Technology Inc's SM8350 SoC.
> >
> > Signed-off-by: Robert Foss <[email protected]>
> > ---
> > .../bindings/clock/qcom,dispcc-sm8x50.yaml | 6 +-
> > .../dt-bindings/clock/qcom,dispcc-sm8350.h | 77 +++++++++++++++++++
> > 2 files changed, 81 insertions(+), 2 deletions(-)
> > create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8350.h
> >
> > diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
> > index 0cdf53f41f84..c10eefd024f6 100644
> > --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
> > +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
> > @@ -4,24 +4,26 @@
> > $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
> > $schema: http://devicetree.org/meta-schemas/core.yaml#
> >
> > -title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250
> > +title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350
> >
> > maintainers:
> > - Jonathan Marek <[email protected]>
> >
> > description: |
> > Qualcomm display clock control module which supports the clocks, resets and
> > - power domains on SM8150 and SM8250.
> > + power domains on SM8150, SM8250 and SM8350.
> >
> > See also:
> > dt-bindings/clock/qcom,dispcc-sm8150.h
> > dt-bindings/clock/qcom,dispcc-sm8250.h
> > + dt-bindings/clock/qcom,dispcc-sm8350.h
> >
> > properties:
> > compatible:
> > enum:
> > - qcom,sm8150-dispcc
> > - qcom,sm8250-dispcc
> > + - qcom,sm8350-dispcc
> >
> > clocks:
> > items:
> > diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8350.h b/include/dt-bindings/clock/qcom,dispcc-sm8350.h
> > new file mode 100644
> > index 000000000000..361ef27de585
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/qcom,dispcc-sm8350.h
> > @@ -0,0 +1,77 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
>
> I'm tired of saying this for QCom bindings given it's been QCom I've
> gotten complaints on DT licensing, but dual license please. Spread the
> word.
>
> I'm sure if someone audited licenses of headers and dts files they'd
> find a mess.
Thanks for pointing this out. I'll keep an eye out and change it to
(GPL-2.0-only OR BSD-2-Clause).