This series support MIPI DSI on i.MX8MM.
It worked directly with existing mxsfb driver but the SEC DSIM
timings has to be validate and tested through all platforms,
ie reason I'm sending it as RFC.
Tested on Engicam i.Core MX8M Mini SoM.
patch 1: dt-bindings for SEC MIPI DSIM
patch 2: SEC MIPI DSIM bridge driver
patch 3: dt-bindings for SEC DSIM DPHY
patch 4: SEC DSIM DPHY driver
patch 5: MIPI DPHY reset enable in blk-ctl
patch 6: display mix blk ctl node
patch 7: eLCDIF node
patch 8: MIPI DSI pipeline nodes
patch 9: Enable LVDS panel on EDIMM2.2
Note:
- all these patches on top of Peng Fan's blk-ctl driver.
- anyone interest, please have a look on this repo
https://github.com/openedev/linux/commits/imx8mm
Any inputs?
Jagan.
Jagan Teki (9):
dt-bindings: display: bridge: Add Samsung SEC MIPI DSIM bindings
drm: bridge: Add Samsung SEC MIPI DSIM bridge driver
dt-bindings: phy: Add SEC DSIM DPHY bindings
phy: samsung: Add SEC DSIM DPHY driver
soc: imx8mm: blk-ctl: Add MIPI DPHY reset enable
arm64: dts: imx8mm: Add display mix blk ctl
arm64: dts: imx8mm: Add eLCDIF node support
arm64: dts: imx8mm: Add MIPI DSI pipeline
arm64: dts: imx8mm-icore: Enable LVDS panel for EDIMM2.2
.../display/bridge/samsung,sec-dsim.yaml | 184 ++
.../bindings/phy/samsung,sec-dsim-dphy.yaml | 56 +
.../freescale/imx8mm-icore-mx8mm-edimm2.2.dts | 90 +
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 104 ++
drivers/gpu/drm/bridge/Kconfig | 15 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/sec-dsim.c | 1535 +++++++++++++++++
drivers/phy/samsung/Kconfig | 9 +
drivers/phy/samsung/Makefile | 1 +
drivers/phy/samsung/phy-sec-dsim-dphy.c | 236 +++
drivers/soc/imx/blk-ctl-imx8mm.c | 4 +
include/dt-bindings/power/imx8mm-power.h | 5 +-
12 files changed, 2238 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/bridge/samsung,sec-dsim.yaml
create mode 100644 Documentation/devicetree/bindings/phy/samsung,sec-dsim-dphy.yaml
create mode 100644 drivers/gpu/drm/bridge/sec-dsim.c
create mode 100644 drivers/phy/samsung/phy-sec-dsim-dphy.c
--
2.25.1
Samsung SEC MIPI DSIM Bridge controller is MIPI DSI bridge
available in NXP's i.MX8M Mini and Nano Processors.
Add bridge driver for it.
Cc: Andrzej Hajda <[email protected]>
Cc: Neil Armstrong <[email protected]>
Cc: Robert Foss <[email protected]>
Cc: Laurent Pinchart <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
---
drivers/gpu/drm/bridge/Kconfig | 15 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/sec-dsim.c | 1535 +++++++++++++++++++++++++++++
3 files changed, 1551 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/sec-dsim.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 19109c0b5481..a183eb165a35 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -189,6 +189,21 @@ config DRM_PARADE_PS8640
The PS8640 is a high-performance and low-power
MIPI DSI to eDP converter
+config DRM_SEC_MIPI_DSIM
+ tristate "Samsung SEC MIPI DSIM Bridge controller"
+ depends on DRM
+ depends on COMMON_CLK
+ depends on OF && HAS_IOMEM
+ select DRM_KMS_HELPER
+ select DRM_MIPI_DSI
+ select DRM_PANEL_BRIDGE
+ select GENERIC_PHY_MIPI_DPHY
+ select MFD_SYSCON
+ select REGMAP_MMIO
+ help
+ This enables the Samsung SEC MIPI DSIM Bridge controller as
+ for example found on NXP's i.MX8M Mini and Nano Processors.
+
config DRM_SIL_SII8620
tristate "Silicon Image SII8620 HDMI/MHL bridge"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 88e4edf81087..ff802a4ffe65 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW) += megachips-stdpxxxx-ge-b850v
obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o
+obj-$(CONFIG_DRM_SEC_MIPI_DSIM) += sec-dsim.o
obj-$(CONFIG_DRM_SIL_SII8620) += sil-sii8620.o
obj-$(CONFIG_DRM_SII902X) += sii902x.o
obj-$(CONFIG_DRM_SII9234) += sii9234.o
diff --git a/drivers/gpu/drm/bridge/sec-dsim.c b/drivers/gpu/drm/bridge/sec-dsim.c
new file mode 100644
index 000000000000..5b6645bb94e7
--- /dev/null
+++ b/drivers/gpu/drm/bridge/sec-dsim.c
@@ -0,0 +1,1535 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Samsung SEC MIPI DSIM Bridge
+ *
+ * Copyright (C) 2018 NXP
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd
+ * Copyright (C) 2021 Amarula Solutions(India)
+ *
+ * Based on the drivers/gpu/drm/exynos/exynos_drm_dsi.c
+ *
+ * Authors:
+ * Tomasz Figa <[email protected]>
+ * Andrzej Hajda <[email protected]>
+ * Fancy Fang <[email protected]>
+ * Jagan Teki <[email protected]>
+ */
+
+#include <asm/unaligned.h>
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_graph.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_of.h>
+#include <drm/drm_print.h>
+
+#include <video/mipi_display.h>
+
+#define DRIVER_NAME "sec-dsim"
+
+/* dsim registers */
+#define DSIM_VERSION 0x00
+#define DSIM_STATUS 0x04
+#define DSIM_RGB_STATUS 0x08
+#define DSIM_SWRST 0x0c
+#define DSIM_CLKCTRL 0x10
+#define DSIM_TIMEOUT 0x14
+#define DSIM_CONFIG 0x18
+#define DSIM_ESCMODE 0x1c
+#define DSIM_MDRESOL 0x20
+#define DSIM_MVPORCH 0x24
+#define DSIM_MHPORCH 0x28
+#define DSIM_MSYNC 0x2c
+#define DSIM_SDRESOL 0x30
+#define DSIM_INTSRC 0x34
+#define DSIM_INTMSK 0x38
+#define DSIM_PKTHDR 0x3c
+#define DSIM_PAYLOAD 0x40
+#define DSIM_RXFIFO 0x44
+#define DSIM_FIFOTHLD 0x48
+#define DSIM_FIFOCTRL 0x4c
+#define DSIM_MEMACCHR 0x50
+#define DSIM_MULTI_PKT 0x78
+#define DSIM_PLLCTRL_1G 0x90
+#define DSIM_PLLCTRL 0x94
+#define DSIM_PLLCTRL1 0x98
+#define DSIM_PLLCTRL2 0x9c
+#define DSIM_PLLTMR 0xa0
+
+/* register bit fields */
+#define STATUS_PLLSTABLE BIT(31)
+#define STATUS_SWRSTRLS BIT(20)
+#define STATUS_TXREADYHSCLK BIT(10)
+#define STATUS_ULPSCLK BIT(9)
+#define STATUS_STOPSTATECLK BIT(8)
+
+#define CLKCTRL_TXREQUESTHSCLK BIT(31)
+#define CLKCTRL_ESCCLKEN BIT(28)
+#define CLKCTRL_PLLBYPASS BIT(27)
+#define CLKCTRL_BYTECLKSRC_MASK GENMASK(26, 25)
+#define CLKCTRL_BYTECLKSRC(x) FIELD_PREP(CLKCTRL_BYTECLKSRC_MASK, (x))
+#define CLKCTRL_BYTECLKEN BIT(24)
+#define CLKCTRL_LANEESCDATAEN_MASK GENMASK(23, 20)
+#define CLKCTRL_LANEESCDATAEN(x) FIELD_PREP(CLKCTRL_LANEESCDATAEN_MASK, (x))
+#define CLKCTRL_LANEESCCLKEN BIT(19)
+#define CLKCTRL_ESCPRESCALER_MASK GENMASK(15, 0)
+#define CLKCTRL_ESCPRESCALER(x) FIELD_PREP(CLKCTRL_ESCPRESCALER_MASK, (x))
+
+#define TIMEOUT_BTAOUT_MASK GENMASK(23, 16)
+#define TIMEOUT_BTAOUT(x) FIELD_PREP(TIMEOUT_BTAOUT_MASK, (x))
+#define TIMEOUT_LPDRTOUT_MASK GENMASK(15, 0)
+#define TIMEOUT_LPDRTOUT(x) FIELD_PREP(TIMEOUT_LPDRTOUT_MASK, (x))
+
+#define CONFIG_NON_CONTINUOUS_CLOCK_LANE BIT(31)
+#define CONFIG_CLKLANE_STOP_START BIT(30)
+#define CONFIG_MFLUSH_VS BIT(29)
+#define CONFIG_EOT_R03 BIT(28)
+#define CONFIG_SYNCINFORM BIT(27)
+#define CONFIG_BURSTMODE BIT(26)
+#define CONFIG_VIDEOMODE BIT(25)
+#define CONFIG_AUTOMODE BIT(24)
+#define CONFIG_HSEDISABLEMODE BIT(23)
+#define CONFIG_HFPDISABLEMODE BIT(22)
+#define CONFIG_HBPDISABLEMODE BIT(21)
+#define CONFIG_HSADISABLEMODE BIT(20)
+
+#define CONFIG_MAINPIXFORMAT_MASK GENMASK(14, 12)
+#define CONFIG_MAINPIXFORMAT(x) FIELD_PREP(CONFIG_MAINPIXFORMAT_MASK, (x))
+#define CONFIG_NUMOFDATLANE_MASK GENMASK(6, 5)
+#define CONFIG_NUMOFDATLANE(x) FIELD_PREP(CONFIG_NUMOFDATLANE_MASK, (x))
+#define CONFIG_LANEEN_MASK GENMASK(4, 0)
+#define CONFIG_LANEEN(x) FIELD_PREP(GENMASK(4, 1), (x))
+#define CONFIG_CLKLANEEN BIT(0)
+
+#define ESCMODE_STOPSTATE_CN_MASK GENMASK(31, 21)
+#define ESCMODE_STOPSTATE_CN(x) FIELD_PREP(ESCMODE_STOPSTATE_CN_MASK, (x))
+#define ESCMODE_CMDLPDT BIT(7)
+
+#define MDRESOL_MAINSTANDBY BIT(31)
+#define MVPORCH_MAINVRESOL_MASK GENMASK(27, 16)
+#define MVPORCH_MAINVRESOL(x) FIELD_PREP(MVPORCH_MAINVRESOL_MASK, (x))
+#define MVPORCH_MAINHRESOL_MASK GENMASK(11, 0)
+#define MVPORCH_MAINHRESOL(x) FIELD_PREP(MVPORCH_MAINHRESOL_MASK, (x))
+#define MVPORCH_CMDALLOW_MASK GENMASK(31, 28)
+#define MVPORCH_CMDALLOW(x) FIELD_PREP(MVPORCH_CMDALLOW_MASK, (x))
+#define MVPORCH_STABLEVFP_MASK GENMASK(26, 16)
+#define MVPORCH_STABLEVFP(x) FIELD_PREP(MVPORCH_STABLEVFP_MASK, (x))
+#define MVPORCH_MAINVBP_MASK GENMASK(10, 0)
+#define MVPORCH_MAINVBP(x) FIELD_PREP(MVPORCH_MAINVBP_MASK, (x))
+#define MVPORCH_MAINHFP_MASK GENMASK(31, 16)
+#define MVPORCH_MAINHFP(x) FIELD_PREP(MVPORCH_MAINHFP_MASK, (x))
+#define MVPORCH_MAINHBP_MASK GENMASK(15, 0)
+#define MVPORCH_MAINHBP(x) FIELD_PREP(MVPORCH_MAINHBP_MASK, (x))
+#define MVPORCH_MAINVSA_MASK GENMASK(31, 22)
+#define MVPORCH_MAINVSA(x) FIELD_PREP(MVPORCH_MAINVSA_MASK, (x))
+#define MVPORCH_MAINHSA_MASK GENMASK(15, 0)
+#define MVPORCH_MAINHSA(x) FIELD_PREP(MVPORCH_MAINHSA_MASK, (x))
+
+#define INTSRC_PLLSTABLE BIT(31)
+#define INTSRC_SWRSTRELEASE BIT(30)
+#define INTSRC_SFRPLFIFOEMPTY BIT(29)
+#define INTSRC_SFRPHFIFOEMPTY BIT(28)
+#define INTSRC_FRAMEDONE BIT(24)
+#define INTSRC_LPDRTOUT BIT(21)
+#define INTSRC_TATOUT BIT(20)
+#define INTSRC_RXDATDONE BIT(18)
+#define INTSRC_RXTE BIT(17)
+#define INTSRC_RXACK BIT(16)
+#define INTSRC_MASK (INTSRC_PLLSTABLE | \
+ INTSRC_SWRSTRELEASE | \
+ INTSRC_SFRPLFIFOEMPTY | \
+ INTSRC_SFRPHFIFOEMPTY | \
+ INTSRC_FRAMEDONE | \
+ INTSRC_LPDRTOUT | \
+ INTSRC_TATOUT | \
+ INTSRC_RXDATDONE | \
+ INTSRC_RXTE | \
+ INTSRC_RXACK)
+
+#define INTMSK_MSKPLLSTABLE BIT(31)
+#define INTMSK_MSKSWRELEASE BIT(30)
+#define INTMSK_MSKSFRPLFIFOEMPTY BIT(29)
+#define INTMSK_MSKSFRPHFIFOEMPTY BIT(28)
+#define INTMSK_MSKFRAMEDONE BIT(24)
+#define INTMSK_MSKLPDRTOUT BIT(21)
+#define INTMSK_MSKTATOUT BIT(20)
+#define INTMSK_MSKRXDATDONE BIT(18)
+#define INTMSK_MSKRXTE BIT(17)
+#define INTMSK_MSKRXACK BIT(16)
+
+#define PKTHDR_DATA1_MASK GENMASK(23, 16)
+#define PKTHDR_DATA1(x) FIELD_PREP(PKTHDR_DATA1_MASK, (x))
+#define PKTHDR_DATA1_GET(x) FIELD_GET(PKTHDR_DATA1_MASK, (x))
+#define PKTHDR_WC_MASK GENMASK(23, 8)
+#define PKTHDR_WC_GET(x) FIELD_GET(PKTHDR_WC_MASK, (x))
+#define PKTHDR_DATA0_MASK GENMASK(15, 8)
+#define PKTHDR_DATA0(x) FIELD_PREP(PKTHDR_DATA0_MASK, (x))
+#define PKTHDR_DATA0_GET(x) FIELD_GET(PKTHDR_DATA0_MASK, (x))
+#define PKTHDR_DI_MASK GENMASK(7, 0)
+#define PKTHDR_DI(x) FIELD_PREP(PKTHDR_DI_MASK, (x))
+#define PKTHDR_DT_MASK GENMASK(5, 0)
+#define PKTHDR_DT_GET(x) FIELD_GET(PKTHDR_DT_MASK, (x))
+
+#define FIFOCTRL_FULLRX BIT(25)
+#define FIFOCTRL_EMPTYRX BIT(24)
+#define FIFOCTRL_FULLHSFR BIT(23)
+#define FIFOCTRL_EMPTYHSFR BIT(22)
+#define FIFOCTRL_FULLLSFR BIT(21)
+#define FIFOCTRL_EMPTYLSFR BIT(20)
+#define FIFOCTRL_FULLHMAIN BIT(11)
+#define FIFOCTRL_EMPTYHMAIN BIT(10)
+#define FIFOCTRL_FULLLMAIN BIT(9)
+#define FIFOCTRL_EMPTYLMAIN BIT(8)
+#define FIFOCTRL_NINITRX BIT(4)
+#define FIFOCTRL_NINITSFR BIT(3)
+#define FIFOCTRL_NINITI80 BIT(2)
+#define FIFOCTRL_NINITSUB BIT(1)
+#define FIFOCTRL_NINITMAIN BIT(0)
+#define FIFOCTRL_INIT_MASK GENMASK(4, 0)
+
+#define PLLCTRL_PLLEN BIT(23)
+#define PLLCTRL_PMS_P_MASK GENMASK(18, 14)
+#define PLLCTRL_PMS_P(x) FIELD_PREP(PLLCTRL_PMS_P_MASK, (x))
+#define PLLCTRL_PMS_M_MASK GENMASK(12, 4)
+#define PLLCTRL_PMS_M(x) FIELD_PREP(PLLCTRL_PMS_M_MASK, (x))
+#define PLLCTRL_PMS_S_MASK GENMASK(2, 1)
+#define PLLCTRL_PMS_S(x) FIELD_PREP(PLLCTRL_PMS_S_MASK, (x))
+
+/* dsim all irqs index */
+#define PLLSTABLE 1
+#define SWRSTRELEASE 2
+#define SFRPLFIFOEMPTY 3
+#define SFRPHFIFOEMPTY 4
+#define SYNCOVERRIDE 5
+#define BUSTURNOVER 6
+#define FRAMEDONE 7
+#define LPDRTOUT 8
+#define TATOUT 9
+#define RXDATDONE 10
+#define RXTE 11
+#define RXACK 12
+#define ERRRXECC 13
+#define ERRRXCRC 14
+#define ERRESC3 15
+#define ERRESC2 16
+#define ERRESC1 17
+#define ERRESC0 18
+#define ERRSYNC3 19
+#define ERRSYNC2 20
+#define ERRSYNC1 21
+#define ERRSYNC0 22
+#define ERRCONTROL3 23
+#define ERRCONTROL2 24
+#define ERRCONTROL1 25
+#define ERRCONTROL0 26
+
+#define MIPI_FIFO_TIMEOUT msecs_to_jiffies(250)
+
+#define DSIM_HFP_PKT_OVERHEAD 6
+#define DSIM_HBP_PKT_OVERHEAD 6
+#define DSIM_HSA_PKT_OVERHEAD 6
+
+struct sec_dsim_plat_data {
+ unsigned int version;
+ unsigned int pll_timer;
+ unsigned int max_freq_hz;
+ unsigned int esc_stop_state_cnt;
+};
+
+struct sec_dsim {
+ struct mipi_dsi_host host;
+ struct drm_bridge bridge;
+ struct drm_bridge *panel_bridge;
+ struct device *dev;
+
+ struct clk *clk_phy_ref;
+ struct clk *clk_bus;
+ struct phy *phy;
+
+ struct regmap *regmap;
+ struct drm_display_mode mode;
+ int irq;
+ unsigned int pll_clk_hz;
+ unsigned int burst_clk_hz;
+ unsigned int esc_clk_hz;
+ unsigned int lanes;
+ unsigned int channel;
+ enum mipi_dsi_pixel_format format;
+ unsigned long mode_flags;
+
+ struct completion pll_stable;
+ struct completion ph_tx_done;
+ struct completion pl_tx_done;
+ struct completion rx_done;
+ const struct sec_dsim_plat_data *pdata;
+};
+
+static const struct regmap_config sec_dsim_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = DSIM_PLLTMR,
+ .name = DRIVER_NAME,
+};
+
+static inline struct sec_dsim *host_to_dsim(struct mipi_dsi_host *host)
+{
+ return container_of(host, struct sec_dsim, host);
+}
+
+static inline struct sec_dsim *bridge_to_dsim(struct drm_bridge *bridge)
+{
+ return container_of(bridge, struct sec_dsim, bridge);
+}
+
+/* used for CEA standard modes */
+struct dsim_hblank_par {
+ char *name; /* drm display mode name */
+ int vrefresh;
+ int hfp_wc;
+ int hbp_wc;
+ int hsa_wc;
+ int lanes;
+};
+
+#define DSIM_HBLANK_PARAM(nm, vf, hfp, hbp, hsa, num) \
+ .name = (nm), \
+ .vrefresh = (vf), \
+ .hfp_wc = (hfp), \
+ .hbp_wc = (hbp), \
+ .hsa_wc = (hsa), \
+ .lanes = (num)
+
+static const struct dsim_hblank_par hblank_4lanes[] = {
+ /* { 88, 148, 44 } */
+ { DSIM_HBLANK_PARAM("1920x1080", 60, 60, 105, 27, 4), },
+ /* { 528, 148, 44 } */
+ { DSIM_HBLANK_PARAM("1920x1080", 50, 390, 105, 27, 4), },
+ /* { 88, 148, 44 } */
+ { DSIM_HBLANK_PARAM("1920x1080", 30, 60, 105, 27, 4), },
+ /* { 110, 220, 40 } */
+ { DSIM_HBLANK_PARAM("1280x720", 60, 78, 159, 24, 4), },
+ /* { 440, 220, 40 } */
+ { DSIM_HBLANK_PARAM("1280x720", 50, 324, 159, 24, 4), },
+ /* { 16, 60, 62 } */
+ { DSIM_HBLANK_PARAM("720x480", 60, 6, 39, 40, 4), },
+ /* { 12, 68, 64 } */
+ { DSIM_HBLANK_PARAM("720x576", 50, 3, 45, 42, 4), },
+ /* { 16, 48, 96 } */
+ { DSIM_HBLANK_PARAM("640x480", 60, 6, 30, 66, 4), },
+};
+
+static const struct dsim_hblank_par hblank_2lanes[] = {
+ /* { 88, 148, 44 } */
+ { DSIM_HBLANK_PARAM("1920x1080", 30, 114, 210, 60, 2), },
+ /* { 110, 220, 40 } */
+ { DSIM_HBLANK_PARAM("1280x720", 60, 159, 320, 40, 2), },
+ /* { 440, 220, 40 } */
+ { DSIM_HBLANK_PARAM("1280x720", 50, 654, 320, 40, 2), },
+ /* { 16, 60, 62 } */
+ { DSIM_HBLANK_PARAM("720x480", 60, 16, 66, 88, 2), },
+ /* { 12, 68, 64 } */
+ { DSIM_HBLANK_PARAM("720x576", 50, 12, 96, 72, 2), },
+ /* { 16, 48, 96 } */
+ { DSIM_HBLANK_PARAM("640x480", 60, 18, 66, 138, 2), },
+};
+
+static
+const struct dsim_hblank_par *sec_dsim_get_hblank_par(struct sec_dsim *dsim)
+{
+ struct drm_display_mode *mode = &dsim->mode;
+ const struct dsim_hblank_par *hpar, *hblank;
+ int i, size;
+
+ if (unlikely(!mode->name))
+ return NULL;
+
+ switch (dsim->lanes) {
+ case 2:
+ hblank = hblank_2lanes;
+ size = ARRAY_SIZE(hblank_2lanes);
+ break;
+ case 4:
+ hblank = hblank_4lanes;
+ size = ARRAY_SIZE(hblank_4lanes);
+ break;
+ default:
+ DRM_DEV_ERROR(dsim->dev,
+ "No hblank data for mode %s with %d lanes\n",
+ mode->name, dsim->lanes);
+ return NULL;
+ }
+
+ for (i = 0; i < size; i++) {
+ hpar = &hblank[i];
+
+ if (!strcmp(mode->name, hpar->name)) {
+ if (drm_mode_vrefresh(mode) != hpar->vrefresh)
+ continue;
+
+ /* found */
+ return hpar;
+ }
+ }
+
+ return NULL;
+}
+
+static void dsim_write(struct sec_dsim *dsim, unsigned int reg, u32 val)
+{
+ int ret;
+
+ ret = regmap_write(dsim->regmap, reg, val);
+ if (ret < 0)
+ DRM_DEV_ERROR(dsim->dev,
+ "failed to write sec dsim reg 0x%x: %d\n",
+ reg, ret);
+}
+
+static u32 dsim_read(struct sec_dsim *dsim, u32 reg)
+{
+ unsigned int val;
+ int ret;
+
+ ret = regmap_read(dsim->regmap, reg, &val);
+ if (ret < 0)
+ DRM_DEV_ERROR(dsim->dev,
+ "failed to read sec dsim reg 0x%x: %d\n",
+ reg, ret);
+
+ return val;
+}
+
+static void __maybe_unused sec_dsim_irq_mask(struct sec_dsim *dsim,
+ int irq_idx)
+{
+ uint32_t intmsk;
+
+ intmsk = dsim_read(dsim, DSIM_INTMSK);
+
+ switch (irq_idx) {
+ case PLLSTABLE:
+ intmsk |= INTMSK_MSKPLLSTABLE;
+ break;
+ case SWRSTRELEASE:
+ intmsk |= INTMSK_MSKSWRELEASE;
+ break;
+ case SFRPLFIFOEMPTY:
+ intmsk |= INTMSK_MSKSFRPLFIFOEMPTY;
+ break;
+ case SFRPHFIFOEMPTY:
+ intmsk |= INTMSK_MSKSFRPHFIFOEMPTY;
+ break;
+ case FRAMEDONE:
+ intmsk |= INTMSK_MSKFRAMEDONE;
+ break;
+ case LPDRTOUT:
+ intmsk |= INTMSK_MSKLPDRTOUT;
+ break;
+ case TATOUT:
+ intmsk |= INTMSK_MSKTATOUT;
+ break;
+ case RXDATDONE:
+ intmsk |= INTMSK_MSKRXDATDONE;
+ break;
+ case RXTE:
+ intmsk |= INTMSK_MSKRXTE;
+ break;
+ case RXACK:
+ intmsk |= INTMSK_MSKRXACK;
+ break;
+ default:
+ /* unsupported irq */
+ return;
+ }
+
+ dsim_write(dsim, DSIM_INTMSK, intmsk);
+}
+
+static void sec_dsim_irq_unmask(struct sec_dsim *dsim,
+ int irq_idx)
+{
+ uint32_t intmsk;
+
+ intmsk = dsim_read(dsim, DSIM_INTMSK);
+
+ switch (irq_idx) {
+ case PLLSTABLE:
+ intmsk &= ~INTMSK_MSKPLLSTABLE;
+ break;
+ case SWRSTRELEASE:
+ intmsk &= ~INTMSK_MSKSWRELEASE;
+ break;
+ case SFRPLFIFOEMPTY:
+ intmsk &= ~INTMSK_MSKSFRPLFIFOEMPTY;
+ break;
+ case SFRPHFIFOEMPTY:
+ intmsk &= ~INTMSK_MSKSFRPHFIFOEMPTY;
+ break;
+ case FRAMEDONE:
+ intmsk &= ~INTMSK_MSKFRAMEDONE;
+ break;
+ case LPDRTOUT:
+ intmsk &= ~INTMSK_MSKLPDRTOUT;
+ break;
+ case TATOUT:
+ intmsk &= ~INTMSK_MSKTATOUT;
+ break;
+ case RXDATDONE:
+ intmsk &= ~INTMSK_MSKRXDATDONE;
+ break;
+ case RXTE:
+ intmsk &= ~INTMSK_MSKRXTE;
+ break;
+ case RXACK:
+ intmsk &= ~INTMSK_MSKRXACK;
+ break;
+ default:
+ /* unsupported irq */
+ return;
+ }
+
+ dsim_write(dsim, DSIM_INTMSK, intmsk);
+}
+
+/* write 1 clear irq */
+static void sec_dsim_irq_clear(struct sec_dsim *dsim,
+ int irq_idx)
+{
+ uint32_t intsrc = 0;
+
+ switch (irq_idx) {
+ case PLLSTABLE:
+ intsrc |= INTSRC_PLLSTABLE;
+ break;
+ case SWRSTRELEASE:
+ intsrc |= INTSRC_SWRSTRELEASE;
+ break;
+ case SFRPLFIFOEMPTY:
+ intsrc |= INTSRC_SFRPLFIFOEMPTY;
+ break;
+ case SFRPHFIFOEMPTY:
+ intsrc |= INTSRC_SFRPHFIFOEMPTY;
+ break;
+ case FRAMEDONE:
+ intsrc |= INTSRC_FRAMEDONE;
+ break;
+ case LPDRTOUT:
+ intsrc |= INTSRC_LPDRTOUT;
+ break;
+ case TATOUT:
+ intsrc |= INTSRC_TATOUT;
+ break;
+ case RXDATDONE:
+ intsrc |= INTSRC_RXDATDONE;
+ break;
+ case RXTE:
+ intsrc |= INTSRC_RXTE;
+ break;
+ case RXACK:
+ intsrc |= INTSRC_RXACK;
+ break;
+ default:
+ /* unsupported irq */
+ return;
+ }
+
+ dsim_write(dsim, DSIM_INTSRC, intsrc);
+}
+
+static void sec_dsim_irq_init(struct sec_dsim *dsim)
+{
+ sec_dsim_irq_unmask(dsim, PLLSTABLE);
+ sec_dsim_irq_unmask(dsim, SWRSTRELEASE);
+}
+
+static irqreturn_t sec_dsim_irq_handler(int irq, void *data)
+{
+ uint32_t intsrc, status;
+ struct sec_dsim *dsim = data;
+
+ intsrc = dsim_read(dsim, DSIM_INTSRC);
+ status = dsim_read(dsim, DSIM_STATUS);
+
+ if (WARN_ON(!intsrc)) {
+ DRM_DEV_ERROR(dsim->dev, "interrupt is not from dsim\n");
+ return IRQ_NONE;
+ }
+
+ if (WARN_ON(!(intsrc & INTSRC_MASK))) {
+ dev_warn(dsim->dev, "unenable irq happens: %#x\n", intsrc);
+ /* just clear irqs */
+ dsim_write(dsim, DSIM_INTSRC, intsrc);
+ return IRQ_NONE;
+ }
+
+ if (intsrc & INTSRC_PLLSTABLE) {
+ WARN_ON(!(status & STATUS_PLLSTABLE));
+ sec_dsim_irq_clear(dsim, PLLSTABLE);
+ complete(&dsim->pll_stable);
+ }
+
+ if (intsrc & INTSRC_SWRSTRELEASE)
+ sec_dsim_irq_clear(dsim, SWRSTRELEASE);
+
+ if (intsrc & INTSRC_SFRPLFIFOEMPTY) {
+ sec_dsim_irq_clear(dsim, SFRPLFIFOEMPTY);
+ complete(&dsim->pl_tx_done);
+ }
+
+ if (intsrc & INTSRC_SFRPHFIFOEMPTY) {
+ sec_dsim_irq_clear(dsim, SFRPHFIFOEMPTY);
+ complete(&dsim->ph_tx_done);
+ }
+
+ if (WARN_ON(intsrc & INTSRC_LPDRTOUT)) {
+ sec_dsim_irq_clear(dsim, LPDRTOUT);
+ dev_warn(dsim->dev, "LP RX timeout\n");
+ }
+
+ if (WARN_ON(intsrc & INTSRC_TATOUT)) {
+ sec_dsim_irq_clear(dsim, TATOUT);
+ dev_warn(dsim->dev, "Turns around Acknowledge timeout\n");
+ }
+
+ if (intsrc & INTSRC_RXDATDONE) {
+ sec_dsim_irq_clear(dsim, RXDATDONE);
+ complete(&dsim->rx_done);
+ }
+
+ if (intsrc & INTSRC_RXTE) {
+ sec_dsim_irq_clear(dsim, RXTE);
+ DRM_DEV_DEBUG(dsim->dev, "TE Rx trigger received\n");
+ }
+
+ if (intsrc & INTSRC_RXACK) {
+ sec_dsim_irq_clear(dsim, RXACK);
+ DRM_DEV_DEBUG(dsim->dev, "ACK Rx trigger received\n");
+ }
+
+ return IRQ_HANDLED;
+}
+
+static void sec_dsim_config_cmd_lpm(struct sec_dsim *dsim, bool enable)
+{
+ u32 reg;
+
+ reg = dsim_read(dsim, DSIM_ESCMODE);
+
+ if (enable)
+ reg |= ESCMODE_CMDLPDT;
+ else
+ reg &= ~ESCMODE_CMDLPDT;
+
+ dsim_write(dsim, DSIM_ESCMODE, reg);
+}
+
+static void sec_dsim_write_pl_to_sfr_fifo(struct sec_dsim *dsim,
+ const void *payload,
+ size_t length)
+{
+ uint32_t pl_data;
+
+ if (!length)
+ return;
+
+ while (length >= 4) {
+ pl_data = get_unaligned_le32(payload);
+ dsim_write(dsim, DSIM_PAYLOAD, pl_data);
+ payload += 4;
+ length -= 4;
+ }
+
+ pl_data = 0;
+ switch (length) {
+ case 3:
+ pl_data |= ((u8 *)payload)[2] << 16;
+ /* fallthrough */
+ case 2:
+ pl_data |= ((u8 *)payload)[1] << 8;
+ /* fallthrough */
+ case 1:
+ pl_data |= ((u8 *)payload)[0];
+ dsim_write(dsim, DSIM_PAYLOAD, pl_data);
+ break;
+ }
+}
+
+static void sec_dsim_write_ph_to_sfr_fifo(struct sec_dsim *dsim,
+ void *header,
+ bool use_lpm)
+{
+ u32 reg;
+
+ reg = dsim_read(dsim, DSIM_PKTHDR);
+
+ reg &= ~PKTHDR_DATA1_MASK;
+ reg |= PKTHDR_DATA1(((u8 *)header)[2]); /* WC MSB */
+ reg &= ~PKTHDR_DATA0_MASK;
+ reg |= PKTHDR_DATA0(((u8 *)header)[1]); /* WC LSB */
+ reg &= ~PKTHDR_DI_MASK;
+ reg |= PKTHDR_DI(((u8 *)header)[0]); /* Data ID */
+ dsim_write(dsim, DSIM_PKTHDR, reg);
+}
+
+static int sec_dsim_read_pl_from_sfr_fifo(struct sec_dsim *dsim,
+ void *payload,
+ size_t length)
+{
+ uint8_t data_type;
+ uint16_t word_count = 0;
+ uint32_t reg, ph, pl;
+
+ reg = dsim_read(dsim, DSIM_FIFOCTRL);
+
+ if (WARN_ON(reg & FIFOCTRL_EMPTYRX))
+ return -EINVAL;
+
+ ph = dsim_read(dsim, DSIM_RXFIFO);
+ data_type = PKTHDR_DT_GET(ph);
+ switch (data_type) {
+ case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
+ DRM_DEV_ERROR(dsim->dev,
+ "peripheral report error: (0-7)%lx, (8-15)%lx\n",
+ PKTHDR_DATA0_GET(ph), PKTHDR_DATA1_GET(ph));
+ return -EPROTO;
+ case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
+ case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
+ if (!WARN_ON(length < 2)) {
+ ((u8 *)payload)[1] = PKTHDR_DATA1_GET(ph);
+ word_count++;
+ }
+ /* fall through */
+ case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
+ case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
+ ((u8 *)payload)[0] = PKTHDR_DATA0_GET(ph);
+ word_count++;
+ length = word_count;
+ break;
+ case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
+ case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
+ word_count = PKTHDR_WC_GET(ph);
+ if (word_count > length) {
+ DRM_DEV_ERROR(dsim->dev, "invalid receive buffer length\n");
+ return -EINVAL;
+ }
+
+ length = word_count;
+
+ while (word_count >= 4) {
+ pl = dsim_read(dsim, DSIM_RXFIFO);
+ ((u8 *)payload)[0] = pl & 0xff;
+ ((u8 *)payload)[1] = (pl >> 8) & 0xff;
+ ((u8 *)payload)[2] = (pl >> 16) & 0xff;
+ ((u8 *)payload)[3] = (pl >> 24) & 0xff;
+ payload += 4;
+ word_count -= 4;
+ }
+
+ if (word_count > 0) {
+ pl = dsim_read(dsim, DSIM_RXFIFO);
+
+ switch (word_count) {
+ case 3:
+ ((u8 *)payload)[2] = (pl >> 16) & 0xff;
+ /* fall through */
+ case 2:
+ ((u8 *)payload)[1] = (pl >> 8) & 0xff;
+ /* fall through */
+ case 1:
+ ((u8 *)payload)[0] = pl & 0xff;
+ break;
+ }
+ }
+
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return length;
+}
+
+static ssize_t sec_dsim_host_transfer(struct mipi_dsi_host *host,
+ const struct mipi_dsi_msg *msg)
+{
+ int ret;
+ bool use_lpm;
+ struct mipi_dsi_packet packet;
+ struct sec_dsim *dsim = host_to_dsim(host);
+
+ if ((msg->rx_buf && !msg->rx_len) || (msg->rx_len && !msg->rx_buf))
+ return -EINVAL;
+
+ ret = mipi_dsi_create_packet(&packet, msg);
+ if (ret) {
+ DRM_DEV_ERROR(dsim->dev, "failed to create dsi packet: %d\n", ret);
+ return ret;
+ }
+
+ /* need to read data from peripheral */
+ if (unlikely(msg->rx_buf))
+ reinit_completion(&dsim->rx_done);
+
+ /* config LPM for CMD TX */
+ use_lpm = msg->flags & MIPI_DSI_MSG_USE_LPM ? true : false;
+ sec_dsim_config_cmd_lpm(dsim, use_lpm);
+
+ if (packet.payload_length) { /* Long Packet case */
+ reinit_completion(&dsim->pl_tx_done);
+
+ /* write packet payload */
+ sec_dsim_write_pl_to_sfr_fifo(dsim,
+ packet.payload,
+ packet.payload_length);
+
+ /* write packet header */
+ sec_dsim_write_ph_to_sfr_fifo(dsim,
+ packet.header,
+ use_lpm);
+
+ ret = wait_for_completion_timeout(&dsim->ph_tx_done,
+ MIPI_FIFO_TIMEOUT);
+ if (!ret) {
+ DRM_DEV_ERROR(dsim->dev, "wait payload tx done time out\n");
+ return -EBUSY;
+ }
+ } else {
+ reinit_completion(&dsim->ph_tx_done);
+
+ /* write packet header */
+ sec_dsim_write_ph_to_sfr_fifo(dsim,
+ packet.header,
+ use_lpm);
+
+ ret = wait_for_completion_timeout(&dsim->ph_tx_done,
+ MIPI_FIFO_TIMEOUT);
+ if (!ret) {
+ DRM_DEV_ERROR(dsim->dev, "wait pkthdr tx done time out\n");
+ return -EBUSY;
+ }
+ }
+
+ /* read packet payload */
+ if (unlikely(msg->rx_buf)) {
+ ret = wait_for_completion_timeout(&dsim->rx_done,
+ MIPI_FIFO_TIMEOUT);
+ if (!ret) {
+ DRM_DEV_ERROR(dsim->dev, "wait rx done time out\n");
+ return -EBUSY;
+ }
+
+ ret = sec_dsim_read_pl_from_sfr_fifo(dsim,
+ msg->rx_buf,
+ msg->rx_len);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int sec_dsim_host_attach(struct mipi_dsi_host *host,
+ struct mipi_dsi_device *device)
+{
+ struct sec_dsim *dsim = host_to_dsim(host);
+
+ dsim->lanes = device->lanes;
+ dsim->channel = device->channel;
+ dsim->format = device->format;
+ dsim->mode_flags = device->mode_flags;
+
+ return 0;
+}
+
+static const struct mipi_dsi_host_ops sec_dsim_host_ops = {
+ .attach = sec_dsim_host_attach,
+ .transfer = sec_dsim_host_transfer,
+};
+
+static void sec_dsim_video_mode(struct sec_dsim *dsim)
+{
+ struct drm_display_mode *mode = &dsim->mode;
+ unsigned int bpp = mipi_dsi_pixel_format_to_bpp(dsim->format);
+ const struct dsim_hblank_par *hpar = NULL;
+ unsigned int hfp, hbp, hsa, vfp, vbp, vsa;
+ unsigned int hfp_wc, hbp_wc, hsa_wc, wc;
+ unsigned int reg;
+
+ hfp = mode->hsync_start - mode->hdisplay;
+ hbp = mode->htotal - mode->hsync_end;
+ hsa = mode->hsync_end - mode->hsync_start;
+ vfp = mode->vsync_start - mode->vdisplay;
+ vbp = mode->vtotal - mode->vsync_end;
+ vsa = mode->vsync_end - mode->vsync_start;
+
+ if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
+ hpar = sec_dsim_get_hblank_par(dsim);
+ if (!hpar)
+ DRM_DEV_DEBUG(dsim->dev,
+ "No pre-exist hpar can be used\n");
+ }
+
+ /* vertical porch */
+ reg = dsim_read(dsim, DSIM_MVPORCH);
+
+ reg &= ~MVPORCH_MAINVBP_MASK;
+ reg |= MVPORCH_MAINVBP(vbp);
+ reg &= ~MVPORCH_STABLEVFP_MASK;
+ reg |= MVPORCH_STABLEVFP(vfp);
+ reg &= ~MVPORCH_CMDALLOW_MASK;
+ reg |= MVPORCH_CMDALLOW(0x0);
+ dsim_write(dsim, DSIM_MVPORCH, reg);
+
+ if (!hpar) {
+ wc = DIV_ROUND_UP(hfp * (bpp >> 3), dsim->lanes);
+ hfp_wc = wc > DSIM_HFP_PKT_OVERHEAD ?
+ wc - DSIM_HFP_PKT_OVERHEAD : hfp;
+ wc = DIV_ROUND_UP(hbp * (bpp >> 3), dsim->lanes);
+ hbp_wc = wc > DSIM_HBP_PKT_OVERHEAD ?
+ wc - DSIM_HBP_PKT_OVERHEAD : hbp;
+ } else {
+ hfp_wc = hpar->hfp_wc;
+ hbp_wc = hpar->hbp_wc;
+ }
+
+ /* horizontal porch */
+ reg = dsim_read(dsim, DSIM_MHPORCH);
+
+ reg &= ~MVPORCH_MAINHBP_MASK;
+ reg |= MVPORCH_MAINHBP(hbp_wc);
+ reg &= ~MVPORCH_MAINHFP_MASK;
+ reg |= MVPORCH_MAINHFP(hfp_wc);
+ dsim_write(dsim, DSIM_MHPORCH, reg);
+
+ if (!hpar) {
+ wc = DIV_ROUND_UP(hsa * (bpp >> 3), dsim->lanes);
+ hsa_wc = wc > DSIM_HSA_PKT_OVERHEAD ?
+ wc - DSIM_HSA_PKT_OVERHEAD : hsa;
+ } else {
+ hsa_wc = hpar->hsa_wc;
+ }
+
+ /* sync area */
+ reg = dsim_read(dsim, DSIM_MSYNC);
+
+ reg &= ~MVPORCH_MAINHSA_MASK;
+ reg |= MVPORCH_MAINHSA(hsa_wc);
+ reg &= ~MVPORCH_MAINVSA_MASK;
+ reg |= MVPORCH_MAINVSA(vsa);
+ dsim_write(dsim, DSIM_MSYNC, reg);
+}
+
+static void sec_dsim_display_mode(struct sec_dsim *dsim)
+{
+ struct drm_display_mode *mode = &dsim->mode;
+ u32 reg;
+
+ if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO)
+ sec_dsim_video_mode(dsim);
+
+ /* image resolution */
+ reg = dsim_read(dsim, DSIM_MDRESOL);
+
+ reg &= ~MVPORCH_MAINHRESOL_MASK;
+ reg |= MVPORCH_MAINHRESOL(mode->hdisplay);
+ reg &= ~MVPORCH_MAINVRESOL_MASK;
+ reg |= MVPORCH_MAINVRESOL(mode->vdisplay);
+
+ dsim_write(dsim, DSIM_MDRESOL, reg);
+}
+
+static void sec_dsim_config_bridge(struct sec_dsim *dsim)
+{
+ const struct sec_dsim_plat_data *pdata = dsim->pdata;
+ u32 reg;
+
+ reg = dsim_read(dsim, DSIM_CONFIG);
+
+ if (dsim->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
+ reg |= CONFIG_NON_CONTINUOUS_CLOCK_LANE;
+ reg |= CONFIG_CLKLANE_STOP_START;
+ }
+
+ if (!(dsim->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
+ reg |= CONFIG_MFLUSH_VS;
+
+ /* disable EoT packets in HS mode */
+ if (!(dsim->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
+ reg |= CONFIG_EOT_R03;
+
+ if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO) {
+ reg |= CONFIG_VIDEOMODE;
+
+ if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
+ reg |= CONFIG_BURSTMODE;
+
+ else if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
+ reg |= CONFIG_SYNCINFORM;
+
+ if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
+ reg |= CONFIG_AUTOMODE;
+
+ if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
+ reg |= CONFIG_HSEDISABLEMODE;
+
+ if (!(dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HFP))
+ reg |= CONFIG_HFPDISABLEMODE;
+
+ if (!(dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HBP))
+ reg |= CONFIG_HBPDISABLEMODE;
+
+ if (!(dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HSA))
+ reg |= CONFIG_HSADISABLEMODE;
+ }
+
+ /* pixel format */
+ reg &= ~CONFIG_MAINPIXFORMAT_MASK;
+ if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO) {
+ switch (dsim->format) {
+ case MIPI_DSI_FMT_RGB565:
+ reg |= CONFIG_MAINPIXFORMAT(0x4);
+ break;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ reg |= CONFIG_MAINPIXFORMAT(0x5);
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ reg |= CONFIG_MAINPIXFORMAT(0x6);
+ break;
+ case MIPI_DSI_FMT_RGB888:
+ reg |= CONFIG_MAINPIXFORMAT(0x7);
+ break;
+ default:
+ reg |= CONFIG_MAINPIXFORMAT(0x7);
+ break;
+ }
+ }
+
+ /* number of data lanes */
+ reg &= ~CONFIG_NUMOFDATLANE_MASK;
+ reg |= CONFIG_NUMOFDATLANE(dsim->lanes - 1);
+
+ /* enable data, clock lane */
+ reg &= ~CONFIG_LANEEN_MASK;
+ reg |= CONFIG_LANEEN(BIT(dsim->lanes) - 1);
+ reg |= CONFIG_CLKLANEEN;
+
+ dsim_write(dsim, DSIM_CONFIG, reg);
+
+ /* escape mode */
+ reg = dsim_read(dsim, DSIM_ESCMODE);
+
+ reg &= ~ESCMODE_STOPSTATE_CN_MASK;
+ reg |= ESCMODE_STOPSTATE_CN(pdata->esc_stop_state_cnt);
+ dsim_write(dsim, DSIM_ESCMODE, reg);
+
+ /* timeout */
+ reg = dsim_read(dsim, DSIM_TIMEOUT);
+
+ reg &= ~TIMEOUT_LPDRTOUT_MASK;
+ reg |= TIMEOUT_LPDRTOUT(0xffff);
+ reg &= ~TIMEOUT_BTAOUT_MASK;
+ reg |= TIMEOUT_BTAOUT(0xff);
+ dsim_write(dsim, DSIM_TIMEOUT, reg);
+}
+
+#ifndef MHZ
+#define MHZ (1000*1000)
+#endif
+
+static unsigned long sec_dsim_pll_find_pms(struct sec_dsim *dsim,
+ unsigned long fin,
+ unsigned long fout,
+ u8 *p, u16 *m, u8 *s)
+{
+ const struct sec_dsim_plat_data *pdata = dsim->pdata;
+ unsigned long best_freq = 0;
+ u32 min_delta = 0xffffffff;
+ u8 p_min, p_max;
+ u8 _p, best_p;
+ u16 _m, best_m;
+ u8 _s, best_s;
+
+ p_min = DIV_ROUND_UP(fin, (12 * MHZ));
+ p_max = fin / (6 * MHZ);
+
+ for (_p = p_min; _p <= p_max; ++_p) {
+ for (_s = 0; _s <= 5; ++_s) {
+ u64 tmp;
+ u32 delta;
+
+ tmp = (u64)fout * (_p << _s);
+ do_div(tmp, fin);
+ _m = tmp;
+ if (_m < 41 || _m > 125)
+ continue;
+
+ tmp = (u64)_m * fin;
+ do_div(tmp, _p);
+ if (tmp < 500 * MHZ || tmp > pdata->max_freq_hz * MHZ)
+ continue;
+
+ tmp = (u64)_m * fin;
+ do_div(tmp, _p << _s);
+
+ delta = abs(fout - tmp);
+ if (delta < min_delta) {
+ best_p = _p;
+ best_m = _m;
+ best_s = _s;
+ min_delta = delta;
+ best_freq = tmp;
+ }
+ }
+ }
+
+ if (best_freq) {
+ *p = best_p;
+ *m = best_m;
+ *s = best_s;
+ }
+
+ return best_freq;
+}
+
+static unsigned long sec_dsim_set_pll(struct sec_dsim *dsim)
+{
+ unsigned long fin, fout, freq;
+ u8 p, s;
+ u16 m;
+ u32 reg;
+
+ fin = dsim->pll_clk_hz;
+ freq = dsim->burst_clk_hz;
+ fout = sec_dsim_pll_find_pms(dsim, fin, freq, &p, &m, &s);
+ if (!fout) {
+ DRM_DEV_ERROR(dsim->dev,
+ "failed to find PLL PMS for requested frequency\n");
+ return 0;
+ }
+ DRM_DEV_DEBUG(dsim->dev,
+ "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
+
+ reg = PLLCTRL_PLLEN | PLLCTRL_PMS_P(p) | PLLCTRL_PMS_M(m) | PLLCTRL_PMS_S(s);
+
+ dsim_write(dsim, DSIM_PLLCTRL, reg);
+
+ regmap_read_poll_timeout(dsim->regmap, DSIM_STATUS, reg,
+ reg & STATUS_PLLSTABLE, 0, 1000);
+ return fout;
+}
+
+static int sec_dsim_enable_clock(struct sec_dsim *dsim)
+{
+ const struct sec_dsim_plat_data *pdata = dsim->pdata;
+ unsigned long hs_clk, byte_clk, esc_clk;
+ unsigned long esc_div;
+ u32 reg;
+
+ /* pll timer */
+ dsim_write(dsim, DSIM_PLLTMR, pdata->pll_timer);
+
+ /* pll control */
+ hs_clk = sec_dsim_set_pll(dsim);
+ if (!hs_clk) {
+ DRM_DEV_ERROR(dsim->dev, "failed to configure DSI PLL\n");
+ return -EFAULT;
+ }
+
+ byte_clk = hs_clk / 8;
+ esc_div = DIV_ROUND_UP(byte_clk, dsim->esc_clk_hz);
+ esc_clk = byte_clk / esc_div;
+
+ if (esc_clk > 20 * MHZ) {
+ ++esc_div;
+ esc_clk = byte_clk / esc_div;
+ }
+
+ DRM_DEV_DEBUG(dsim->dev,
+ "PLL: hs_clk = %lu, byte_clk = %lu, esc_clk = %lu, esc_div = %lu\n",
+ hs_clk, byte_clk, esc_clk, esc_div);
+
+ /* clk control */
+ reg = dsim_read(dsim, DSIM_CLKCTRL);
+
+ reg |= CLKCTRL_TXREQUESTHSCLK;
+ reg |= CLKCTRL_ESCCLKEN;
+ reg &= ~CLKCTRL_PLLBYPASS;
+ reg &= ~CLKCTRL_BYTECLKSRC_MASK;
+ reg |= CLKCTRL_BYTECLKEN;
+ reg &= ~CLKCTRL_LANEESCDATAEN_MASK;
+ reg |= CLKCTRL_LANEESCDATAEN(BIT(dsim->lanes) - 1);
+ reg |= CLKCTRL_LANEESCCLKEN;
+ reg &= ~CLKCTRL_ESCPRESCALER_MASK;
+ reg |= CLKCTRL_ESCPRESCALER(esc_div);
+
+ dsim_write(dsim, DSIM_CLKCTRL, reg);
+
+ return 0;
+}
+
+static void sec_dsim_fifo_enable(struct sec_dsim *dsim, bool enable)
+{
+ u32 reg;
+
+ reg = dsim_read(dsim, DSIM_FIFOCTRL);
+
+ reg &= ~FIFOCTRL_INIT_MASK;
+ dsim_write(dsim, DSIM_FIFOCTRL, reg);
+ udelay(500);
+
+ if (!enable)
+ return;
+
+ reg |= FIFOCTRL_NINITRX |
+ FIFOCTRL_NINITSFR |
+ FIFOCTRL_NINITI80 |
+ FIFOCTRL_NINITSUB |
+ FIFOCTRL_NINITMAIN;
+ dsim_write(dsim, DSIM_FIFOCTRL, reg);
+ udelay(500);
+}
+
+static void sec_dsim_set_display(struct sec_dsim *dsim, bool enable)
+{
+ u32 reg;
+
+ reg = dsim_read(dsim, DSIM_MDRESOL);
+
+ if (enable)
+ reg |= MDRESOL_MAINSTANDBY;
+ else
+ reg &= ~MDRESOL_MAINSTANDBY;
+ dsim_write(dsim, DSIM_MDRESOL, reg);
+}
+
+static void sec_dsim_bridge_enable(struct drm_bridge *bridge)
+{
+ struct sec_dsim *dsim = bridge_to_dsim(bridge);
+ int ret;
+
+ /* enable bridge clocks */
+ clk_prepare_enable(dsim->clk_bus);
+ clk_prepare_enable(dsim->clk_phy_ref);
+
+ /* initialize the irq */
+ sec_dsim_irq_init(dsim);
+
+ /* configure the bridge */
+ sec_dsim_config_bridge(dsim);
+
+ /* enable fifo control */
+ sec_dsim_fifo_enable(dsim, true);
+
+ /* configure the display mode */
+ sec_dsim_display_mode(dsim);
+
+ /* config dsim pll */
+ ret = sec_dsim_enable_clock(dsim);
+ if (ret) {
+ DRM_DEV_ERROR(dsim->dev, "failed to enable clock: %d\n", ret);
+ return;
+ }
+
+ /* power on the dphy */
+ ret = phy_init(dsim->phy);
+ if (ret) {
+ DRM_DEV_ERROR(dsim->dev, "failed to init phy %d\n", ret);
+ return;
+ }
+
+ /* power on the dphy */
+ ret = phy_power_on(dsim->phy);
+ if (ret) {
+ DRM_DEV_ERROR(dsim->dev, "failed to enable phy %d\n", ret);
+ return;
+ }
+
+ /* enable data transfer */
+ sec_dsim_set_display(dsim, true);
+}
+
+static void sec_dsim_disable_clock(struct sec_dsim *dsim)
+{
+ u32 reg;
+
+ /* clk control */
+ reg = dsim_read(dsim, DSIM_CLKCTRL);
+
+ reg &= ~CLKCTRL_TXREQUESTHSCLK;
+ reg &= ~CLKCTRL_BYTECLKEN;
+ reg &= ~CLKCTRL_ESCCLKEN;
+ reg &= ~CLKCTRL_LANEESCDATAEN_MASK;
+ reg &= ~CLKCTRL_LANEESCCLKEN;
+ dsim_write(dsim, DSIM_CLKCTRL, reg);
+
+ /* pll control */
+ reg = dsim_read(dsim, DSIM_PLLCTRL);
+
+ reg &= ~PLLCTRL_PLLEN;
+ dsim_write(dsim, DSIM_PLLCTRL, reg);
+}
+
+static void sec_dsim_bridge_disable(struct drm_bridge *bridge)
+{
+ struct sec_dsim *dsim = bridge_to_dsim(bridge);
+
+ /* disable data transfer */
+ sec_dsim_set_display(dsim, false);
+
+ /* disable bridge clocks */
+ sec_dsim_disable_clock(dsim);
+
+ /* disable fifo control */
+ sec_dsim_fifo_enable(dsim, false);
+
+ /* power off the phy */
+ phy_power_off(dsim->phy);
+
+ /* exit the phy */
+ phy_exit(dsim->phy);
+
+ /* disable bridge clock */
+ clk_disable_unprepare(dsim->clk_phy_ref);
+ clk_disable_unprepare(dsim->clk_bus);
+}
+
+static bool sec_dsim_bridge_mode_fixup(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
+ adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
+
+ return true;
+}
+
+static void sec_dsim_bridge_mode_set(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adjusted_mode)
+{
+ struct sec_dsim *dsim = bridge_to_dsim(bridge);
+
+ drm_mode_copy(&dsim->mode, adjusted_mode);
+}
+
+static int sec_dsim_bridge_attach(struct drm_bridge *bridge,
+ enum drm_bridge_attach_flags flags)
+{
+ struct sec_dsim *dsim = bridge_to_dsim(bridge);
+ struct drm_bridge *panel_bridge;
+ struct drm_panel *panel;
+ int ret;
+
+ ret = drm_of_find_panel_or_bridge(dsim->dev->of_node, 1, 0, &panel,
+ &panel_bridge);
+ if (ret)
+ return ret;
+
+ if (panel) {
+ panel_bridge = drm_panel_bridge_add(panel);
+ if (IS_ERR(panel_bridge))
+ return PTR_ERR(panel_bridge);
+ }
+ dsim->panel_bridge = panel_bridge;
+
+ if (!dsim->panel_bridge)
+ return -EPROBE_DEFER;
+
+ return drm_bridge_attach(bridge->encoder, dsim->panel_bridge, bridge,
+ flags);
+}
+
+static void sec_dsim_bridge_detach(struct drm_bridge *bridge)
+{
+ struct sec_dsim *dsim = bridge_to_dsim(bridge);
+
+ drm_of_panel_bridge_remove(dsim->dev->of_node, 1, 0);
+}
+
+static const struct drm_bridge_funcs sec_dsim_bridge_funcs = {
+ .enable = sec_dsim_bridge_enable,
+ .disable = sec_dsim_bridge_disable,
+ .mode_set = sec_dsim_bridge_mode_set,
+ .mode_fixup = sec_dsim_bridge_mode_fixup,
+ .attach = sec_dsim_bridge_attach,
+ .detach = sec_dsim_bridge_detach,
+};
+
+static const struct drm_bridge_timings sec_dsim_bridge_timings = {
+ .input_bus_flags = DRM_BUS_FLAG_DE_LOW,
+};
+
+static const struct sec_dsim_plat_data imx8mm_mipi_dsim_plat_data = {
+ .version = 0x1060200,
+ .pll_timer = 500,
+ .max_freq_hz = 2100,
+ .esc_stop_state_cnt = 0xf,
+};
+
+static const struct of_device_id sec_dsim_dt_ids[] = {
+ {
+ .compatible = "fsl,imx8mm-sec-dsim",
+ .data = &imx8mm_mipi_dsim_plat_data,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, sec_dsim_dt_ids);
+
+static int sec_dsim_parse_dt(struct sec_dsim *dsim)
+{
+ struct platform_device *pdev = to_platform_device(dsim->dev);
+ struct device *dev = dsim->dev;
+ struct device_node *node = dev->of_node;
+ struct clk *clk;
+ void __iomem *base;
+ u32 value;
+ int irq;
+ int ret;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ dsim->regmap = devm_regmap_init_mmio(dev, base, &sec_dsim_regmap_config);
+ if (IS_ERR(dsim->regmap)) {
+ ret = PTR_ERR(dsim->regmap);
+ DRM_DEV_ERROR(dev, "failed to create sec dsim regmap: %d\n", ret);
+ return ret;
+ }
+
+ dsim->phy = devm_phy_get(dev, "dphy");
+ if (IS_ERR(dsim->phy)) {
+ DRM_DEV_ERROR(dev, "failed to get dsim phy\n");
+ return PTR_ERR(dsim->phy);
+ }
+
+ clk = devm_clk_get(dev, "bus");
+ if (IS_ERR(clk)) {
+ ret = PTR_ERR(clk);
+ DRM_DEV_ERROR(dev, "failed to get bus clock: %d\n", ret);
+ return ret;
+ }
+ dsim->clk_bus = clk;
+
+ clk = devm_clk_get(dev, "phy_ref");
+ if (IS_ERR(clk)) {
+ ret = PTR_ERR(clk);
+ DRM_DEV_ERROR(dev, "failed to get phy_ref clock: %d\n", ret);
+ return ret;
+ }
+ dsim->clk_phy_ref = clk;
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return -ENODEV;
+
+ ret = devm_request_irq(dev, irq, sec_dsim_irq_handler, 0, dev_name(dev), dsim);
+ if (ret) {
+ DRM_DEV_ERROR(dev, "failed to request dsim irq: %d\n", ret);
+ return ret;
+ }
+
+ if (!of_property_read_u32(node, "samsung,pll-clock-frequency", &value))
+ dsim->pll_clk_hz = value;
+
+ if (!of_property_read_u32(node, "samsung,burst-clock-frequency", &value))
+ dsim->burst_clk_hz = value;
+
+ if (!of_property_read_u32(node, "samsung,esc-clock-frequency", &value))
+ dsim->esc_clk_hz = value;
+
+ init_completion(&dsim->pll_stable);
+ init_completion(&dsim->ph_tx_done);
+ init_completion(&dsim->pl_tx_done);
+ init_completion(&dsim->rx_done);
+
+ return 0;
+}
+
+static int sec_dsim_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ const struct of_device_id *of_id;
+ struct sec_dsim *dsim;
+ int version;
+ int ret;
+
+ dsim = devm_kzalloc(dev, sizeof(*dsim), GFP_KERNEL);
+ if (!dsim) {
+ DRM_DEV_ERROR(dev, "failed to allocate dsim\n");
+ return -ENOMEM;
+ }
+
+ of_id = of_match_device(sec_dsim_dt_ids, dev);
+ if (!of_id)
+ return -ENODEV;
+
+ dsim->pdata = of_id->data;
+ dsim->dev = dev;
+
+ ret = sec_dsim_parse_dt(dsim);
+ if (ret) {
+ DRM_DEV_ERROR(dev, "failed to parse dt: %d\n", ret);
+ return ret;
+ }
+
+ version = dsim_read(dsim, DSIM_VERSION);
+ WARN_ON(version != dsim->pdata->version);
+ DRM_DEV_INFO(dev, "DSIM version number is %#x\n", version);
+
+ dsim->host.ops = &sec_dsim_host_ops;
+ dsim->host.dev = dsim->dev;
+
+ ret = mipi_dsi_host_register(&dsim->host);
+ if (ret) {
+ DRM_DEV_ERROR(dev, "failed to register mipi dsi host: %d\n", ret);
+ return ret;
+ }
+
+ dsim->bridge.driver_private = dsim;
+ dsim->bridge.funcs = &sec_dsim_bridge_funcs;
+ dsim->bridge.of_node = dev->of_node;
+ dsim->bridge.timings = &sec_dsim_bridge_timings;
+
+ dev_set_drvdata(dev, dsim);
+
+ drm_bridge_add(&dsim->bridge);
+
+ return 0;
+}
+
+static int sec_dsim_remove(struct platform_device *pdev)
+{
+ struct sec_dsim *dsim = platform_get_drvdata(pdev);
+
+ mipi_dsi_host_unregister(&dsim->host);
+ drm_bridge_remove(&dsim->bridge);
+
+ return 0;
+}
+
+struct platform_driver sec_dsim_driver = {
+ .probe = sec_dsim_probe,
+ .remove = sec_dsim_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = sec_dsim_dt_ids,
+ },
+};
+
+module_platform_driver(sec_dsim_driver);
+
+MODULE_AUTHOR("Jagan Teki <[email protected]>");
+MODULE_DESCRIPTION("Samsung SEC MIPI DSIM Bridge driver");
+MODULE_LICENSE("GPL v2");
--
2.25.1
Samsung SEC MIPI DSIM DPHY controller is part of registers
available in SEC MIPI DSIM bridge for NXP's i.MX8M Mini and
Nano Processors.
Add dt-bingings for it.
Cc: Kishon Vijay Abraham I <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: Rob Herring <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
---
.../bindings/phy/samsung,sec-dsim-dphy.yaml | 56 +++++++++++++++++++
1 file changed, 56 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/samsung,sec-dsim-dphy.yaml
diff --git a/Documentation/devicetree/bindings/phy/samsung,sec-dsim-dphy.yaml b/Documentation/devicetree/bindings/phy/samsung,sec-dsim-dphy.yaml
new file mode 100644
index 000000000000..c5770c8035e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung,sec-dsim-dphy.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/samsung,sec-dsim-dphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SEC MIPI DSIM DPHY controller on i.MX8M Mini and Nano SoCs
+
+maintainers:
+ - Jagan Teki <[email protected]>
+
+properties:
+ "#phy-cells":
+ const: 0
+
+ compatible:
+ enum:
+ - fsl,imx8mm-sec-dsim-dphy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Phy Ref Clock
+
+ clock-names:
+ items:
+ - const: phy_ref
+
+ power-domains:
+ maxItems: 1
+ description: phandle to the associated power domain
+
+required:
+ - "#phy-cells"
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8mm-clock.h>
+ #include <dt-bindings/power/imx8mm-power.h>
+
+ dphy: dphy@32e100a4 {
+ compatible = "fsl,imx8mm-sec-dsim-dphy";
+ reg = <0x32e100a4 0xbc>;
+ clocks = <&clk IMX8MM_CLK_DSI_PHY_REF>;
+ clock-names = "phy_ref";
+ power-domains = <&dispmix_blk_ctl IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_DPHY>;
+ #phy-cells = <0>;
+ };
--
2.25.1
Add eLCDIF controller node for i.MX8MM.
Cc: Rob Herring <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index fe5485ee9419..5f68182ed3a6 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1030,6 +1030,25 @@ aips4: bus@32c00000 {
#size-cells = <1>;
ranges = <0x32c00000 0x32c00000 0x400000>;
+ lcdif: lcdif@32e00000 {
+ compatible = "fsl,imx8mm-lcdif", "fsl,imx6sx-lcdif";
+ reg = <0x32e00000 0x10000>;
+ clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
+ <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MM_CLK_DISP_APB_ROOT>;
+ clock-names = "pix", "disp_axi", "axi";
+ assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
+ <&clk IMX8MM_CLK_DISP_AXI>,
+ <&clk IMX8MM_CLK_DISP_APB>;
+ assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
+ <&clk IMX8MM_SYS_PLL2_1000M>,
+ <&clk IMX8MM_SYS_PLL1_800M>;
+ assigned-clock-rate = <594000000>, <500000000>, <200000000>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&dispmix_blk_ctl IMX8MM_BLK_CTL_PD_DISPMIX_LCDIF>;
+ status = "disabled";
+ };
+
dispmix_blk_ctl: blk-ctl@32e28000 {
compatible = "fsl,imx8mm-dispmix-blk-ctl", "syscon";
reg = <0x32e28000 0x100>;
--
2.25.1
Samsung SEC MIPI DSIM Bridge controller is MIPI DSI bridge
available in NXP's i.MX8M Mini and Nano Processors.
Add dt-bingings for it.
Cc: Andrzej Hajda <[email protected]>
Cc: Neil Armstrong <[email protected]>
Cc: Robert Foss <[email protected]>
Cc: Laurent Pinchart <[email protected]>
Cc: Rob Herring <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
---
.../display/bridge/samsung,sec-dsim.yaml | 184 ++++++++++++++++++
1 file changed, 184 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/samsung,sec-dsim.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,sec-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,sec-dsim.yaml
new file mode 100644
index 000000000000..32f67f313dfd
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/samsung,sec-dsim.yaml
@@ -0,0 +1,184 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/samsung,sec-dsim.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SEC MIPI DSIM Bridge controller on i.MX8M Mini and Nano SoCs
+
+maintainers:
+ - Jagan Teki <[email protected]>
+
+description: |
+ NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
+ the SOCs NWL MIPI-DSI host controller.
+
+allOf:
+ - $ref: ../dsi-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8mm-sec-dsim
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ assigned-clock-parents: true
+ assigned-clock-rates: true
+ assigned-clocks: true
+
+ clocks:
+ items:
+ - description: DSI bus clock
+ - description: PHY_REF clock
+
+ clock-names:
+ items:
+ - const: bus
+ - const: phy_ref
+
+ phys:
+ maxItems: 1
+ description: phandle to the phy module representing the DPHY
+
+ phy-names:
+ items:
+ - const: dphy
+
+ power-domains:
+ maxItems: 1
+ description: phandle to the associated power domain
+
+ samsung,burst-clock-frequency:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ DSIM high speed burst mode frequency.
+
+ samsung,esc-clock-frequency:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ DSIM escape mode frequency.
+
+ samsung,pll-clock-frequency:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ DSIM oscillator clock frequency.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ description:
+ Input port node to receive pixel data from the
+ display controller. Exactly one endpoint must be
+ specified.
+ properties:
+ endpoint@0:
+ $ref: /schemas/graph.yaml#/properties/endpoint
+ description: sub-node describing the input from LCDIF
+
+ endpoint@1:
+ $ref: /schemas/graph.yaml#/properties/endpoint
+ description: sub-node describing the input from DCSS
+
+ oneOf:
+ - required:
+ - endpoint@0
+ - required:
+ - endpoint@1
+
+ unevaluatedProperties: false
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ DSI output port node to the panel or the next bridge
+ in the chain
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - '#address-cells'
+ - '#size-cells'
+ - clock-names
+ - clocks
+ - compatible
+ - interrupts
+ - phy-names
+ - phys
+ - ports
+ - reg
+ - samsung,burst-clock-frequency
+ - samsung,esc-clock-frequency
+ - samsung,pll-clock-frequency
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8mm-clock.h>
+ #include <dt-bindings/power/imx8mm-power.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ dsi: dsi@32e10000 {
+ compatible = "fsl,imx8mm-sec-dsim";
+ reg = <0x32e10000 0xa0>;
+ clocks = <&clk IMX8MM_CLK_DSI_CORE>,
+ <&clk IMX8MM_CLK_DSI_PHY_REF>;
+ clock-names = "bus", "phy_ref";
+ assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
+ <&clk IMX8MM_VIDEO_PLL1_OUT>,
+ <&clk IMX8MM_CLK_DSI_PHY_REF>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
+ <&clk IMX8MM_VIDEO_PLL1_BYPASS>,
+ <&clk IMX8MM_VIDEO_PLL1_OUT>;
+ assigned-clock-rates = <266000000>, <594000000>, <27000000>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&dphy>;
+ phy-names = "dphy";
+ power-domains = <&dispmix_blk_ctl IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_DSI>;
+ samsung,burst-clock-frequency = <891000000>;
+ samsung,esc-clock-frequency = <54000000>;
+ samsung,pll-clock-frequency = <27000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #size-cells = <0>;
+ #address-cells = <1>;
+
+ dsi_in_lcdif: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&lcdif_out_dsi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ dsi_out_panel: endpoint {
+ remote-endpoint = <&panel_in_dsi>;
+ };
+ };
+ };
+ };
--
2.25.1
Add display mix blk control node for i.MX8MM.
Cc: Rob Herring <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 26 +++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 849dd0250ba9..fe5485ee9419 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -663,6 +663,20 @@ pgc_gpu: power-domain@5 {
resets = <&src IMX8MQ_RESET_GPU_RESET>;
power-domains = <&pgc_gpumix>;
};
+
+ pgc_dispmix: power-domain@10 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_DISPMIX>;
+ clocks = <&clk IMX8MM_CLK_DISP_ROOT>,
+ <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MM_CLK_DISP_APB_ROOT>;
+ };
+
+ pgc_mipi: power-domain@11 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_MIPI>;
+ power-domains = <&pgc_dispmix>;
+ };
};
};
};
@@ -1016,6 +1030,18 @@ aips4: bus@32c00000 {
#size-cells = <1>;
ranges = <0x32c00000 0x32c00000 0x400000>;
+ dispmix_blk_ctl: blk-ctl@32e28000 {
+ compatible = "fsl,imx8mm-dispmix-blk-ctl", "syscon";
+ reg = <0x32e28000 0x100>;
+ #power-domain-cells = <1>;
+ power-domains = <&pgc_dispmix>, <&pgc_mipi>;
+ power-domain-names = "dispmix", "mipi";
+ clocks = <&clk IMX8MM_CLK_DISP_ROOT>,
+ <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MM_CLK_DISP_APB_ROOT>;
+ clock-names = "disp", "axi", "apb";
+ };
+
usbotg1: usb@32e40000 {
compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
reg = <0x32e40000 0x200>;
--
2.25.1
Samsung SEC MIPI DSIM DPHY controller is part of registers
available in SEC MIPI DSIM bridge for NXP's i.MX8M Mini and
Nano Processors.
Add phy driver for it.
Cc: Kishon Vijay Abraham I <[email protected]>
Cc: Vinod Koul <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
---
drivers/phy/samsung/Kconfig | 9 +
drivers/phy/samsung/Makefile | 1 +
drivers/phy/samsung/phy-sec-dsim-dphy.c | 236 ++++++++++++++++++++++++
3 files changed, 246 insertions(+)
create mode 100644 drivers/phy/samsung/phy-sec-dsim-dphy.c
diff --git a/drivers/phy/samsung/Kconfig b/drivers/phy/samsung/Kconfig
index e20d2fcc9fe7..e80d40d1278c 100644
--- a/drivers/phy/samsung/Kconfig
+++ b/drivers/phy/samsung/Kconfig
@@ -103,3 +103,12 @@ config PHY_EXYNOS5250_SATA
Exynos5250 based SoCs.This SerDes/Phy supports SATA 1.5 Gb/s,
SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds. It supports one SATA host
port to accept one SATA device.
+
+config PHY_SEC_DSIM_DPHY
+ tristate "Samsung SEC MIPI DSIM DPHY driver"
+ depends on OF && HAS_IOMEM
+ select GENERIC_PHY
+ select REGMAP_MMIO
+ help
+ Enable this to add support for the SEC MIPI DSIM DPHY as found
+ on NXP's i.MX8M Mini and Nano family of SOCs.
diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
index 3959100fe8a2..4d46c7ec0072 100644
--- a/drivers/phy/samsung/Makefile
+++ b/drivers/phy/samsung/Makefile
@@ -11,3 +11,4 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_EXYNOS5250_SATA) += phy-exynos5250-sata.o
+obj-$(CONFIG_PHY_SEC_DSIM_DPHY) += phy-sec-dsim-dphy.o
diff --git a/drivers/phy/samsung/phy-sec-dsim-dphy.c b/drivers/phy/samsung/phy-sec-dsim-dphy.c
new file mode 100644
index 000000000000..31de4a774b5f
--- /dev/null
+++ b/drivers/phy/samsung/phy-sec-dsim-dphy.c
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 NXP
+ * Copyright (C) 2021 Amarula Solutions(India)
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+
+#define DSI_PHYCTRL_B1 0x00
+#define DSI_PHYCTRL_B2 0x04
+#define DSI_PHYCTRL_M1 0x08
+#define DSI_PHYCTRL_M2 0x0c
+#define DSI_PHYTIMING 0x10
+#define DSI_PHYTIMING1 0x14
+#define DSI_PHYTIMING2 0x18
+
+/* phytiming */
+#define M_TLPXCTL_MASK GENMASK(15, 8)
+#define M_TLPXCTL(x) FIELD_PREP(M_TLPXCTL_MASK, (x))
+#define M_THSEXITCTL_MASK GENMASK(7, 0)
+#define M_THSEXITCTL(x) FIELD_PREP(M_THSEXITCTL_MASK, (x))
+
+/* phytiming1 */
+#define M_TCLKPRPRCTL_MASK GENMASK(31, 24)
+#define M_TCLKPRPRCTL(x) FIELD_PREP(M_TCLKPRPRCTL_MASK, (x))
+#define M_TCLKZEROCTL_MASK GENMASK(23, 16)
+#define M_TCLKZEROCTL(x) FIELD_PREP(M_TCLKZEROCTL_MASK, (x))
+#define M_TCLKPOSTCTL_MASK GENMASK(15, 8)
+#define M_TCLKPOSTCTL(x) FIELD_PREP(M_TCLKPOSTCTL_MASK, (x))
+#define M_TCLKTRAILCTL_MASK GENMASK(7, 0)
+#define M_TCLKTRAILCTL(x) FIELD_PREP(M_TCLKTRAILCTL_MASK, (x))
+
+/* phytiming2 */
+#define M_THSPRPRCTL_MASK GENMASK(23, 16)
+#define M_THSPRPRCTL(x) FIELD_PREP(M_THSPRPRCTL_MASK, (x))
+#define M_THSZEROCTL_MASK GENMASK(15, 8)
+#define M_THSZEROCTL(x) FIELD_PREP(M_THSZEROCTL_MASK, (x))
+#define M_THSTRAILCTL_MASK GENMASK(7, 0)
+#define M_THSTRAILCTL(x) FIELD_PREP(M_THSTRAILCTL_MASK, (x))
+
+struct dsim_dphy_plat_data {
+ unsigned int m_tlpxctl;
+ unsigned int m_thsexitctl;
+ unsigned int m_tclkprprctl;
+ unsigned int m_tclkzeroctl;
+ unsigned int m_tclkpostctl;
+ unsigned int m_tclktrailctl;
+ unsigned int m_thsprprctl;
+ unsigned int m_thszeroctl;
+ unsigned int m_thstrailctl;
+};
+
+struct dsim_dphy {
+ struct regmap *regmap;
+ struct clk *phy_ref_clk;
+ const struct dsim_dphy_plat_data *pdata;
+};
+
+static const struct regmap_config dsim_dphy_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = DSI_PHYTIMING2,
+ .name = "mipi-dphy",
+};
+
+static int dsim_dphy_init(struct phy *phy)
+{
+ struct dsim_dphy *dphy = phy_get_drvdata(phy);
+ const struct dsim_dphy_plat_data *pdata = dphy->pdata;
+ u32 reg;
+
+ /* phytiming */
+ regmap_read(dphy->regmap, DSI_PHYTIMING, ®);
+
+ reg &= ~M_TLPXCTL_MASK;
+ reg |= M_TLPXCTL(pdata->m_tlpxctl);
+ reg &= ~M_THSEXITCTL_MASK;
+ reg |= M_THSEXITCTL(pdata->m_thsexitctl);
+ regmap_write(dphy->regmap, DSI_PHYTIMING, reg);
+
+ /* phytiming1 */
+ regmap_read(dphy->regmap, DSI_PHYTIMING1, ®);
+
+ reg &= ~M_TCLKPRPRCTL_MASK;
+ reg |= M_TCLKPRPRCTL(pdata->m_tclkprprctl);
+ reg &= ~M_TCLKZEROCTL_MASK;
+ reg |= M_TCLKZEROCTL(pdata->m_tclkzeroctl);
+ reg &= ~M_TCLKPOSTCTL_MASK;
+ reg |= M_TCLKPOSTCTL(pdata->m_tclkpostctl);
+ reg &= ~M_TCLKTRAILCTL_MASK;
+ reg |= M_TCLKTRAILCTL(pdata->m_tclktrailctl);
+ regmap_write(dphy->regmap, DSI_PHYTIMING1, reg);
+
+ /* phytiming2 */
+ regmap_read(dphy->regmap, DSI_PHYTIMING2, ®);
+
+ reg &= ~M_THSPRPRCTL_MASK;
+ reg |= M_THSPRPRCTL(pdata->m_thsprprctl);
+ reg &= ~M_THSZEROCTL_MASK;
+ reg |= M_THSZEROCTL(pdata->m_thszeroctl);
+ reg &= ~M_THSTRAILCTL_MASK;
+ reg |= M_THSTRAILCTL(pdata->m_thstrailctl);
+ regmap_write(dphy->regmap, DSI_PHYTIMING2, reg);
+
+ return 0;
+}
+
+static int dsim_dphy_exit(struct phy *phy)
+{
+ return 0;
+}
+
+static int dsim_dphy_power_on(struct phy *phy)
+{
+ struct dsim_dphy *dphy = phy_get_drvdata(phy);
+ int ret;
+
+ ret = clk_prepare_enable(dphy->phy_ref_clk);
+ if (ret < 0)
+ return ret;
+
+ return ret;
+}
+
+static int dsim_dphy_power_off(struct phy *phy)
+{
+ struct dsim_dphy *dphy = phy_get_drvdata(phy);
+
+ clk_disable_unprepare(dphy->phy_ref_clk);
+
+ return 0;
+}
+
+static const struct phy_ops dsim_dphy_phy_ops = {
+ .init = dsim_dphy_init,
+ .exit = dsim_dphy_exit,
+ .power_on = dsim_dphy_power_on,
+ .power_off = dsim_dphy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static const struct dsim_dphy_plat_data imx8mm_dphy_plat_data = {
+ /* phytiming */
+ .m_tlpxctl = 0x06,
+ .m_thsexitctl = 0x0b,
+ /* phytiming1 */
+ .m_tclkprprctl = 0x07,
+ .m_tclkzeroctl = 0x26,
+ .m_tclkpostctl = 0x0d,
+ .m_tclktrailctl = 0x08,
+ /* phytimings2 */
+ .m_thsprprctl = 0x08,
+ .m_thszeroctl = 0x0d,
+ .m_thstrailctl = 0x0b,
+};
+
+static const struct of_device_id dsim_dphy_of_match[] = {
+ {
+ .compatible = "fsl,imx8mm-sec-dsim-dphy",
+ .data = &imx8mm_dphy_plat_data,
+ },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, dsim_dphy_of_match);
+
+static int dsim_dphy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct phy_provider *phy_provider;
+ struct dsim_dphy *dphy;
+ struct phy *phy;
+ void __iomem *base;
+
+ if (!np)
+ return -ENODEV;
+
+ dphy = devm_kzalloc(dev, sizeof(*dphy), GFP_KERNEL);
+ if (!dphy)
+ return -ENOMEM;
+
+ dphy->pdata = of_device_get_match_data(&pdev->dev);
+ if (!dphy->pdata)
+ return -EINVAL;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ dphy->regmap = devm_regmap_init_mmio(&pdev->dev, base,
+ &dsim_dphy_regmap_config);
+ if (IS_ERR(dphy->regmap)) {
+ dev_err(dev, "failed create the DPHY regmap\n");
+ return PTR_ERR(dphy->regmap);
+ }
+
+ dphy->phy_ref_clk = devm_clk_get(&pdev->dev, "phy_ref");
+ if (IS_ERR(dphy->phy_ref_clk)) {
+ dev_err(dev, "failed to get phy_ref clock\n");
+ return PTR_ERR(dphy->phy_ref_clk);
+ }
+
+ dev_set_drvdata(dev, dphy);
+
+ phy = devm_phy_create(dev, np, &dsim_dphy_phy_ops);
+ if (IS_ERR(phy)) {
+ dev_err(dev, "failed to create phy %ld\n", PTR_ERR(phy));
+ return PTR_ERR(phy);
+ }
+ phy_set_drvdata(phy, dphy);
+
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static struct platform_driver dsim_dphy_driver = {
+ .probe = dsim_dphy_probe,
+ .driver = {
+ .name = "sec-dsim-dphy",
+ .of_match_table = dsim_dphy_of_match,
+ }
+};
+module_platform_driver(dsim_dphy_driver);
+
+MODULE_AUTHOR("Jagan Teki <[email protected]>");
+MODULE_DESCRIPTION("Samsung SEC MIPI DSIM DPHY driver");
+MODULE_LICENSE("GPL");
--
2.25.1
Add MIPI DPHY reset enable pin in blk-ctl driver for i.MX8MM.
Signed-off-by: Jagan Teki <[email protected]>
---
drivers/soc/imx/blk-ctl-imx8mm.c | 4 ++++
include/dt-bindings/power/imx8mm-power.h | 5 +++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/imx/blk-ctl-imx8mm.c b/drivers/soc/imx/blk-ctl-imx8mm.c
index 5ca8d6c52917..a9d900754faf 100644
--- a/drivers/soc/imx/blk-ctl-imx8mm.c
+++ b/drivers/soc/imx/blk-ctl-imx8mm.c
@@ -25,6 +25,7 @@
#define MEDIA_BLK_MIPI_CSI_I_PRESETN_SFT_EN BIT(4)
#define MEDIA_BLK_CAMERA_PIXEL_RESET_N_SFT_EN BIT(3)
#define MEDIA_BLK_CSI_BRIDGE_SFT_EN GENMASK(2, 0)
+#define MEDIA_BLK_GPR_MIPI_M_RESETN BIT(17)
#define MEDIA_BLK_BUS_PD_MASK BIT(12)
#define MEDIA_BLK_MIPI_CSI_PD_MASK GENMASK(11, 10)
@@ -41,6 +42,9 @@ static struct imx_blk_ctl_hw imx8mm_dispmix_blk_ctl_pds[] = {
IMX_BLK_CTL_PD("MIPI_DSI", "mipi", IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_DSI, 0x4,
MEDIA_BLK_MIPI_DSI_PD_MASK, 0, MEDIA_BLK_MIPI_DSI_I_PRESETN_SFT_EN,
IMX_BLK_CTL_PD_RESET),
+ IMX_BLK_CTL_PD("DPHY", "dphy", IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_DPHY, 0x4,
+ MEDIA_BLK_MIPI_DSI_PD_MASK, 0x8, MEDIA_BLK_GPR_MIPI_M_RESETN,
+ IMX_BLK_CTL_PD_RESET),
IMX_BLK_CTL_PD("MIPI_CSI", "mipi", IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_CSI, 0x4,
MEDIA_BLK_MIPI_CSI_PD_MASK, 0,
MEDIA_BLK_MIPI_CSI_I_PRESETN_SFT_EN | MEDIA_BLK_CAMERA_PIXEL_RESET_N_SFT_EN,
diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-bindings/power/imx8mm-power.h
index a10266befa9c..8becb123e191 100644
--- a/include/dt-bindings/power/imx8mm-power.h
+++ b/include/dt-bindings/power/imx8mm-power.h
@@ -27,7 +27,8 @@
#define IMX8MM_BLK_CTL_PD_DISPMIX_CSI_BRIDGE 0
#define IMX8MM_BLK_CTL_PD_DISPMIX_LCDIF 1
#define IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_DSI 2
-#define IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_CSI 3
-#define IMX8MM_BLK_CTL_PD_DISPMIX_MAX 4
+#define IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_DPHY 3
+#define IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_CSI 4
+#define IMX8MM_BLK_CTL_PD_DISPMIX_MAX 5
#endif
--
2.25.1
Add MIPI DSI pipeline for i.MX8MM.
Video pipeline start from eLCDIF to MIPI DSI and respective
Panel or Bridge on the backend side.
Add support for it.
Cc: Rob Herring <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 59 +++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 5f68182ed3a6..bc09fce0f6a9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1047,6 +1047,65 @@ lcdif: lcdif@32e00000 {
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&dispmix_blk_ctl IMX8MM_BLK_CTL_PD_DISPMIX_LCDIF>;
status = "disabled";
+
+ port {
+ lcdif_out_dsi: endpoint {
+ remote-endpoint = <&dsi_in_lcdif>;
+ };
+ };
+ };
+
+ dsi: dsi@32e10000 {
+ compatible = "fsl,imx8mm-sec-dsim";
+ reg = <0x32e10000 0xa0>;
+ clocks = <&clk IMX8MM_CLK_DSI_CORE>,
+ <&clk IMX8MM_CLK_DSI_PHY_REF>;
+ clock-names = "bus", "phy_ref";
+ assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
+ <&clk IMX8MM_VIDEO_PLL1_OUT>,
+ <&clk IMX8MM_CLK_DSI_PHY_REF>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
+ <&clk IMX8MM_VIDEO_PLL1_BYPASS>,
+ <&clk IMX8MM_VIDEO_PLL1_OUT>;
+ assigned-clock-rates = <266000000>, <594000000>, <27000000>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&dphy>;
+ phy-names = "dphy";
+ power-domains = <&dispmix_blk_ctl IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_DSI>;
+ samsung,burst-clock-frequency = <891000000>;
+ samsung,esc-clock-frequency = <54000000>;
+ samsung,pll-clock-frequency = <27000000>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsi_in_lcdif: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&lcdif_out_dsi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ dphy: dphy@32e100a4 {
+ compatible = "fsl,imx8mm-sec-dsim-dphy";
+ reg = <0x32e100a4 0xbc>;
+ clocks = <&clk IMX8MM_CLK_DSI_PHY_REF>;
+ clock-names = "phy_ref";
+ #phy-cells = <0>;
+ power-domains = <&dispmix_blk_ctl IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_DPHY>;
+ status = "disabled";
};
dispmix_blk_ctl: blk-ctl@32e28000 {
--
2.25.1
Enable LVDS Panel for Engicam i.Core MX8MMini EDIMM2.2 board.
Cc: Rob Herring <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
---
.../freescale/imx8mm-icore-mx8mm-edimm2.2.dts | 90 +++++++++++++++++++
1 file changed, 90 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts
index a4a2ada14835..f1256c9c9bd7 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts
@@ -14,9 +14,51 @@ / {
compatible = "engicam,icore-mx8mm-edimm2.2", "engicam,icore-mx8mm",
"fsl,imx8mm";
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ pwms = <&pwm1 0 1000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ };
+
chosen {
stdout-path = &uart2;
};
+
+ panel {
+ compatible = "yes-optoelectronics,ytc700tlag-05-201c";
+ backlight = <&backlight>;
+ data-mapping = "vesa-24";
+
+ port {
+ panel_out_bridge: endpoint {
+ remote-endpoint = <&bridge_out_panel>;
+ };
+ };
+ };
+};
+
+&dphy {
+ status = "okay";
+};
+
+&dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+
+ dsi_out_bridge: endpoint {
+ remote-endpoint = <&bridge_in_dsi>;
+ data-lanes = <0 1>;
+ };
+ };
+ };
};
&fec1 {
@@ -35,9 +77,43 @@ &i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
+
+ bridge@2c {
+ compatible = "ti,sn65dsi84";
+ reg = <0x2c>;
+ enable-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dsi_bridge_enable>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ bridge_in_dsi: endpoint {
+ remote-endpoint = <&dsi_out_bridge>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ bridge_out_panel: endpoint {
+ remote-endpoint = <&panel_out_bridge>;
+ };
+ };
+ };
+ };
};
&iomuxc {
+ pinctrl_dsi_bridge_enable: dsibridgeenablegrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19
+ MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19
+ >;
+ };
+
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
@@ -52,6 +128,12 @@ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x19
+ >;
+ };
+
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
@@ -77,6 +159,14 @@ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
};
};
+&lcdif {
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
--
2.25.1
On Mon, 21 Jun 2021 12:54:18 +0530, Jagan Teki wrote:
> Samsung SEC MIPI DSIM DPHY controller is part of registers
> available in SEC MIPI DSIM bridge for NXP's i.MX8M Mini and
> Nano Processors.
>
> Add dt-bingings for it.
>
> Cc: Kishon Vijay Abraham I <[email protected]>
> Cc: Vinod Koul <[email protected]>
> Cc: Rob Herring <[email protected]>
> Signed-off-by: Jagan Teki <[email protected]>
> ---
> .../bindings/phy/samsung,sec-dsim-dphy.yaml | 56 +++++++++++++++++++
> 1 file changed, 56 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/samsung,sec-dsim-dphy.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/phy/samsung,sec-dsim-dphy.example.dts:20:18: fatal error: dt-bindings/power/imx8mm-power.h: No such file or directory
20 | #include <dt-bindings/power/imx8mm-power.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:380: Documentation/devicetree/bindings/phy/samsung,sec-dsim-dphy.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1416: dt_binding_check] Error 2
\ndoc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1494925
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Mon, 21 Jun 2021 12:54:16 +0530, Jagan Teki wrote:
> Samsung SEC MIPI DSIM Bridge controller is MIPI DSI bridge
> available in NXP's i.MX8M Mini and Nano Processors.
>
> Add dt-bingings for it.
>
> Cc: Andrzej Hajda <[email protected]>
> Cc: Neil Armstrong <[email protected]>
> Cc: Robert Foss <[email protected]>
> Cc: Laurent Pinchart <[email protected]>
> Cc: Rob Herring <[email protected]>
> Signed-off-by: Jagan Teki <[email protected]>
> ---
> .../display/bridge/samsung,sec-dsim.yaml | 184 ++++++++++++++++++
> 1 file changed, 184 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/bridge/samsung,sec-dsim.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/display/bridge/samsung,sec-dsim.example.dts:20:18: fatal error: dt-bindings/power/imx8mm-power.h: No such file or directory
20 | #include <dt-bindings/power/imx8mm-power.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:380: Documentation/devicetree/bindings/display/bridge/samsung,sec-dsim.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1416: dt_binding_check] Error 2
\ndoc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1494924
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
Hi Jagan,
Thank you for the patch.
On Mon, Jun 21, 2021 at 12:54:16PM +0530, Jagan Teki wrote:
> Samsung SEC MIPI DSIM Bridge controller is MIPI DSI bridge
> available in NXP's i.MX8M Mini and Nano Processors.
>
> Add dt-bingings for it.
>
> Cc: Andrzej Hajda <[email protected]>
> Cc: Neil Armstrong <[email protected]>
> Cc: Robert Foss <[email protected]>
> Cc: Laurent Pinchart <[email protected]>
> Cc: Rob Herring <[email protected]>
> Signed-off-by: Jagan Teki <[email protected]>
> ---
> .../display/bridge/samsung,sec-dsim.yaml | 184 ++++++++++++++++++
> 1 file changed, 184 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/bridge/samsung,sec-dsim.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,sec-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,sec-dsim.yaml
> new file mode 100644
> index 000000000000..32f67f313dfd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/samsung,sec-dsim.yaml
> @@ -0,0 +1,184 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/samsung,sec-dsim.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Samsung SEC MIPI DSIM Bridge controller on i.MX8M Mini and Nano SoCs
> +
> +maintainers:
> + - Jagan Teki <[email protected]>
> +
> +description: |
> + NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
> + the SOCs NWL MIPI-DSI host controller.
> +
> +allOf:
> + - $ref: ../dsi-controller.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - fsl,imx8mm-sec-dsim
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 0
> +
> + assigned-clock-parents: true
> + assigned-clock-rates: true
> + assigned-clocks: true
> +
> + clocks:
> + items:
> + - description: DSI bus clock
> + - description: PHY_REF clock
> +
> + clock-names:
> + items:
> + - const: bus
> + - const: phy_ref
> +
> + phys:
> + maxItems: 1
> + description: phandle to the phy module representing the DPHY
> +
> + phy-names:
> + items:
> + - const: dphy
> +
> + power-domains:
> + maxItems: 1
> + description: phandle to the associated power domain
> +
> + samsung,burst-clock-frequency:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + DSIM high speed burst mode frequency.
> +
> + samsung,esc-clock-frequency:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + DSIM escape mode frequency.
> +
> + samsung,pll-clock-frequency:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + DSIM oscillator clock frequency.
Why do you need those three properties ? They look like configuration
information to me, not system description. If they are needed, their
description needs to explain how to set them. Looking at the three
descriptions above I have no idea what to select for those frequencies.
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + description:
> + Input port node to receive pixel data from the
> + display controller. Exactly one endpoint must be
> + specified.
> + properties:
> + endpoint@0:
> + $ref: /schemas/graph.yaml#/properties/endpoint
> + description: sub-node describing the input from LCDIF
> +
> + endpoint@1:
> + $ref: /schemas/graph.yaml#/properties/endpoint
> + description: sub-node describing the input from DCSS
> +
> + oneOf:
> + - required:
> + - endpoint@0
> + - required:
> + - endpoint@1
> +
> + unevaluatedProperties: false
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/properties/port
> + description:
> + DSI output port node to the panel or the next bridge
> + in the chain
> +
> + required:
> + - port@0
> + - port@1
> +
> +required:
> + - '#address-cells'
> + - '#size-cells'
> + - clock-names
> + - clocks
> + - compatible
> + - interrupts
> + - phy-names
> + - phys
> + - ports
> + - reg
> + - samsung,burst-clock-frequency
> + - samsung,esc-clock-frequency
> + - samsung,pll-clock-frequency
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/imx8mm-clock.h>
> + #include <dt-bindings/power/imx8mm-power.h>
> + #include <dt-bindings/gpio/gpio.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + dsi: dsi@32e10000 {
> + compatible = "fsl,imx8mm-sec-dsim";
> + reg = <0x32e10000 0xa0>;
> + clocks = <&clk IMX8MM_CLK_DSI_CORE>,
> + <&clk IMX8MM_CLK_DSI_PHY_REF>;
> + clock-names = "bus", "phy_ref";
> + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
> + <&clk IMX8MM_VIDEO_PLL1_OUT>,
> + <&clk IMX8MM_CLK_DSI_PHY_REF>;
> + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
> + <&clk IMX8MM_VIDEO_PLL1_BYPASS>,
> + <&clk IMX8MM_VIDEO_PLL1_OUT>;
> + assigned-clock-rates = <266000000>, <594000000>, <27000000>;
> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&dphy>;
> + phy-names = "dphy";
> + power-domains = <&dispmix_blk_ctl IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_DSI>;
> + samsung,burst-clock-frequency = <891000000>;
> + samsung,esc-clock-frequency = <54000000>;
> + samsung,pll-clock-frequency = <27000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + #size-cells = <0>;
> + #address-cells = <1>;
> +
> + dsi_in_lcdif: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&lcdif_out_dsi>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + dsi_out_panel: endpoint {
> + remote-endpoint = <&panel_in_dsi>;
> + };
> + };
> + };
> + };
--
Regards,
Laurent Pinchart
On Mon, Jun 21, 2021 at 2:25 AM Jagan Teki <[email protected]> wrote:
>
> Add MIPI DSI pipeline for i.MX8MM.
>
> Video pipeline start from eLCDIF to MIPI DSI and respective
> Panel or Bridge on the backend side.
>
> Add support for it.
>
> Cc: Rob Herring <[email protected]>
> Signed-off-by: Jagan Teki <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 59 +++++++++++++++++++++++
> 1 file changed, 59 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 5f68182ed3a6..bc09fce0f6a9 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -1047,6 +1047,65 @@ lcdif: lcdif@32e00000 {
> interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> power-domains = <&dispmix_blk_ctl IMX8MM_BLK_CTL_PD_DISPMIX_LCDIF>;
> status = "disabled";
> +
> + port {
> + lcdif_out_dsi: endpoint {
> + remote-endpoint = <&dsi_in_lcdif>;
> + };
> + };
> + };
> +
> + dsi: dsi@32e10000 {
> + compatible = "fsl,imx8mm-sec-dsim";
> + reg = <0x32e10000 0xa0>;
> + clocks = <&clk IMX8MM_CLK_DSI_CORE>,
> + <&clk IMX8MM_CLK_DSI_PHY_REF>;
> + clock-names = "bus", "phy_ref";
> + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
> + <&clk IMX8MM_VIDEO_PLL1_OUT>,
> + <&clk IMX8MM_CLK_DSI_PHY_REF>;
> + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
> + <&clk IMX8MM_VIDEO_PLL1_BYPASS>,
> + <&clk IMX8MM_VIDEO_PLL1_OUT>;
> + assigned-clock-rates = <266000000>, <594000000>, <27000000>;
> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&dphy>;
> + phy-names = "dphy";
> + power-domains = <&dispmix_blk_ctl IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_DSI>;
> + samsung,burst-clock-frequency = <891000000>;
> + samsung,esc-clock-frequency = <54000000>;
> + samsung,pll-clock-frequency = <27000000>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + dsi_in_lcdif: endpoint@0 {
> + reg = <0>;
When I build this with W=1, I get a warning:
Warning (graph_child_address):
/soc@0/bus@32c00000/dsi@32e10000/ports/port@0: graph node has single
child node 'endpoint@0', #address-cells/#size-cells are not necessary
Are there supposed to be two endpoints for port@0?
> + remote-endpoint = <&lcdif_out_dsi>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + };
> + };
> + };
> +
> + dphy: dphy@32e100a4 {
> + compatible = "fsl,imx8mm-sec-dsim-dphy";
> + reg = <0x32e100a4 0xbc>;
> + clocks = <&clk IMX8MM_CLK_DSI_PHY_REF>;
> + clock-names = "phy_ref";
> + #phy-cells = <0>;
> + power-domains = <&dispmix_blk_ctl IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_DPHY>;
> + status = "disabled";
> };
>
> dispmix_blk_ctl: blk-ctl@32e28000 {
> --
> 2.25.1
>
On Mon, Jun 21, 2021 at 2:25 AM Jagan Teki <[email protected]> wrote:
>
> Add eLCDIF controller node for i.MX8MM.
>
> Cc: Rob Herring <[email protected]>
> Signed-off-by: Jagan Teki <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index fe5485ee9419..5f68182ed3a6 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -1030,6 +1030,25 @@ aips4: bus@32c00000 {
> #size-cells = <1>;
> ranges = <0x32c00000 0x32c00000 0x400000>;
>
> + lcdif: lcdif@32e00000 {
> + compatible = "fsl,imx8mm-lcdif", "fsl,imx6sx-lcdif";
Based on a comment I read from Marek [1] from this patch series for
the driver, I think fallback compatible should be fsl,imx28-lcdif.
"The iMX8MM and iMX8MN do not support the overlay plane, so they are MXSFB V4"
[1] - https://patchwork.kernel.org/project/dri-devel/patch/[email protected]/
adam
> + reg = <0x32e00000 0x10000>;
> + clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
> + <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
> + <&clk IMX8MM_CLK_DISP_APB_ROOT>;
> + clock-names = "pix", "disp_axi", "axi";
> + assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
> + <&clk IMX8MM_CLK_DISP_AXI>,
> + <&clk IMX8MM_CLK_DISP_APB>;
> + assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
> + <&clk IMX8MM_SYS_PLL2_1000M>,
> + <&clk IMX8MM_SYS_PLL1_800M>;
> + assigned-clock-rate = <594000000>, <500000000>, <200000000>;
> + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&dispmix_blk_ctl IMX8MM_BLK_CTL_PD_DISPMIX_LCDIF>;
> + status = "disabled";
> + };
> +
> dispmix_blk_ctl: blk-ctl@32e28000 {
> compatible = "fsl,imx8mm-dispmix-blk-ctl", "syscon";
> reg = <0x32e28000 0x100>;
> --
> 2.25.1
>
On Tue, Jun 22, 2021 at 8:39 AM Adam Ford <[email protected]> wrote:
>
> On Mon, Jun 21, 2021 at 2:25 AM Jagan Teki <[email protected]> wrote:
> >
> > Add eLCDIF controller node for i.MX8MM.
> >
> > Cc: Rob Herring <[email protected]>
> > Signed-off-by: Jagan Teki <[email protected]>
> > ---
> > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 19 +++++++++++++++++++
> > 1 file changed, 19 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > index fe5485ee9419..5f68182ed3a6 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > @@ -1030,6 +1030,25 @@ aips4: bus@32c00000 {
> > #size-cells = <1>;
> > ranges = <0x32c00000 0x32c00000 0x400000>;
> >
> > + lcdif: lcdif@32e00000 {
> > + compatible = "fsl,imx8mm-lcdif", "fsl,imx6sx-lcdif";
>
> Based on a comment I read from Marek [1] from this patch series for
> the driver, I think fallback compatible should be fsl,imx28-lcdif.
>
> "The iMX8MM and iMX8MN do not support the overlay plane, so they are MXSFB V4"
>
> [1] - https://patchwork.kernel.org/project/dri-devel/patch/[email protected]/
Yes, I saw that, look like some conversation is going on that thread.
will update accordingly in next version.
Jagan.
On Mon, Jun 21, 2021 at 12:54:18PM +0530, Jagan Teki wrote:
> Samsung SEC MIPI DSIM DPHY controller is part of registers
> available in SEC MIPI DSIM bridge for NXP's i.MX8M Mini and
> Nano Processors.
>
> Add dt-bingings for it.
>
> Cc: Kishon Vijay Abraham I <[email protected]>
> Cc: Vinod Koul <[email protected]>
> Cc: Rob Herring <[email protected]>
> Signed-off-by: Jagan Teki <[email protected]>
> ---
> .../bindings/phy/samsung,sec-dsim-dphy.yaml | 56 +++++++++++++++++++
> 1 file changed, 56 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/samsung,sec-dsim-dphy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/samsung,sec-dsim-dphy.yaml b/Documentation/devicetree/bindings/phy/samsung,sec-dsim-dphy.yaml
> new file mode 100644
> index 000000000000..c5770c8035e1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/samsung,sec-dsim-dphy.yaml
> @@ -0,0 +1,56 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/samsung,sec-dsim-dphy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Samsung SEC MIPI DSIM DPHY controller on i.MX8M Mini and Nano SoCs
> +
> +maintainers:
> + - Jagan Teki <[email protected]>
> +
> +properties:
> + "#phy-cells":
> + const: 0
> +
> + compatible:
> + enum:
> + - fsl,imx8mm-sec-dsim-dphy
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Phy Ref Clock
> +
> + clock-names:
> + items:
> + - const: phy_ref
'ref' is sufficient.
> +
> + power-domains:
> + maxItems: 1
> + description: phandle to the associated power domain
> +
> +required:
> + - "#phy-cells"
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/imx8mm-clock.h>
> + #include <dt-bindings/power/imx8mm-power.h>
> +
> + dphy: dphy@32e100a4 {
phy@...
> + compatible = "fsl,imx8mm-sec-dsim-dphy";
> + reg = <0x32e100a4 0xbc>;
> + clocks = <&clk IMX8MM_CLK_DSI_PHY_REF>;
> + clock-names = "phy_ref";
> + power-domains = <&dispmix_blk_ctl IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_DPHY>;
> + #phy-cells = <0>;
> + };
> --
> 2.25.1
>
>
Hi Laurent,
On Mon, Jun 21, 2021 at 11:26 PM Laurent Pinchart
<[email protected]> wrote:
>
> Hi Jagan,
>
> Thank you for the patch.
>
> On Mon, Jun 21, 2021 at 12:54:16PM +0530, Jagan Teki wrote:
> > Samsung SEC MIPI DSIM Bridge controller is MIPI DSI bridge
> > available in NXP's i.MX8M Mini and Nano Processors.
> >
> > Add dt-bingings for it.
> >
> > Cc: Andrzej Hajda <[email protected]>
> > Cc: Neil Armstrong <[email protected]>
> > Cc: Robert Foss <[email protected]>
> > Cc: Laurent Pinchart <[email protected]>
> > Cc: Rob Herring <[email protected]>
> > Signed-off-by: Jagan Teki <[email protected]>
> > ---
> > .../display/bridge/samsung,sec-dsim.yaml | 184 ++++++++++++++++++
> > 1 file changed, 184 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/display/bridge/samsung,sec-dsim.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,sec-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,sec-dsim.yaml
> > new file mode 100644
> > index 000000000000..32f67f313dfd
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/bridge/samsung,sec-dsim.yaml
> > @@ -0,0 +1,184 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/bridge/samsung,sec-dsim.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Samsung SEC MIPI DSIM Bridge controller on i.MX8M Mini and Nano SoCs
> > +
> > +maintainers:
> > + - Jagan Teki <[email protected]>
> > +
> > +description: |
> > + NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
> > + the SOCs NWL MIPI-DSI host controller.
> > +
> > +allOf:
> > + - $ref: ../dsi-controller.yaml#
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - fsl,imx8mm-sec-dsim
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + '#address-cells':
> > + const: 1
> > +
> > + '#size-cells':
> > + const: 0
> > +
> > + assigned-clock-parents: true
> > + assigned-clock-rates: true
> > + assigned-clocks: true
> > +
> > + clocks:
> > + items:
> > + - description: DSI bus clock
> > + - description: PHY_REF clock
> > +
> > + clock-names:
> > + items:
> > + - const: bus
> > + - const: phy_ref
> > +
> > + phys:
> > + maxItems: 1
> > + description: phandle to the phy module representing the DPHY
> > +
> > + phy-names:
> > + items:
> > + - const: dphy
> > +
> > + power-domains:
> > + maxItems: 1
> > + description: phandle to the associated power domain
> > +
> > + samsung,burst-clock-frequency:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description:
> > + DSIM high speed burst mode frequency.
> > +
> > + samsung,esc-clock-frequency:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description:
> > + DSIM escape mode frequency.
> > +
> > + samsung,pll-clock-frequency:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description:
> > + DSIM oscillator clock frequency.
>
> Why do you need those three properties ? They look like configuration
> information to me, not system description. If they are needed, their
> description needs to explain how to set them. Looking at the three
> descriptions above I have no idea what to select for those frequencies.
DSIM PLLOutput PMS values are computed based on these clock values as
per exynos dsi code is concern. Look like there is other way to
compute PMS in SEC DSIM(at least on i.MX8MM) unlike exynos. Let me
come back with new changes, thanks!
Jagan.
Hi Jagan,
Thank you for the patch.
On Mon, Jun 21, 2021 at 12:54:17PM +0530, Jagan Teki wrote:
> Samsung SEC MIPI DSIM Bridge controller is MIPI DSI bridge
> available in NXP's i.MX8M Mini and Nano Processors.
>
> Add bridge driver for it.
>
> Cc: Andrzej Hajda <[email protected]>
> Cc: Neil Armstrong <[email protected]>
> Cc: Robert Foss <[email protected]>
> Cc: Laurent Pinchart <[email protected]>
> Signed-off-by: Jagan Teki <[email protected]>
> ---
> drivers/gpu/drm/bridge/Kconfig | 15 +
> drivers/gpu/drm/bridge/Makefile | 1 +
> drivers/gpu/drm/bridge/sec-dsim.c | 1535 +++++++++++++++++++++++++++++
> 3 files changed, 1551 insertions(+)
> create mode 100644 drivers/gpu/drm/bridge/sec-dsim.c
>
> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> index 19109c0b5481..a183eb165a35 100644
> --- a/drivers/gpu/drm/bridge/Kconfig
> +++ b/drivers/gpu/drm/bridge/Kconfig
> @@ -189,6 +189,21 @@ config DRM_PARADE_PS8640
> The PS8640 is a high-performance and low-power
> MIPI DSI to eDP converter
>
> +config DRM_SEC_MIPI_DSIM
> + tristate "Samsung SEC MIPI DSIM Bridge controller"
> + depends on DRM
> + depends on COMMON_CLK
> + depends on OF && HAS_IOMEM
> + select DRM_KMS_HELPER
> + select DRM_MIPI_DSI
> + select DRM_PANEL_BRIDGE
> + select GENERIC_PHY_MIPI_DPHY
> + select MFD_SYSCON
> + select REGMAP_MMIO
> + help
> + This enables the Samsung SEC MIPI DSIM Bridge controller as
> + for example found on NXP's i.MX8M Mini and Nano Processors.
> +
> config DRM_SIL_SII8620
> tristate "Silicon Image SII8620 HDMI/MHL bridge"
> depends on OF
> diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
> index 88e4edf81087..ff802a4ffe65 100644
> --- a/drivers/gpu/drm/bridge/Makefile
> +++ b/drivers/gpu/drm/bridge/Makefile
> @@ -12,6 +12,7 @@ obj-$(CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW) += megachips-stdpxxxx-ge-b850v
> obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
> obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
> obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o
> +obj-$(CONFIG_DRM_SEC_MIPI_DSIM) += sec-dsim.o
> obj-$(CONFIG_DRM_SIL_SII8620) += sil-sii8620.o
> obj-$(CONFIG_DRM_SII902X) += sii902x.o
> obj-$(CONFIG_DRM_SII9234) += sii9234.o
> diff --git a/drivers/gpu/drm/bridge/sec-dsim.c b/drivers/gpu/drm/bridge/sec-dsim.c
> new file mode 100644
> index 000000000000..5b6645bb94e7
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/sec-dsim.c
> @@ -0,0 +1,1535 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Samsung SEC MIPI DSIM Bridge
> + *
> + * Copyright (C) 2018 NXP
> + * Copyright (c) 2014 Samsung Electronics Co., Ltd
> + * Copyright (C) 2021 Amarula Solutions(India)
> + *
> + * Based on the drivers/gpu/drm/exynos/exynos_drm_dsi.c
> + *
> + * Authors:
> + * Tomasz Figa <[email protected]>
> + * Andrzej Hajda <[email protected]>
> + * Fancy Fang <[email protected]>
> + * Jagan Teki <[email protected]>
> + */
> +
> +#include <asm/unaligned.h>
> +#include <linux/bitfield.h>
> +#include <linux/clk.h>
> +#include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/of_graph.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_bridge.h>
> +#include <drm/drm_mipi_dsi.h>
> +#include <drm/drm_panel.h>
> +#include <drm/drm_of.h>
> +#include <drm/drm_print.h>
> +
> +#include <video/mipi_display.h>
> +
> +#define DRIVER_NAME "sec-dsim"
> +
> +/* dsim registers */
> +#define DSIM_VERSION 0x00
> +#define DSIM_STATUS 0x04
> +#define DSIM_RGB_STATUS 0x08
> +#define DSIM_SWRST 0x0c
> +#define DSIM_CLKCTRL 0x10
> +#define DSIM_TIMEOUT 0x14
> +#define DSIM_CONFIG 0x18
> +#define DSIM_ESCMODE 0x1c
> +#define DSIM_MDRESOL 0x20
> +#define DSIM_MVPORCH 0x24
> +#define DSIM_MHPORCH 0x28
> +#define DSIM_MSYNC 0x2c
> +#define DSIM_SDRESOL 0x30
> +#define DSIM_INTSRC 0x34
> +#define DSIM_INTMSK 0x38
> +#define DSIM_PKTHDR 0x3c
> +#define DSIM_PAYLOAD 0x40
> +#define DSIM_RXFIFO 0x44
> +#define DSIM_FIFOTHLD 0x48
> +#define DSIM_FIFOCTRL 0x4c
> +#define DSIM_MEMACCHR 0x50
> +#define DSIM_MULTI_PKT 0x78
> +#define DSIM_PLLCTRL_1G 0x90
> +#define DSIM_PLLCTRL 0x94
> +#define DSIM_PLLCTRL1 0x98
> +#define DSIM_PLLCTRL2 0x9c
> +#define DSIM_PLLTMR 0xa0
Looking at the register set, it seems to match the Exynos 5433,
supported by drivers/gpu/drm/exynos/exynos_drm_dsi.c. Can we leverage
that driver instead of adding a new one for the same IP core ?
> +
> +/* register bit fields */
> +#define STATUS_PLLSTABLE BIT(31)
> +#define STATUS_SWRSTRLS BIT(20)
> +#define STATUS_TXREADYHSCLK BIT(10)
> +#define STATUS_ULPSCLK BIT(9)
> +#define STATUS_STOPSTATECLK BIT(8)
> +
> +#define CLKCTRL_TXREQUESTHSCLK BIT(31)
> +#define CLKCTRL_ESCCLKEN BIT(28)
> +#define CLKCTRL_PLLBYPASS BIT(27)
> +#define CLKCTRL_BYTECLKSRC_MASK GENMASK(26, 25)
> +#define CLKCTRL_BYTECLKSRC(x) FIELD_PREP(CLKCTRL_BYTECLKSRC_MASK, (x))
> +#define CLKCTRL_BYTECLKEN BIT(24)
> +#define CLKCTRL_LANEESCDATAEN_MASK GENMASK(23, 20)
> +#define CLKCTRL_LANEESCDATAEN(x) FIELD_PREP(CLKCTRL_LANEESCDATAEN_MASK, (x))
> +#define CLKCTRL_LANEESCCLKEN BIT(19)
> +#define CLKCTRL_ESCPRESCALER_MASK GENMASK(15, 0)
> +#define CLKCTRL_ESCPRESCALER(x) FIELD_PREP(CLKCTRL_ESCPRESCALER_MASK, (x))
> +
> +#define TIMEOUT_BTAOUT_MASK GENMASK(23, 16)
> +#define TIMEOUT_BTAOUT(x) FIELD_PREP(TIMEOUT_BTAOUT_MASK, (x))
> +#define TIMEOUT_LPDRTOUT_MASK GENMASK(15, 0)
> +#define TIMEOUT_LPDRTOUT(x) FIELD_PREP(TIMEOUT_LPDRTOUT_MASK, (x))
> +
> +#define CONFIG_NON_CONTINUOUS_CLOCK_LANE BIT(31)
> +#define CONFIG_CLKLANE_STOP_START BIT(30)
> +#define CONFIG_MFLUSH_VS BIT(29)
> +#define CONFIG_EOT_R03 BIT(28)
> +#define CONFIG_SYNCINFORM BIT(27)
> +#define CONFIG_BURSTMODE BIT(26)
> +#define CONFIG_VIDEOMODE BIT(25)
> +#define CONFIG_AUTOMODE BIT(24)
> +#define CONFIG_HSEDISABLEMODE BIT(23)
> +#define CONFIG_HFPDISABLEMODE BIT(22)
> +#define CONFIG_HBPDISABLEMODE BIT(21)
> +#define CONFIG_HSADISABLEMODE BIT(20)
> +
> +#define CONFIG_MAINPIXFORMAT_MASK GENMASK(14, 12)
> +#define CONFIG_MAINPIXFORMAT(x) FIELD_PREP(CONFIG_MAINPIXFORMAT_MASK, (x))
> +#define CONFIG_NUMOFDATLANE_MASK GENMASK(6, 5)
> +#define CONFIG_NUMOFDATLANE(x) FIELD_PREP(CONFIG_NUMOFDATLANE_MASK, (x))
> +#define CONFIG_LANEEN_MASK GENMASK(4, 0)
> +#define CONFIG_LANEEN(x) FIELD_PREP(GENMASK(4, 1), (x))
> +#define CONFIG_CLKLANEEN BIT(0)
> +
> +#define ESCMODE_STOPSTATE_CN_MASK GENMASK(31, 21)
> +#define ESCMODE_STOPSTATE_CN(x) FIELD_PREP(ESCMODE_STOPSTATE_CN_MASK, (x))
> +#define ESCMODE_CMDLPDT BIT(7)
> +
> +#define MDRESOL_MAINSTANDBY BIT(31)
> +#define MVPORCH_MAINVRESOL_MASK GENMASK(27, 16)
> +#define MVPORCH_MAINVRESOL(x) FIELD_PREP(MVPORCH_MAINVRESOL_MASK, (x))
> +#define MVPORCH_MAINHRESOL_MASK GENMASK(11, 0)
> +#define MVPORCH_MAINHRESOL(x) FIELD_PREP(MVPORCH_MAINHRESOL_MASK, (x))
> +#define MVPORCH_CMDALLOW_MASK GENMASK(31, 28)
> +#define MVPORCH_CMDALLOW(x) FIELD_PREP(MVPORCH_CMDALLOW_MASK, (x))
> +#define MVPORCH_STABLEVFP_MASK GENMASK(26, 16)
> +#define MVPORCH_STABLEVFP(x) FIELD_PREP(MVPORCH_STABLEVFP_MASK, (x))
> +#define MVPORCH_MAINVBP_MASK GENMASK(10, 0)
> +#define MVPORCH_MAINVBP(x) FIELD_PREP(MVPORCH_MAINVBP_MASK, (x))
> +#define MVPORCH_MAINHFP_MASK GENMASK(31, 16)
> +#define MVPORCH_MAINHFP(x) FIELD_PREP(MVPORCH_MAINHFP_MASK, (x))
> +#define MVPORCH_MAINHBP_MASK GENMASK(15, 0)
> +#define MVPORCH_MAINHBP(x) FIELD_PREP(MVPORCH_MAINHBP_MASK, (x))
> +#define MVPORCH_MAINVSA_MASK GENMASK(31, 22)
> +#define MVPORCH_MAINVSA(x) FIELD_PREP(MVPORCH_MAINVSA_MASK, (x))
> +#define MVPORCH_MAINHSA_MASK GENMASK(15, 0)
> +#define MVPORCH_MAINHSA(x) FIELD_PREP(MVPORCH_MAINHSA_MASK, (x))
> +
> +#define INTSRC_PLLSTABLE BIT(31)
> +#define INTSRC_SWRSTRELEASE BIT(30)
> +#define INTSRC_SFRPLFIFOEMPTY BIT(29)
> +#define INTSRC_SFRPHFIFOEMPTY BIT(28)
> +#define INTSRC_FRAMEDONE BIT(24)
> +#define INTSRC_LPDRTOUT BIT(21)
> +#define INTSRC_TATOUT BIT(20)
> +#define INTSRC_RXDATDONE BIT(18)
> +#define INTSRC_RXTE BIT(17)
> +#define INTSRC_RXACK BIT(16)
> +#define INTSRC_MASK (INTSRC_PLLSTABLE | \
> + INTSRC_SWRSTRELEASE | \
> + INTSRC_SFRPLFIFOEMPTY | \
> + INTSRC_SFRPHFIFOEMPTY | \
> + INTSRC_FRAMEDONE | \
> + INTSRC_LPDRTOUT | \
> + INTSRC_TATOUT | \
> + INTSRC_RXDATDONE | \
> + INTSRC_RXTE | \
> + INTSRC_RXACK)
> +
> +#define INTMSK_MSKPLLSTABLE BIT(31)
> +#define INTMSK_MSKSWRELEASE BIT(30)
> +#define INTMSK_MSKSFRPLFIFOEMPTY BIT(29)
> +#define INTMSK_MSKSFRPHFIFOEMPTY BIT(28)
> +#define INTMSK_MSKFRAMEDONE BIT(24)
> +#define INTMSK_MSKLPDRTOUT BIT(21)
> +#define INTMSK_MSKTATOUT BIT(20)
> +#define INTMSK_MSKRXDATDONE BIT(18)
> +#define INTMSK_MSKRXTE BIT(17)
> +#define INTMSK_MSKRXACK BIT(16)
> +
> +#define PKTHDR_DATA1_MASK GENMASK(23, 16)
> +#define PKTHDR_DATA1(x) FIELD_PREP(PKTHDR_DATA1_MASK, (x))
> +#define PKTHDR_DATA1_GET(x) FIELD_GET(PKTHDR_DATA1_MASK, (x))
> +#define PKTHDR_WC_MASK GENMASK(23, 8)
> +#define PKTHDR_WC_GET(x) FIELD_GET(PKTHDR_WC_MASK, (x))
> +#define PKTHDR_DATA0_MASK GENMASK(15, 8)
> +#define PKTHDR_DATA0(x) FIELD_PREP(PKTHDR_DATA0_MASK, (x))
> +#define PKTHDR_DATA0_GET(x) FIELD_GET(PKTHDR_DATA0_MASK, (x))
> +#define PKTHDR_DI_MASK GENMASK(7, 0)
> +#define PKTHDR_DI(x) FIELD_PREP(PKTHDR_DI_MASK, (x))
> +#define PKTHDR_DT_MASK GENMASK(5, 0)
> +#define PKTHDR_DT_GET(x) FIELD_GET(PKTHDR_DT_MASK, (x))
> +
> +#define FIFOCTRL_FULLRX BIT(25)
> +#define FIFOCTRL_EMPTYRX BIT(24)
> +#define FIFOCTRL_FULLHSFR BIT(23)
> +#define FIFOCTRL_EMPTYHSFR BIT(22)
> +#define FIFOCTRL_FULLLSFR BIT(21)
> +#define FIFOCTRL_EMPTYLSFR BIT(20)
> +#define FIFOCTRL_FULLHMAIN BIT(11)
> +#define FIFOCTRL_EMPTYHMAIN BIT(10)
> +#define FIFOCTRL_FULLLMAIN BIT(9)
> +#define FIFOCTRL_EMPTYLMAIN BIT(8)
> +#define FIFOCTRL_NINITRX BIT(4)
> +#define FIFOCTRL_NINITSFR BIT(3)
> +#define FIFOCTRL_NINITI80 BIT(2)
> +#define FIFOCTRL_NINITSUB BIT(1)
> +#define FIFOCTRL_NINITMAIN BIT(0)
> +#define FIFOCTRL_INIT_MASK GENMASK(4, 0)
> +
> +#define PLLCTRL_PLLEN BIT(23)
> +#define PLLCTRL_PMS_P_MASK GENMASK(18, 14)
> +#define PLLCTRL_PMS_P(x) FIELD_PREP(PLLCTRL_PMS_P_MASK, (x))
> +#define PLLCTRL_PMS_M_MASK GENMASK(12, 4)
> +#define PLLCTRL_PMS_M(x) FIELD_PREP(PLLCTRL_PMS_M_MASK, (x))
> +#define PLLCTRL_PMS_S_MASK GENMASK(2, 1)
> +#define PLLCTRL_PMS_S(x) FIELD_PREP(PLLCTRL_PMS_S_MASK, (x))
> +
> +/* dsim all irqs index */
> +#define PLLSTABLE 1
> +#define SWRSTRELEASE 2
> +#define SFRPLFIFOEMPTY 3
> +#define SFRPHFIFOEMPTY 4
> +#define SYNCOVERRIDE 5
> +#define BUSTURNOVER 6
> +#define FRAMEDONE 7
> +#define LPDRTOUT 8
> +#define TATOUT 9
> +#define RXDATDONE 10
> +#define RXTE 11
> +#define RXACK 12
> +#define ERRRXECC 13
> +#define ERRRXCRC 14
> +#define ERRESC3 15
> +#define ERRESC2 16
> +#define ERRESC1 17
> +#define ERRESC0 18
> +#define ERRSYNC3 19
> +#define ERRSYNC2 20
> +#define ERRSYNC1 21
> +#define ERRSYNC0 22
> +#define ERRCONTROL3 23
> +#define ERRCONTROL2 24
> +#define ERRCONTROL1 25
> +#define ERRCONTROL0 26
> +
> +#define MIPI_FIFO_TIMEOUT msecs_to_jiffies(250)
> +
> +#define DSIM_HFP_PKT_OVERHEAD 6
> +#define DSIM_HBP_PKT_OVERHEAD 6
> +#define DSIM_HSA_PKT_OVERHEAD 6
> +
> +struct sec_dsim_plat_data {
> + unsigned int version;
> + unsigned int pll_timer;
> + unsigned int max_freq_hz;
> + unsigned int esc_stop_state_cnt;
> +};
> +
> +struct sec_dsim {
> + struct mipi_dsi_host host;
> + struct drm_bridge bridge;
> + struct drm_bridge *panel_bridge;
> + struct device *dev;
> +
> + struct clk *clk_phy_ref;
> + struct clk *clk_bus;
> + struct phy *phy;
> +
> + struct regmap *regmap;
> + struct drm_display_mode mode;
> + int irq;
> + unsigned int pll_clk_hz;
> + unsigned int burst_clk_hz;
> + unsigned int esc_clk_hz;
> + unsigned int lanes;
> + unsigned int channel;
> + enum mipi_dsi_pixel_format format;
> + unsigned long mode_flags;
> +
> + struct completion pll_stable;
> + struct completion ph_tx_done;
> + struct completion pl_tx_done;
> + struct completion rx_done;
> + const struct sec_dsim_plat_data *pdata;
> +};
> +
> +static const struct regmap_config sec_dsim_regmap_config = {
> + .reg_bits = 8,
> + .val_bits = 32,
> + .reg_stride = 4,
> + .max_register = DSIM_PLLTMR,
> + .name = DRIVER_NAME,
> +};
> +
> +static inline struct sec_dsim *host_to_dsim(struct mipi_dsi_host *host)
> +{
> + return container_of(host, struct sec_dsim, host);
> +}
> +
> +static inline struct sec_dsim *bridge_to_dsim(struct drm_bridge *bridge)
> +{
> + return container_of(bridge, struct sec_dsim, bridge);
> +}
> +
> +/* used for CEA standard modes */
> +struct dsim_hblank_par {
> + char *name; /* drm display mode name */
> + int vrefresh;
> + int hfp_wc;
> + int hbp_wc;
> + int hsa_wc;
> + int lanes;
> +};
> +
> +#define DSIM_HBLANK_PARAM(nm, vf, hfp, hbp, hsa, num) \
> + .name = (nm), \
> + .vrefresh = (vf), \
> + .hfp_wc = (hfp), \
> + .hbp_wc = (hbp), \
> + .hsa_wc = (hsa), \
> + .lanes = (num)
> +
> +static const struct dsim_hblank_par hblank_4lanes[] = {
> + /* { 88, 148, 44 } */
> + { DSIM_HBLANK_PARAM("1920x1080", 60, 60, 105, 27, 4), },
> + /* { 528, 148, 44 } */
> + { DSIM_HBLANK_PARAM("1920x1080", 50, 390, 105, 27, 4), },
> + /* { 88, 148, 44 } */
> + { DSIM_HBLANK_PARAM("1920x1080", 30, 60, 105, 27, 4), },
> + /* { 110, 220, 40 } */
> + { DSIM_HBLANK_PARAM("1280x720", 60, 78, 159, 24, 4), },
> + /* { 440, 220, 40 } */
> + { DSIM_HBLANK_PARAM("1280x720", 50, 324, 159, 24, 4), },
> + /* { 16, 60, 62 } */
> + { DSIM_HBLANK_PARAM("720x480", 60, 6, 39, 40, 4), },
> + /* { 12, 68, 64 } */
> + { DSIM_HBLANK_PARAM("720x576", 50, 3, 45, 42, 4), },
> + /* { 16, 48, 96 } */
> + { DSIM_HBLANK_PARAM("640x480", 60, 6, 30, 66, 4), },
> +};
> +
> +static const struct dsim_hblank_par hblank_2lanes[] = {
> + /* { 88, 148, 44 } */
> + { DSIM_HBLANK_PARAM("1920x1080", 30, 114, 210, 60, 2), },
> + /* { 110, 220, 40 } */
> + { DSIM_HBLANK_PARAM("1280x720", 60, 159, 320, 40, 2), },
> + /* { 440, 220, 40 } */
> + { DSIM_HBLANK_PARAM("1280x720", 50, 654, 320, 40, 2), },
> + /* { 16, 60, 62 } */
> + { DSIM_HBLANK_PARAM("720x480", 60, 16, 66, 88, 2), },
> + /* { 12, 68, 64 } */
> + { DSIM_HBLANK_PARAM("720x576", 50, 12, 96, 72, 2), },
> + /* { 16, 48, 96 } */
> + { DSIM_HBLANK_PARAM("640x480", 60, 18, 66, 138, 2), },
> +};
> +
> +static
> +const struct dsim_hblank_par *sec_dsim_get_hblank_par(struct sec_dsim *dsim)
> +{
> + struct drm_display_mode *mode = &dsim->mode;
> + const struct dsim_hblank_par *hpar, *hblank;
> + int i, size;
> +
> + if (unlikely(!mode->name))
> + return NULL;
> +
> + switch (dsim->lanes) {
> + case 2:
> + hblank = hblank_2lanes;
> + size = ARRAY_SIZE(hblank_2lanes);
> + break;
> + case 4:
> + hblank = hblank_4lanes;
> + size = ARRAY_SIZE(hblank_4lanes);
> + break;
> + default:
> + DRM_DEV_ERROR(dsim->dev,
> + "No hblank data for mode %s with %d lanes\n",
> + mode->name, dsim->lanes);
> + return NULL;
> + }
> +
> + for (i = 0; i < size; i++) {
> + hpar = &hblank[i];
> +
> + if (!strcmp(mode->name, hpar->name)) {
> + if (drm_mode_vrefresh(mode) != hpar->vrefresh)
> + continue;
> +
> + /* found */
> + return hpar;
> + }
> + }
> +
> + return NULL;
> +}
> +
> +static void dsim_write(struct sec_dsim *dsim, unsigned int reg, u32 val)
> +{
> + int ret;
> +
> + ret = regmap_write(dsim->regmap, reg, val);
> + if (ret < 0)
> + DRM_DEV_ERROR(dsim->dev,
> + "failed to write sec dsim reg 0x%x: %d\n",
> + reg, ret);
> +}
> +
> +static u32 dsim_read(struct sec_dsim *dsim, u32 reg)
> +{
> + unsigned int val;
> + int ret;
> +
> + ret = regmap_read(dsim->regmap, reg, &val);
> + if (ret < 0)
> + DRM_DEV_ERROR(dsim->dev,
> + "failed to read sec dsim reg 0x%x: %d\n",
> + reg, ret);
> +
> + return val;
> +}
> +
> +static void __maybe_unused sec_dsim_irq_mask(struct sec_dsim *dsim,
> + int irq_idx)
> +{
> + uint32_t intmsk;
> +
> + intmsk = dsim_read(dsim, DSIM_INTMSK);
> +
> + switch (irq_idx) {
> + case PLLSTABLE:
> + intmsk |= INTMSK_MSKPLLSTABLE;
> + break;
> + case SWRSTRELEASE:
> + intmsk |= INTMSK_MSKSWRELEASE;
> + break;
> + case SFRPLFIFOEMPTY:
> + intmsk |= INTMSK_MSKSFRPLFIFOEMPTY;
> + break;
> + case SFRPHFIFOEMPTY:
> + intmsk |= INTMSK_MSKSFRPHFIFOEMPTY;
> + break;
> + case FRAMEDONE:
> + intmsk |= INTMSK_MSKFRAMEDONE;
> + break;
> + case LPDRTOUT:
> + intmsk |= INTMSK_MSKLPDRTOUT;
> + break;
> + case TATOUT:
> + intmsk |= INTMSK_MSKTATOUT;
> + break;
> + case RXDATDONE:
> + intmsk |= INTMSK_MSKRXDATDONE;
> + break;
> + case RXTE:
> + intmsk |= INTMSK_MSKRXTE;
> + break;
> + case RXACK:
> + intmsk |= INTMSK_MSKRXACK;
> + break;
> + default:
> + /* unsupported irq */
> + return;
> + }
> +
> + dsim_write(dsim, DSIM_INTMSK, intmsk);
> +}
> +
> +static void sec_dsim_irq_unmask(struct sec_dsim *dsim,
> + int irq_idx)
> +{
> + uint32_t intmsk;
> +
> + intmsk = dsim_read(dsim, DSIM_INTMSK);
> +
> + switch (irq_idx) {
> + case PLLSTABLE:
> + intmsk &= ~INTMSK_MSKPLLSTABLE;
> + break;
> + case SWRSTRELEASE:
> + intmsk &= ~INTMSK_MSKSWRELEASE;
> + break;
> + case SFRPLFIFOEMPTY:
> + intmsk &= ~INTMSK_MSKSFRPLFIFOEMPTY;
> + break;
> + case SFRPHFIFOEMPTY:
> + intmsk &= ~INTMSK_MSKSFRPHFIFOEMPTY;
> + break;
> + case FRAMEDONE:
> + intmsk &= ~INTMSK_MSKFRAMEDONE;
> + break;
> + case LPDRTOUT:
> + intmsk &= ~INTMSK_MSKLPDRTOUT;
> + break;
> + case TATOUT:
> + intmsk &= ~INTMSK_MSKTATOUT;
> + break;
> + case RXDATDONE:
> + intmsk &= ~INTMSK_MSKRXDATDONE;
> + break;
> + case RXTE:
> + intmsk &= ~INTMSK_MSKRXTE;
> + break;
> + case RXACK:
> + intmsk &= ~INTMSK_MSKRXACK;
> + break;
> + default:
> + /* unsupported irq */
> + return;
> + }
> +
> + dsim_write(dsim, DSIM_INTMSK, intmsk);
> +}
> +
> +/* write 1 clear irq */
> +static void sec_dsim_irq_clear(struct sec_dsim *dsim,
> + int irq_idx)
> +{
> + uint32_t intsrc = 0;
> +
> + switch (irq_idx) {
> + case PLLSTABLE:
> + intsrc |= INTSRC_PLLSTABLE;
> + break;
> + case SWRSTRELEASE:
> + intsrc |= INTSRC_SWRSTRELEASE;
> + break;
> + case SFRPLFIFOEMPTY:
> + intsrc |= INTSRC_SFRPLFIFOEMPTY;
> + break;
> + case SFRPHFIFOEMPTY:
> + intsrc |= INTSRC_SFRPHFIFOEMPTY;
> + break;
> + case FRAMEDONE:
> + intsrc |= INTSRC_FRAMEDONE;
> + break;
> + case LPDRTOUT:
> + intsrc |= INTSRC_LPDRTOUT;
> + break;
> + case TATOUT:
> + intsrc |= INTSRC_TATOUT;
> + break;
> + case RXDATDONE:
> + intsrc |= INTSRC_RXDATDONE;
> + break;
> + case RXTE:
> + intsrc |= INTSRC_RXTE;
> + break;
> + case RXACK:
> + intsrc |= INTSRC_RXACK;
> + break;
> + default:
> + /* unsupported irq */
> + return;
> + }
> +
> + dsim_write(dsim, DSIM_INTSRC, intsrc);
> +}
> +
> +static void sec_dsim_irq_init(struct sec_dsim *dsim)
> +{
> + sec_dsim_irq_unmask(dsim, PLLSTABLE);
> + sec_dsim_irq_unmask(dsim, SWRSTRELEASE);
> +}
> +
> +static irqreturn_t sec_dsim_irq_handler(int irq, void *data)
> +{
> + uint32_t intsrc, status;
> + struct sec_dsim *dsim = data;
> +
> + intsrc = dsim_read(dsim, DSIM_INTSRC);
> + status = dsim_read(dsim, DSIM_STATUS);
> +
> + if (WARN_ON(!intsrc)) {
> + DRM_DEV_ERROR(dsim->dev, "interrupt is not from dsim\n");
> + return IRQ_NONE;
> + }
> +
> + if (WARN_ON(!(intsrc & INTSRC_MASK))) {
> + dev_warn(dsim->dev, "unenable irq happens: %#x\n", intsrc);
> + /* just clear irqs */
> + dsim_write(dsim, DSIM_INTSRC, intsrc);
> + return IRQ_NONE;
> + }
> +
> + if (intsrc & INTSRC_PLLSTABLE) {
> + WARN_ON(!(status & STATUS_PLLSTABLE));
> + sec_dsim_irq_clear(dsim, PLLSTABLE);
> + complete(&dsim->pll_stable);
> + }
> +
> + if (intsrc & INTSRC_SWRSTRELEASE)
> + sec_dsim_irq_clear(dsim, SWRSTRELEASE);
> +
> + if (intsrc & INTSRC_SFRPLFIFOEMPTY) {
> + sec_dsim_irq_clear(dsim, SFRPLFIFOEMPTY);
> + complete(&dsim->pl_tx_done);
> + }
> +
> + if (intsrc & INTSRC_SFRPHFIFOEMPTY) {
> + sec_dsim_irq_clear(dsim, SFRPHFIFOEMPTY);
> + complete(&dsim->ph_tx_done);
> + }
> +
> + if (WARN_ON(intsrc & INTSRC_LPDRTOUT)) {
> + sec_dsim_irq_clear(dsim, LPDRTOUT);
> + dev_warn(dsim->dev, "LP RX timeout\n");
> + }
> +
> + if (WARN_ON(intsrc & INTSRC_TATOUT)) {
> + sec_dsim_irq_clear(dsim, TATOUT);
> + dev_warn(dsim->dev, "Turns around Acknowledge timeout\n");
> + }
> +
> + if (intsrc & INTSRC_RXDATDONE) {
> + sec_dsim_irq_clear(dsim, RXDATDONE);
> + complete(&dsim->rx_done);
> + }
> +
> + if (intsrc & INTSRC_RXTE) {
> + sec_dsim_irq_clear(dsim, RXTE);
> + DRM_DEV_DEBUG(dsim->dev, "TE Rx trigger received\n");
> + }
> +
> + if (intsrc & INTSRC_RXACK) {
> + sec_dsim_irq_clear(dsim, RXACK);
> + DRM_DEV_DEBUG(dsim->dev, "ACK Rx trigger received\n");
> + }
> +
> + return IRQ_HANDLED;
> +}
> +
> +static void sec_dsim_config_cmd_lpm(struct sec_dsim *dsim, bool enable)
> +{
> + u32 reg;
> +
> + reg = dsim_read(dsim, DSIM_ESCMODE);
> +
> + if (enable)
> + reg |= ESCMODE_CMDLPDT;
> + else
> + reg &= ~ESCMODE_CMDLPDT;
> +
> + dsim_write(dsim, DSIM_ESCMODE, reg);
> +}
> +
> +static void sec_dsim_write_pl_to_sfr_fifo(struct sec_dsim *dsim,
> + const void *payload,
> + size_t length)
> +{
> + uint32_t pl_data;
> +
> + if (!length)
> + return;
> +
> + while (length >= 4) {
> + pl_data = get_unaligned_le32(payload);
> + dsim_write(dsim, DSIM_PAYLOAD, pl_data);
> + payload += 4;
> + length -= 4;
> + }
> +
> + pl_data = 0;
> + switch (length) {
> + case 3:
> + pl_data |= ((u8 *)payload)[2] << 16;
> + /* fallthrough */
> + case 2:
> + pl_data |= ((u8 *)payload)[1] << 8;
> + /* fallthrough */
> + case 1:
> + pl_data |= ((u8 *)payload)[0];
> + dsim_write(dsim, DSIM_PAYLOAD, pl_data);
> + break;
> + }
> +}
> +
> +static void sec_dsim_write_ph_to_sfr_fifo(struct sec_dsim *dsim,
> + void *header,
> + bool use_lpm)
> +{
> + u32 reg;
> +
> + reg = dsim_read(dsim, DSIM_PKTHDR);
> +
> + reg &= ~PKTHDR_DATA1_MASK;
> + reg |= PKTHDR_DATA1(((u8 *)header)[2]); /* WC MSB */
> + reg &= ~PKTHDR_DATA0_MASK;
> + reg |= PKTHDR_DATA0(((u8 *)header)[1]); /* WC LSB */
> + reg &= ~PKTHDR_DI_MASK;
> + reg |= PKTHDR_DI(((u8 *)header)[0]); /* Data ID */
> + dsim_write(dsim, DSIM_PKTHDR, reg);
> +}
> +
> +static int sec_dsim_read_pl_from_sfr_fifo(struct sec_dsim *dsim,
> + void *payload,
> + size_t length)
> +{
> + uint8_t data_type;
> + uint16_t word_count = 0;
> + uint32_t reg, ph, pl;
> +
> + reg = dsim_read(dsim, DSIM_FIFOCTRL);
> +
> + if (WARN_ON(reg & FIFOCTRL_EMPTYRX))
> + return -EINVAL;
> +
> + ph = dsim_read(dsim, DSIM_RXFIFO);
> + data_type = PKTHDR_DT_GET(ph);
> + switch (data_type) {
> + case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
> + DRM_DEV_ERROR(dsim->dev,
> + "peripheral report error: (0-7)%lx, (8-15)%lx\n",
> + PKTHDR_DATA0_GET(ph), PKTHDR_DATA1_GET(ph));
> + return -EPROTO;
> + case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
> + case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
> + if (!WARN_ON(length < 2)) {
> + ((u8 *)payload)[1] = PKTHDR_DATA1_GET(ph);
> + word_count++;
> + }
> + /* fall through */
> + case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
> + case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
> + ((u8 *)payload)[0] = PKTHDR_DATA0_GET(ph);
> + word_count++;
> + length = word_count;
> + break;
> + case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
> + case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
> + word_count = PKTHDR_WC_GET(ph);
> + if (word_count > length) {
> + DRM_DEV_ERROR(dsim->dev, "invalid receive buffer length\n");
> + return -EINVAL;
> + }
> +
> + length = word_count;
> +
> + while (word_count >= 4) {
> + pl = dsim_read(dsim, DSIM_RXFIFO);
> + ((u8 *)payload)[0] = pl & 0xff;
> + ((u8 *)payload)[1] = (pl >> 8) & 0xff;
> + ((u8 *)payload)[2] = (pl >> 16) & 0xff;
> + ((u8 *)payload)[3] = (pl >> 24) & 0xff;
> + payload += 4;
> + word_count -= 4;
> + }
> +
> + if (word_count > 0) {
> + pl = dsim_read(dsim, DSIM_RXFIFO);
> +
> + switch (word_count) {
> + case 3:
> + ((u8 *)payload)[2] = (pl >> 16) & 0xff;
> + /* fall through */
> + case 2:
> + ((u8 *)payload)[1] = (pl >> 8) & 0xff;
> + /* fall through */
> + case 1:
> + ((u8 *)payload)[0] = pl & 0xff;
> + break;
> + }
> + }
> +
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return length;
> +}
> +
> +static ssize_t sec_dsim_host_transfer(struct mipi_dsi_host *host,
> + const struct mipi_dsi_msg *msg)
> +{
> + int ret;
> + bool use_lpm;
> + struct mipi_dsi_packet packet;
> + struct sec_dsim *dsim = host_to_dsim(host);
> +
> + if ((msg->rx_buf && !msg->rx_len) || (msg->rx_len && !msg->rx_buf))
> + return -EINVAL;
> +
> + ret = mipi_dsi_create_packet(&packet, msg);
> + if (ret) {
> + DRM_DEV_ERROR(dsim->dev, "failed to create dsi packet: %d\n", ret);
> + return ret;
> + }
> +
> + /* need to read data from peripheral */
> + if (unlikely(msg->rx_buf))
> + reinit_completion(&dsim->rx_done);
> +
> + /* config LPM for CMD TX */
> + use_lpm = msg->flags & MIPI_DSI_MSG_USE_LPM ? true : false;
> + sec_dsim_config_cmd_lpm(dsim, use_lpm);
> +
> + if (packet.payload_length) { /* Long Packet case */
> + reinit_completion(&dsim->pl_tx_done);
> +
> + /* write packet payload */
> + sec_dsim_write_pl_to_sfr_fifo(dsim,
> + packet.payload,
> + packet.payload_length);
> +
> + /* write packet header */
> + sec_dsim_write_ph_to_sfr_fifo(dsim,
> + packet.header,
> + use_lpm);
> +
> + ret = wait_for_completion_timeout(&dsim->ph_tx_done,
> + MIPI_FIFO_TIMEOUT);
> + if (!ret) {
> + DRM_DEV_ERROR(dsim->dev, "wait payload tx done time out\n");
> + return -EBUSY;
> + }
> + } else {
> + reinit_completion(&dsim->ph_tx_done);
> +
> + /* write packet header */
> + sec_dsim_write_ph_to_sfr_fifo(dsim,
> + packet.header,
> + use_lpm);
> +
> + ret = wait_for_completion_timeout(&dsim->ph_tx_done,
> + MIPI_FIFO_TIMEOUT);
> + if (!ret) {
> + DRM_DEV_ERROR(dsim->dev, "wait pkthdr tx done time out\n");
> + return -EBUSY;
> + }
> + }
> +
> + /* read packet payload */
> + if (unlikely(msg->rx_buf)) {
> + ret = wait_for_completion_timeout(&dsim->rx_done,
> + MIPI_FIFO_TIMEOUT);
> + if (!ret) {
> + DRM_DEV_ERROR(dsim->dev, "wait rx done time out\n");
> + return -EBUSY;
> + }
> +
> + ret = sec_dsim_read_pl_from_sfr_fifo(dsim,
> + msg->rx_buf,
> + msg->rx_len);
> + if (ret < 0)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int sec_dsim_host_attach(struct mipi_dsi_host *host,
> + struct mipi_dsi_device *device)
> +{
> + struct sec_dsim *dsim = host_to_dsim(host);
> +
> + dsim->lanes = device->lanes;
> + dsim->channel = device->channel;
> + dsim->format = device->format;
> + dsim->mode_flags = device->mode_flags;
> +
> + return 0;
> +}
> +
> +static const struct mipi_dsi_host_ops sec_dsim_host_ops = {
> + .attach = sec_dsim_host_attach,
> + .transfer = sec_dsim_host_transfer,
> +};
> +
> +static void sec_dsim_video_mode(struct sec_dsim *dsim)
> +{
> + struct drm_display_mode *mode = &dsim->mode;
> + unsigned int bpp = mipi_dsi_pixel_format_to_bpp(dsim->format);
> + const struct dsim_hblank_par *hpar = NULL;
> + unsigned int hfp, hbp, hsa, vfp, vbp, vsa;
> + unsigned int hfp_wc, hbp_wc, hsa_wc, wc;
> + unsigned int reg;
> +
> + hfp = mode->hsync_start - mode->hdisplay;
> + hbp = mode->htotal - mode->hsync_end;
> + hsa = mode->hsync_end - mode->hsync_start;
> + vfp = mode->vsync_start - mode->vdisplay;
> + vbp = mode->vtotal - mode->vsync_end;
> + vsa = mode->vsync_end - mode->vsync_start;
> +
> + if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
> + hpar = sec_dsim_get_hblank_par(dsim);
> + if (!hpar)
> + DRM_DEV_DEBUG(dsim->dev,
> + "No pre-exist hpar can be used\n");
> + }
> +
> + /* vertical porch */
> + reg = dsim_read(dsim, DSIM_MVPORCH);
> +
> + reg &= ~MVPORCH_MAINVBP_MASK;
> + reg |= MVPORCH_MAINVBP(vbp);
> + reg &= ~MVPORCH_STABLEVFP_MASK;
> + reg |= MVPORCH_STABLEVFP(vfp);
> + reg &= ~MVPORCH_CMDALLOW_MASK;
> + reg |= MVPORCH_CMDALLOW(0x0);
> + dsim_write(dsim, DSIM_MVPORCH, reg);
> +
> + if (!hpar) {
> + wc = DIV_ROUND_UP(hfp * (bpp >> 3), dsim->lanes);
> + hfp_wc = wc > DSIM_HFP_PKT_OVERHEAD ?
> + wc - DSIM_HFP_PKT_OVERHEAD : hfp;
> + wc = DIV_ROUND_UP(hbp * (bpp >> 3), dsim->lanes);
> + hbp_wc = wc > DSIM_HBP_PKT_OVERHEAD ?
> + wc - DSIM_HBP_PKT_OVERHEAD : hbp;
> + } else {
> + hfp_wc = hpar->hfp_wc;
> + hbp_wc = hpar->hbp_wc;
> + }
> +
> + /* horizontal porch */
> + reg = dsim_read(dsim, DSIM_MHPORCH);
> +
> + reg &= ~MVPORCH_MAINHBP_MASK;
> + reg |= MVPORCH_MAINHBP(hbp_wc);
> + reg &= ~MVPORCH_MAINHFP_MASK;
> + reg |= MVPORCH_MAINHFP(hfp_wc);
> + dsim_write(dsim, DSIM_MHPORCH, reg);
> +
> + if (!hpar) {
> + wc = DIV_ROUND_UP(hsa * (bpp >> 3), dsim->lanes);
> + hsa_wc = wc > DSIM_HSA_PKT_OVERHEAD ?
> + wc - DSIM_HSA_PKT_OVERHEAD : hsa;
> + } else {
> + hsa_wc = hpar->hsa_wc;
> + }
> +
> + /* sync area */
> + reg = dsim_read(dsim, DSIM_MSYNC);
> +
> + reg &= ~MVPORCH_MAINHSA_MASK;
> + reg |= MVPORCH_MAINHSA(hsa_wc);
> + reg &= ~MVPORCH_MAINVSA_MASK;
> + reg |= MVPORCH_MAINVSA(vsa);
> + dsim_write(dsim, DSIM_MSYNC, reg);
> +}
> +
> +static void sec_dsim_display_mode(struct sec_dsim *dsim)
> +{
> + struct drm_display_mode *mode = &dsim->mode;
> + u32 reg;
> +
> + if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO)
> + sec_dsim_video_mode(dsim);
> +
> + /* image resolution */
> + reg = dsim_read(dsim, DSIM_MDRESOL);
> +
> + reg &= ~MVPORCH_MAINHRESOL_MASK;
> + reg |= MVPORCH_MAINHRESOL(mode->hdisplay);
> + reg &= ~MVPORCH_MAINVRESOL_MASK;
> + reg |= MVPORCH_MAINVRESOL(mode->vdisplay);
> +
> + dsim_write(dsim, DSIM_MDRESOL, reg);
> +}
> +
> +static void sec_dsim_config_bridge(struct sec_dsim *dsim)
> +{
> + const struct sec_dsim_plat_data *pdata = dsim->pdata;
> + u32 reg;
> +
> + reg = dsim_read(dsim, DSIM_CONFIG);
> +
> + if (dsim->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
> + reg |= CONFIG_NON_CONTINUOUS_CLOCK_LANE;
> + reg |= CONFIG_CLKLANE_STOP_START;
> + }
> +
> + if (!(dsim->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
> + reg |= CONFIG_MFLUSH_VS;
> +
> + /* disable EoT packets in HS mode */
> + if (!(dsim->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
> + reg |= CONFIG_EOT_R03;
> +
> + if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO) {
> + reg |= CONFIG_VIDEOMODE;
> +
> + if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
> + reg |= CONFIG_BURSTMODE;
> +
> + else if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
> + reg |= CONFIG_SYNCINFORM;
> +
> + if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
> + reg |= CONFIG_AUTOMODE;
> +
> + if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
> + reg |= CONFIG_HSEDISABLEMODE;
> +
> + if (!(dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HFP))
> + reg |= CONFIG_HFPDISABLEMODE;
> +
> + if (!(dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HBP))
> + reg |= CONFIG_HBPDISABLEMODE;
> +
> + if (!(dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HSA))
> + reg |= CONFIG_HSADISABLEMODE;
> + }
> +
> + /* pixel format */
> + reg &= ~CONFIG_MAINPIXFORMAT_MASK;
> + if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO) {
> + switch (dsim->format) {
> + case MIPI_DSI_FMT_RGB565:
> + reg |= CONFIG_MAINPIXFORMAT(0x4);
> + break;
> + case MIPI_DSI_FMT_RGB666_PACKED:
> + reg |= CONFIG_MAINPIXFORMAT(0x5);
> + break;
> + case MIPI_DSI_FMT_RGB666:
> + reg |= CONFIG_MAINPIXFORMAT(0x6);
> + break;
> + case MIPI_DSI_FMT_RGB888:
> + reg |= CONFIG_MAINPIXFORMAT(0x7);
> + break;
> + default:
> + reg |= CONFIG_MAINPIXFORMAT(0x7);
> + break;
> + }
> + }
> +
> + /* number of data lanes */
> + reg &= ~CONFIG_NUMOFDATLANE_MASK;
> + reg |= CONFIG_NUMOFDATLANE(dsim->lanes - 1);
> +
> + /* enable data, clock lane */
> + reg &= ~CONFIG_LANEEN_MASK;
> + reg |= CONFIG_LANEEN(BIT(dsim->lanes) - 1);
> + reg |= CONFIG_CLKLANEEN;
> +
> + dsim_write(dsim, DSIM_CONFIG, reg);
> +
> + /* escape mode */
> + reg = dsim_read(dsim, DSIM_ESCMODE);
> +
> + reg &= ~ESCMODE_STOPSTATE_CN_MASK;
> + reg |= ESCMODE_STOPSTATE_CN(pdata->esc_stop_state_cnt);
> + dsim_write(dsim, DSIM_ESCMODE, reg);
> +
> + /* timeout */
> + reg = dsim_read(dsim, DSIM_TIMEOUT);
> +
> + reg &= ~TIMEOUT_LPDRTOUT_MASK;
> + reg |= TIMEOUT_LPDRTOUT(0xffff);
> + reg &= ~TIMEOUT_BTAOUT_MASK;
> + reg |= TIMEOUT_BTAOUT(0xff);
> + dsim_write(dsim, DSIM_TIMEOUT, reg);
> +}
> +
> +#ifndef MHZ
> +#define MHZ (1000*1000)
> +#endif
> +
> +static unsigned long sec_dsim_pll_find_pms(struct sec_dsim *dsim,
> + unsigned long fin,
> + unsigned long fout,
> + u8 *p, u16 *m, u8 *s)
> +{
> + const struct sec_dsim_plat_data *pdata = dsim->pdata;
> + unsigned long best_freq = 0;
> + u32 min_delta = 0xffffffff;
> + u8 p_min, p_max;
> + u8 _p, best_p;
> + u16 _m, best_m;
> + u8 _s, best_s;
> +
> + p_min = DIV_ROUND_UP(fin, (12 * MHZ));
> + p_max = fin / (6 * MHZ);
> +
> + for (_p = p_min; _p <= p_max; ++_p) {
> + for (_s = 0; _s <= 5; ++_s) {
> + u64 tmp;
> + u32 delta;
> +
> + tmp = (u64)fout * (_p << _s);
> + do_div(tmp, fin);
> + _m = tmp;
> + if (_m < 41 || _m > 125)
> + continue;
> +
> + tmp = (u64)_m * fin;
> + do_div(tmp, _p);
> + if (tmp < 500 * MHZ || tmp > pdata->max_freq_hz * MHZ)
> + continue;
> +
> + tmp = (u64)_m * fin;
> + do_div(tmp, _p << _s);
> +
> + delta = abs(fout - tmp);
> + if (delta < min_delta) {
> + best_p = _p;
> + best_m = _m;
> + best_s = _s;
> + min_delta = delta;
> + best_freq = tmp;
> + }
> + }
> + }
> +
> + if (best_freq) {
> + *p = best_p;
> + *m = best_m;
> + *s = best_s;
> + }
> +
> + return best_freq;
> +}
> +
> +static unsigned long sec_dsim_set_pll(struct sec_dsim *dsim)
> +{
> + unsigned long fin, fout, freq;
> + u8 p, s;
> + u16 m;
> + u32 reg;
> +
> + fin = dsim->pll_clk_hz;
> + freq = dsim->burst_clk_hz;
> + fout = sec_dsim_pll_find_pms(dsim, fin, freq, &p, &m, &s);
> + if (!fout) {
> + DRM_DEV_ERROR(dsim->dev,
> + "failed to find PLL PMS for requested frequency\n");
> + return 0;
> + }
> + DRM_DEV_DEBUG(dsim->dev,
> + "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
> +
> + reg = PLLCTRL_PLLEN | PLLCTRL_PMS_P(p) | PLLCTRL_PMS_M(m) | PLLCTRL_PMS_S(s);
> +
> + dsim_write(dsim, DSIM_PLLCTRL, reg);
> +
> + regmap_read_poll_timeout(dsim->regmap, DSIM_STATUS, reg,
> + reg & STATUS_PLLSTABLE, 0, 1000);
> + return fout;
> +}
> +
> +static int sec_dsim_enable_clock(struct sec_dsim *dsim)
> +{
> + const struct sec_dsim_plat_data *pdata = dsim->pdata;
> + unsigned long hs_clk, byte_clk, esc_clk;
> + unsigned long esc_div;
> + u32 reg;
> +
> + /* pll timer */
> + dsim_write(dsim, DSIM_PLLTMR, pdata->pll_timer);
> +
> + /* pll control */
> + hs_clk = sec_dsim_set_pll(dsim);
> + if (!hs_clk) {
> + DRM_DEV_ERROR(dsim->dev, "failed to configure DSI PLL\n");
> + return -EFAULT;
> + }
> +
> + byte_clk = hs_clk / 8;
> + esc_div = DIV_ROUND_UP(byte_clk, dsim->esc_clk_hz);
> + esc_clk = byte_clk / esc_div;
> +
> + if (esc_clk > 20 * MHZ) {
> + ++esc_div;
> + esc_clk = byte_clk / esc_div;
> + }
> +
> + DRM_DEV_DEBUG(dsim->dev,
> + "PLL: hs_clk = %lu, byte_clk = %lu, esc_clk = %lu, esc_div = %lu\n",
> + hs_clk, byte_clk, esc_clk, esc_div);
> +
> + /* clk control */
> + reg = dsim_read(dsim, DSIM_CLKCTRL);
> +
> + reg |= CLKCTRL_TXREQUESTHSCLK;
> + reg |= CLKCTRL_ESCCLKEN;
> + reg &= ~CLKCTRL_PLLBYPASS;
> + reg &= ~CLKCTRL_BYTECLKSRC_MASK;
> + reg |= CLKCTRL_BYTECLKEN;
> + reg &= ~CLKCTRL_LANEESCDATAEN_MASK;
> + reg |= CLKCTRL_LANEESCDATAEN(BIT(dsim->lanes) - 1);
> + reg |= CLKCTRL_LANEESCCLKEN;
> + reg &= ~CLKCTRL_ESCPRESCALER_MASK;
> + reg |= CLKCTRL_ESCPRESCALER(esc_div);
> +
> + dsim_write(dsim, DSIM_CLKCTRL, reg);
> +
> + return 0;
> +}
> +
> +static void sec_dsim_fifo_enable(struct sec_dsim *dsim, bool enable)
> +{
> + u32 reg;
> +
> + reg = dsim_read(dsim, DSIM_FIFOCTRL);
> +
> + reg &= ~FIFOCTRL_INIT_MASK;
> + dsim_write(dsim, DSIM_FIFOCTRL, reg);
> + udelay(500);
> +
> + if (!enable)
> + return;
> +
> + reg |= FIFOCTRL_NINITRX |
> + FIFOCTRL_NINITSFR |
> + FIFOCTRL_NINITI80 |
> + FIFOCTRL_NINITSUB |
> + FIFOCTRL_NINITMAIN;
> + dsim_write(dsim, DSIM_FIFOCTRL, reg);
> + udelay(500);
> +}
> +
> +static void sec_dsim_set_display(struct sec_dsim *dsim, bool enable)
> +{
> + u32 reg;
> +
> + reg = dsim_read(dsim, DSIM_MDRESOL);
> +
> + if (enable)
> + reg |= MDRESOL_MAINSTANDBY;
> + else
> + reg &= ~MDRESOL_MAINSTANDBY;
> + dsim_write(dsim, DSIM_MDRESOL, reg);
> +}
> +
> +static void sec_dsim_bridge_enable(struct drm_bridge *bridge)
> +{
> + struct sec_dsim *dsim = bridge_to_dsim(bridge);
> + int ret;
> +
> + /* enable bridge clocks */
> + clk_prepare_enable(dsim->clk_bus);
> + clk_prepare_enable(dsim->clk_phy_ref);
> +
> + /* initialize the irq */
> + sec_dsim_irq_init(dsim);
> +
> + /* configure the bridge */
> + sec_dsim_config_bridge(dsim);
> +
> + /* enable fifo control */
> + sec_dsim_fifo_enable(dsim, true);
> +
> + /* configure the display mode */
> + sec_dsim_display_mode(dsim);
> +
> + /* config dsim pll */
> + ret = sec_dsim_enable_clock(dsim);
> + if (ret) {
> + DRM_DEV_ERROR(dsim->dev, "failed to enable clock: %d\n", ret);
> + return;
> + }
> +
> + /* power on the dphy */
> + ret = phy_init(dsim->phy);
> + if (ret) {
> + DRM_DEV_ERROR(dsim->dev, "failed to init phy %d\n", ret);
> + return;
> + }
> +
> + /* power on the dphy */
> + ret = phy_power_on(dsim->phy);
> + if (ret) {
> + DRM_DEV_ERROR(dsim->dev, "failed to enable phy %d\n", ret);
> + return;
> + }
> +
> + /* enable data transfer */
> + sec_dsim_set_display(dsim, true);
> +}
> +
> +static void sec_dsim_disable_clock(struct sec_dsim *dsim)
> +{
> + u32 reg;
> +
> + /* clk control */
> + reg = dsim_read(dsim, DSIM_CLKCTRL);
> +
> + reg &= ~CLKCTRL_TXREQUESTHSCLK;
> + reg &= ~CLKCTRL_BYTECLKEN;
> + reg &= ~CLKCTRL_ESCCLKEN;
> + reg &= ~CLKCTRL_LANEESCDATAEN_MASK;
> + reg &= ~CLKCTRL_LANEESCCLKEN;
> + dsim_write(dsim, DSIM_CLKCTRL, reg);
> +
> + /* pll control */
> + reg = dsim_read(dsim, DSIM_PLLCTRL);
> +
> + reg &= ~PLLCTRL_PLLEN;
> + dsim_write(dsim, DSIM_PLLCTRL, reg);
> +}
> +
> +static void sec_dsim_bridge_disable(struct drm_bridge *bridge)
> +{
> + struct sec_dsim *dsim = bridge_to_dsim(bridge);
> +
> + /* disable data transfer */
> + sec_dsim_set_display(dsim, false);
> +
> + /* disable bridge clocks */
> + sec_dsim_disable_clock(dsim);
> +
> + /* disable fifo control */
> + sec_dsim_fifo_enable(dsim, false);
> +
> + /* power off the phy */
> + phy_power_off(dsim->phy);
> +
> + /* exit the phy */
> + phy_exit(dsim->phy);
> +
> + /* disable bridge clock */
> + clk_disable_unprepare(dsim->clk_phy_ref);
> + clk_disable_unprepare(dsim->clk_bus);
> +}
> +
> +static bool sec_dsim_bridge_mode_fixup(struct drm_bridge *bridge,
> + const struct drm_display_mode *mode,
> + struct drm_display_mode *adjusted_mode)
> +{
> + adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
> + adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
> +
> + return true;
> +}
> +
> +static void sec_dsim_bridge_mode_set(struct drm_bridge *bridge,
> + const struct drm_display_mode *mode,
> + const struct drm_display_mode *adjusted_mode)
> +{
> + struct sec_dsim *dsim = bridge_to_dsim(bridge);
> +
> + drm_mode_copy(&dsim->mode, adjusted_mode);
> +}
> +
> +static int sec_dsim_bridge_attach(struct drm_bridge *bridge,
> + enum drm_bridge_attach_flags flags)
> +{
> + struct sec_dsim *dsim = bridge_to_dsim(bridge);
> + struct drm_bridge *panel_bridge;
> + struct drm_panel *panel;
> + int ret;
> +
> + ret = drm_of_find_panel_or_bridge(dsim->dev->of_node, 1, 0, &panel,
> + &panel_bridge);
> + if (ret)
> + return ret;
> +
> + if (panel) {
> + panel_bridge = drm_panel_bridge_add(panel);
> + if (IS_ERR(panel_bridge))
> + return PTR_ERR(panel_bridge);
> + }
> + dsim->panel_bridge = panel_bridge;
> +
> + if (!dsim->panel_bridge)
> + return -EPROBE_DEFER;
> +
> + return drm_bridge_attach(bridge->encoder, dsim->panel_bridge, bridge,
> + flags);
> +}
> +
> +static void sec_dsim_bridge_detach(struct drm_bridge *bridge)
> +{
> + struct sec_dsim *dsim = bridge_to_dsim(bridge);
> +
> + drm_of_panel_bridge_remove(dsim->dev->of_node, 1, 0);
> +}
> +
> +static const struct drm_bridge_funcs sec_dsim_bridge_funcs = {
> + .enable = sec_dsim_bridge_enable,
> + .disable = sec_dsim_bridge_disable,
> + .mode_set = sec_dsim_bridge_mode_set,
> + .mode_fixup = sec_dsim_bridge_mode_fixup,
> + .attach = sec_dsim_bridge_attach,
> + .detach = sec_dsim_bridge_detach,
> +};
> +
> +static const struct drm_bridge_timings sec_dsim_bridge_timings = {
> + .input_bus_flags = DRM_BUS_FLAG_DE_LOW,
> +};
> +
> +static const struct sec_dsim_plat_data imx8mm_mipi_dsim_plat_data = {
> + .version = 0x1060200,
> + .pll_timer = 500,
> + .max_freq_hz = 2100,
> + .esc_stop_state_cnt = 0xf,
> +};
> +
> +static const struct of_device_id sec_dsim_dt_ids[] = {
> + {
> + .compatible = "fsl,imx8mm-sec-dsim",
> + .data = &imx8mm_mipi_dsim_plat_data,
> + },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, sec_dsim_dt_ids);
> +
> +static int sec_dsim_parse_dt(struct sec_dsim *dsim)
> +{
> + struct platform_device *pdev = to_platform_device(dsim->dev);
> + struct device *dev = dsim->dev;
> + struct device_node *node = dev->of_node;
> + struct clk *clk;
> + void __iomem *base;
> + u32 value;
> + int irq;
> + int ret;
> +
> + base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + dsim->regmap = devm_regmap_init_mmio(dev, base, &sec_dsim_regmap_config);
> + if (IS_ERR(dsim->regmap)) {
> + ret = PTR_ERR(dsim->regmap);
> + DRM_DEV_ERROR(dev, "failed to create sec dsim regmap: %d\n", ret);
> + return ret;
> + }
> +
> + dsim->phy = devm_phy_get(dev, "dphy");
> + if (IS_ERR(dsim->phy)) {
> + DRM_DEV_ERROR(dev, "failed to get dsim phy\n");
> + return PTR_ERR(dsim->phy);
> + }
> +
> + clk = devm_clk_get(dev, "bus");
> + if (IS_ERR(clk)) {
> + ret = PTR_ERR(clk);
> + DRM_DEV_ERROR(dev, "failed to get bus clock: %d\n", ret);
> + return ret;
> + }
> + dsim->clk_bus = clk;
> +
> + clk = devm_clk_get(dev, "phy_ref");
> + if (IS_ERR(clk)) {
> + ret = PTR_ERR(clk);
> + DRM_DEV_ERROR(dev, "failed to get phy_ref clock: %d\n", ret);
> + return ret;
> + }
> + dsim->clk_phy_ref = clk;
> +
> + irq = platform_get_irq(pdev, 0);
> + if (irq < 0)
> + return -ENODEV;
> +
> + ret = devm_request_irq(dev, irq, sec_dsim_irq_handler, 0, dev_name(dev), dsim);
> + if (ret) {
> + DRM_DEV_ERROR(dev, "failed to request dsim irq: %d\n", ret);
> + return ret;
> + }
> +
> + if (!of_property_read_u32(node, "samsung,pll-clock-frequency", &value))
> + dsim->pll_clk_hz = value;
> +
> + if (!of_property_read_u32(node, "samsung,burst-clock-frequency", &value))
> + dsim->burst_clk_hz = value;
> +
> + if (!of_property_read_u32(node, "samsung,esc-clock-frequency", &value))
> + dsim->esc_clk_hz = value;
> +
> + init_completion(&dsim->pll_stable);
> + init_completion(&dsim->ph_tx_done);
> + init_completion(&dsim->pl_tx_done);
> + init_completion(&dsim->rx_done);
> +
> + return 0;
> +}
> +
> +static int sec_dsim_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + const struct of_device_id *of_id;
> + struct sec_dsim *dsim;
> + int version;
> + int ret;
> +
> + dsim = devm_kzalloc(dev, sizeof(*dsim), GFP_KERNEL);
> + if (!dsim) {
> + DRM_DEV_ERROR(dev, "failed to allocate dsim\n");
> + return -ENOMEM;
> + }
> +
> + of_id = of_match_device(sec_dsim_dt_ids, dev);
> + if (!of_id)
> + return -ENODEV;
> +
> + dsim->pdata = of_id->data;
> + dsim->dev = dev;
> +
> + ret = sec_dsim_parse_dt(dsim);
> + if (ret) {
> + DRM_DEV_ERROR(dev, "failed to parse dt: %d\n", ret);
> + return ret;
> + }
> +
> + version = dsim_read(dsim, DSIM_VERSION);
> + WARN_ON(version != dsim->pdata->version);
> + DRM_DEV_INFO(dev, "DSIM version number is %#x\n", version);
> +
> + dsim->host.ops = &sec_dsim_host_ops;
> + dsim->host.dev = dsim->dev;
> +
> + ret = mipi_dsi_host_register(&dsim->host);
> + if (ret) {
> + DRM_DEV_ERROR(dev, "failed to register mipi dsi host: %d\n", ret);
> + return ret;
> + }
> +
> + dsim->bridge.driver_private = dsim;
> + dsim->bridge.funcs = &sec_dsim_bridge_funcs;
> + dsim->bridge.of_node = dev->of_node;
> + dsim->bridge.timings = &sec_dsim_bridge_timings;
> +
> + dev_set_drvdata(dev, dsim);
> +
> + drm_bridge_add(&dsim->bridge);
> +
> + return 0;
> +}
> +
> +static int sec_dsim_remove(struct platform_device *pdev)
> +{
> + struct sec_dsim *dsim = platform_get_drvdata(pdev);
> +
> + mipi_dsi_host_unregister(&dsim->host);
> + drm_bridge_remove(&dsim->bridge);
> +
> + return 0;
> +}
> +
> +struct platform_driver sec_dsim_driver = {
> + .probe = sec_dsim_probe,
> + .remove = sec_dsim_remove,
> + .driver = {
> + .name = DRIVER_NAME,
> + .of_match_table = sec_dsim_dt_ids,
> + },
> +};
> +
> +module_platform_driver(sec_dsim_driver);
> +
> +MODULE_AUTHOR("Jagan Teki <[email protected]>");
> +MODULE_DESCRIPTION("Samsung SEC MIPI DSIM Bridge driver");
> +MODULE_LICENSE("GPL v2");
--
Regards,
Laurent Pinchart
Hi Jagan/Laurent,
On Wed, Jun 23, 2021 at 7:23 PM Laurent Pinchart
<[email protected]> wrote:
> Looking at the register set, it seems to match the Exynos 5433,
> supported by drivers/gpu/drm/exynos/exynos_drm_dsi.c. Can we leverage
> that driver instead of adding a new one for the same IP core ?
Yes. there was an attempt from Michael in this direction:
https://patchwork.kernel.org/project/dri-devel/cover/[email protected]/
Cheers
On 24/06/2021 04:48, Fabio Estevam wrote:
> Hi Jagan/Laurent,
>
> On Wed, Jun 23, 2021 at 7:23 PM Laurent Pinchart
> <[email protected]> wrote:
>
>> Looking at the register set, it seems to match the Exynos 5433,
>> supported by drivers/gpu/drm/exynos/exynos_drm_dsi.c. Can we leverage
>> that driver instead of adding a new one for the same IP core ?
>
> Yes. there was an attempt from Michael in this direction:
> https://patchwork.kernel.org/project/dri-devel/cover/[email protected]/
That's the proper direction (maybe as Marek suggested - sharing common
code like for Analogix DP), not duplicating a driver.
Best regards,
Krzysztof
On 21/06/2021 09:24, Jagan Teki wrote:
> Samsung SEC MIPI DSIM DPHY controller is part of registers
> available in SEC MIPI DSIM bridge for NXP's i.MX8M Mini and
> Nano Processors.
>
> Add phy driver for it.
>
> Cc: Kishon Vijay Abraham I <[email protected]>
> Cc: Vinod Koul <[email protected]>
> Signed-off-by: Jagan Teki <[email protected]>
> ---
> drivers/phy/samsung/Kconfig | 9 +
> drivers/phy/samsung/Makefile | 1 +
> drivers/phy/samsung/phy-sec-dsim-dphy.c | 236 ++++++++++++++++++++++++
> 3 files changed, 246 insertions(+)
> create mode 100644 drivers/phy/samsung/phy-sec-dsim-dphy.c
You add a driver for a Samsung's component, so please Cc respective
folks. They might help you with it or provide comments to avoid
duplication of drivers/code:
Around phy:
Marek Szyprowski <[email protected]>
Jaehoon Chung <[email protected]>
Around MIPI/DRM:
Inki Dae <[email protected]>
Seung-Woo Kim <[email protected]>
Andrzej Hajda <[email protected]>
and:
[email protected]
>
> diff --git a/drivers/phy/samsung/Kconfig b/drivers/phy/samsung/Kconfig
> index e20d2fcc9fe7..e80d40d1278c 100644
> --- a/drivers/phy/samsung/Kconfig
> +++ b/drivers/phy/samsung/Kconfig
> @@ -103,3 +103,12 @@ config PHY_EXYNOS5250_SATA
> Exynos5250 based SoCs.This SerDes/Phy supports SATA 1.5 Gb/s,
> SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds. It supports one SATA host
> port to accept one SATA device.
> +
> +config PHY_SEC_DSIM_DPHY
SEC is not a codename of a project/product/silicon. It is a company
name, so basically you called this "PHY_SAMSUNG_DSIM_DPHY" which is too
generic.
> + tristate "Samsung SEC MIPI DSIM DPHY driver"
What is Samsung SEC? Either Samsung or SEC, not both.
> + depends on OF && HAS_IOMEM
> + select GENERIC_PHY
> + select REGMAP_MMIO
> + help
> + Enable this to add support for the SEC MIPI DSIM DPHY as found
> + on NXP's i.MX8M Mini and Nano family of SOCs.
> diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
> index 3959100fe8a2..4d46c7ec0072 100644
> --- a/drivers/phy/samsung/Makefile
> +++ b/drivers/phy/samsung/Makefile
> @@ -11,3 +11,4 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
> phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
> obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
> obj-$(CONFIG_PHY_EXYNOS5250_SATA) += phy-exynos5250-sata.o
> +obj-$(CONFIG_PHY_SEC_DSIM_DPHY) += phy-sec-dsim-dphy.o
> diff --git a/drivers/phy/samsung/phy-sec-dsim-dphy.c b/drivers/phy/samsung/phy-sec-dsim-dphy.c
> new file mode 100644
> index 000000000000..31de4a774b5f
> --- /dev/null
> +++ b/drivers/phy/samsung/phy-sec-dsim-dphy.c
> @@ -0,0 +1,236 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2018 NXP
> + * Copyright (C) 2021 Amarula Solutions(India)
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +
> +#define DSI_PHYCTRL_B1 0x00
> +#define DSI_PHYCTRL_B2 0x04
> +#define DSI_PHYCTRL_M1 0x08
> +#define DSI_PHYCTRL_M2 0x0c
> +#define DSI_PHYTIMING 0x10
> +#define DSI_PHYTIMING1 0x14
> +#define DSI_PHYTIMING2 0x18
> +
> +/* phytiming */
> +#define M_TLPXCTL_MASK GENMASK(15, 8)
What is the "M_" prefix for?
> +#define M_TLPXCTL(x) FIELD_PREP(M_TLPXCTL_MASK, (x))
> +#define M_THSEXITCTL_MASK GENMASK(7, 0)
> +#define M_THSEXITCTL(x) FIELD_PREP(M_THSEXITCTL_MASK, (x))
> +
> +/* phytiming1 */
> +#define M_TCLKPRPRCTL_MASK GENMASK(31, 24)
> +#define M_TCLKPRPRCTL(x) FIELD_PREP(M_TCLKPRPRCTL_MASK, (x))
> +#define M_TCLKZEROCTL_MASK GENMASK(23, 16)
> +#define M_TCLKZEROCTL(x) FIELD_PREP(M_TCLKZEROCTL_MASK, (x))
> +#define M_TCLKPOSTCTL_MASK GENMASK(15, 8)
> +#define M_TCLKPOSTCTL(x) FIELD_PREP(M_TCLKPOSTCTL_MASK, (x))
> +#define M_TCLKTRAILCTL_MASK GENMASK(7, 0)
> +#define M_TCLKTRAILCTL(x) FIELD_PREP(M_TCLKTRAILCTL_MASK, (x))
> +
> +/* phytiming2 */
> +#define M_THSPRPRCTL_MASK GENMASK(23, 16)
> +#define M_THSPRPRCTL(x) FIELD_PREP(M_THSPRPRCTL_MASK, (x))
> +#define M_THSZEROCTL_MASK GENMASK(15, 8)
> +#define M_THSZEROCTL(x) FIELD_PREP(M_THSZEROCTL_MASK, (x))
> +#define M_THSTRAILCTL_MASK GENMASK(7, 0)
> +#define M_THSTRAILCTL(x) FIELD_PREP(M_THSTRAILCTL_MASK, (x))
> +
> +struct dsim_dphy_plat_data {
Remove the m_ prefix. Please document all fields.
> + unsigned int m_tlpxctl;
> + unsigned int m_thsexitctl;
> + unsigned int m_tclkprprctl;
> + unsigned int m_tclkzeroctl;
> + unsigned int m_tclkpostctl;
> + unsigned int m_tclktrailctl;
> + unsigned int m_thsprprctl;
> + unsigned int m_thszeroctl;
> + unsigned int m_thstrailctl;
> +};
> +
> +struct dsim_dphy {
> + struct regmap *regmap;
> + struct clk *phy_ref_clk;
> + const struct dsim_dphy_plat_data *pdata;
> +};
> +
> +static const struct regmap_config dsim_dphy_regmap_config = {
> + .reg_bits = 8,
> + .val_bits = 32,
> + .reg_stride = 4,
> + .max_register = DSI_PHYTIMING2,
> + .name = "mipi-dphy",
> +};
> +
> +static int dsim_dphy_init(struct phy *phy)
> +{
> + struct dsim_dphy *dphy = phy_get_drvdata(phy);
> + const struct dsim_dphy_plat_data *pdata = dphy->pdata;
> + u32 reg;
> +
> + /* phytiming */
> + regmap_read(dphy->regmap, DSI_PHYTIMING, ®);
> +
> + reg &= ~M_TLPXCTL_MASK;
> + reg |= M_TLPXCTL(pdata->m_tlpxctl);
> + reg &= ~M_THSEXITCTL_MASK;
> + reg |= M_THSEXITCTL(pdata->m_thsexitctl);
> + regmap_write(dphy->regmap, DSI_PHYTIMING, reg);
> +
> + /* phytiming1 */
> + regmap_read(dphy->regmap, DSI_PHYTIMING1, ®);
> +
> + reg &= ~M_TCLKPRPRCTL_MASK;
> + reg |= M_TCLKPRPRCTL(pdata->m_tclkprprctl);
> + reg &= ~M_TCLKZEROCTL_MASK;
> + reg |= M_TCLKZEROCTL(pdata->m_tclkzeroctl);
> + reg &= ~M_TCLKPOSTCTL_MASK;
> + reg |= M_TCLKPOSTCTL(pdata->m_tclkpostctl);
> + reg &= ~M_TCLKTRAILCTL_MASK;
> + reg |= M_TCLKTRAILCTL(pdata->m_tclktrailctl);
> + regmap_write(dphy->regmap, DSI_PHYTIMING1, reg);
> +
> + /* phytiming2 */
> + regmap_read(dphy->regmap, DSI_PHYTIMING2, ®);
> +
> + reg &= ~M_THSPRPRCTL_MASK;
> + reg |= M_THSPRPRCTL(pdata->m_thsprprctl);
> + reg &= ~M_THSZEROCTL_MASK;
> + reg |= M_THSZEROCTL(pdata->m_thszeroctl);
> + reg &= ~M_THSTRAILCTL_MASK;
> + reg |= M_THSTRAILCTL(pdata->m_thstrailctl);
> + regmap_write(dphy->regmap, DSI_PHYTIMING2, reg);
> +
> + return 0;
> +}
> +
> +static int dsim_dphy_exit(struct phy *phy)
> +{
> + return 0;
> +}
> +
> +static int dsim_dphy_power_on(struct phy *phy)
> +{
> + struct dsim_dphy *dphy = phy_get_drvdata(phy);
> + int ret;
> +
> + ret = clk_prepare_enable(dphy->phy_ref_clk);
> + if (ret < 0)
> + return ret;
> +
> + return ret;
> +}
> +
> +static int dsim_dphy_power_off(struct phy *phy)
> +{
> + struct dsim_dphy *dphy = phy_get_drvdata(phy);
> +
> + clk_disable_unprepare(dphy->phy_ref_clk);
> +
> + return 0;
> +}
> +
> +static const struct phy_ops dsim_dphy_phy_ops = {
> + .init = dsim_dphy_init,
> + .exit = dsim_dphy_exit,
> + .power_on = dsim_dphy_power_on,
> + .power_off = dsim_dphy_power_off,
> + .owner = THIS_MODULE,
> +};
> +
> +static const struct dsim_dphy_plat_data imx8mm_dphy_plat_data = {
> + /* phytiming */
> + .m_tlpxctl = 0x06,
> + .m_thsexitctl = 0x0b,
> + /* phytiming1 */
> + .m_tclkprprctl = 0x07,
> + .m_tclkzeroctl = 0x26,
> + .m_tclkpostctl = 0x0d,
> + .m_tclktrailctl = 0x08,
> + /* phytimings2 */
> + .m_thsprprctl = 0x08,
> + .m_thszeroctl = 0x0d,
> + .m_thstrailctl = 0x0b,
> +};
> +
> +static const struct of_device_id dsim_dphy_of_match[] = {
> + {
> + .compatible = "fsl,imx8mm-sec-dsim-dphy",
> + .data = &imx8mm_dphy_plat_data,
> + },
> + { /* sentinel */ },
> +};
> +MODULE_DEVICE_TABLE(of, dsim_dphy_of_match);
> +
> +static int dsim_dphy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + struct phy_provider *phy_provider;
> + struct dsim_dphy *dphy;
> + struct phy *phy;
> + void __iomem *base;
> +
> + if (!np)
> + return -ENODEV;
How can this driver bind without 'np'? How is it possible?
> +
> + dphy = devm_kzalloc(dev, sizeof(*dphy), GFP_KERNEL);
> + if (!dphy)
> + return -ENOMEM;
> +
> + dphy->pdata = of_device_get_match_data(&pdev->dev);
> + if (!dphy->pdata)
> + return -EINVAL;
> +
> + base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + dphy->regmap = devm_regmap_init_mmio(&pdev->dev, base,
> + &dsim_dphy_regmap_config);
> + if (IS_ERR(dphy->regmap)) {
> + dev_err(dev, "failed create the DPHY regmap\n");
> + return PTR_ERR(dphy->regmap);
> + }
> +
> + dphy->phy_ref_clk = devm_clk_get(&pdev->dev, "phy_ref");
> + if (IS_ERR(dphy->phy_ref_clk)) {
> + dev_err(dev, "failed to get phy_ref clock\n");
> + return PTR_ERR(dphy->phy_ref_clk);
> + }
> +
> + dev_set_drvdata(dev, dphy);
> +
> + phy = devm_phy_create(dev, np, &dsim_dphy_phy_ops);
> + if (IS_ERR(phy)) {
> + dev_err(dev, "failed to create phy %ld\n", PTR_ERR(phy));
> + return PTR_ERR(phy);
> + }
> + phy_set_drvdata(phy, dphy);
> +
> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +
> + return PTR_ERR_OR_ZERO(phy_provider);
> +}
> +
> +static struct platform_driver dsim_dphy_driver = {
> + .probe = dsim_dphy_probe,
> + .driver = {
> + .name = "sec-dsim-dphy",
"sec" it's too generic, what if next time we have another one from
Samsung? sec2? Please choose a name matching the actual component.
> + .of_match_table = dsim_dphy_of_match,
> + }
> +};
> +module_platform_driver(dsim_dphy_driver);
> +
> +MODULE_AUTHOR("Jagan Teki <[email protected]>");
> +MODULE_DESCRIPTION("Samsung SEC MIPI DSIM DPHY driver");> +MODULE_LICENSE("GPL");
>
Best regards,
Krzysztof
Hi Laurent,
On Thu, Jun 24, 2021 at 3:53 AM Laurent Pinchart
<[email protected]> wrote:
>
> Hi Jagan,
>
> Thank you for the patch.
>
> On Mon, Jun 21, 2021 at 12:54:17PM +0530, Jagan Teki wrote:
> > Samsung SEC MIPI DSIM Bridge controller is MIPI DSI bridge
> > available in NXP's i.MX8M Mini and Nano Processors.
> >
> > Add bridge driver for it.
> >
> > Cc: Andrzej Hajda <[email protected]>
> > Cc: Neil Armstrong <[email protected]>
> > Cc: Robert Foss <[email protected]>
> > Cc: Laurent Pinchart <[email protected]>
> > Signed-off-by: Jagan Teki <[email protected]>
> > ---
> > drivers/gpu/drm/bridge/Kconfig | 15 +
> > drivers/gpu/drm/bridge/Makefile | 1 +
> > drivers/gpu/drm/bridge/sec-dsim.c | 1535 +++++++++++++++++++++++++++++
> > 3 files changed, 1551 insertions(+)
> > create mode 100644 drivers/gpu/drm/bridge/sec-dsim.c
> >
> > diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> > index 19109c0b5481..a183eb165a35 100644
> > --- a/drivers/gpu/drm/bridge/Kconfig
> > +++ b/drivers/gpu/drm/bridge/Kconfig
> > @@ -189,6 +189,21 @@ config DRM_PARADE_PS8640
> > The PS8640 is a high-performance and low-power
> > MIPI DSI to eDP converter
> >
> > +config DRM_SEC_MIPI_DSIM
> > + tristate "Samsung SEC MIPI DSIM Bridge controller"
> > + depends on DRM
> > + depends on COMMON_CLK
> > + depends on OF && HAS_IOMEM
> > + select DRM_KMS_HELPER
> > + select DRM_MIPI_DSI
> > + select DRM_PANEL_BRIDGE
> > + select GENERIC_PHY_MIPI_DPHY
> > + select MFD_SYSCON
> > + select REGMAP_MMIO
> > + help
> > + This enables the Samsung SEC MIPI DSIM Bridge controller as
> > + for example found on NXP's i.MX8M Mini and Nano Processors.
> > +
> > config DRM_SIL_SII8620
> > tristate "Silicon Image SII8620 HDMI/MHL bridge"
> > depends on OF
> > diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
> > index 88e4edf81087..ff802a4ffe65 100644
> > --- a/drivers/gpu/drm/bridge/Makefile
> > +++ b/drivers/gpu/drm/bridge/Makefile
> > @@ -12,6 +12,7 @@ obj-$(CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW) += megachips-stdpxxxx-ge-b850v
> > obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
> > obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
> > obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o
> > +obj-$(CONFIG_DRM_SEC_MIPI_DSIM) += sec-dsim.o
> > obj-$(CONFIG_DRM_SIL_SII8620) += sil-sii8620.o
> > obj-$(CONFIG_DRM_SII902X) += sii902x.o
> > obj-$(CONFIG_DRM_SII9234) += sii9234.o
> > diff --git a/drivers/gpu/drm/bridge/sec-dsim.c b/drivers/gpu/drm/bridge/sec-dsim.c
> > new file mode 100644
> > index 000000000000..5b6645bb94e7
> > --- /dev/null
> > +++ b/drivers/gpu/drm/bridge/sec-dsim.c
> > @@ -0,0 +1,1535 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Samsung SEC MIPI DSIM Bridge
> > + *
> > + * Copyright (C) 2018 NXP
> > + * Copyright (c) 2014 Samsung Electronics Co., Ltd
> > + * Copyright (C) 2021 Amarula Solutions(India)
> > + *
> > + * Based on the drivers/gpu/drm/exynos/exynos_drm_dsi.c
> > + *
> > + * Authors:
> > + * Tomasz Figa <[email protected]>
> > + * Andrzej Hajda <[email protected]>
> > + * Fancy Fang <[email protected]>
> > + * Jagan Teki <[email protected]>
> > + */
> > +
> > +#include <asm/unaligned.h>
> > +#include <linux/bitfield.h>
> > +#include <linux/clk.h>
> > +#include <linux/completion.h>
> > +#include <linux/delay.h>
> > +#include <linux/module.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_graph.h>
> > +#include <linux/phy/phy.h>
> > +#include <linux/regmap.h>
> > +
> > +#include <drm/drm_atomic_helper.h>
> > +#include <drm/drm_bridge.h>
> > +#include <drm/drm_mipi_dsi.h>
> > +#include <drm/drm_panel.h>
> > +#include <drm/drm_of.h>
> > +#include <drm/drm_print.h>
> > +
> > +#include <video/mipi_display.h>
> > +
> > +#define DRIVER_NAME "sec-dsim"
> > +
> > +/* dsim registers */
> > +#define DSIM_VERSION 0x00
> > +#define DSIM_STATUS 0x04
> > +#define DSIM_RGB_STATUS 0x08
> > +#define DSIM_SWRST 0x0c
> > +#define DSIM_CLKCTRL 0x10
> > +#define DSIM_TIMEOUT 0x14
> > +#define DSIM_CONFIG 0x18
> > +#define DSIM_ESCMODE 0x1c
> > +#define DSIM_MDRESOL 0x20
> > +#define DSIM_MVPORCH 0x24
> > +#define DSIM_MHPORCH 0x28
> > +#define DSIM_MSYNC 0x2c
> > +#define DSIM_SDRESOL 0x30
> > +#define DSIM_INTSRC 0x34
> > +#define DSIM_INTMSK 0x38
> > +#define DSIM_PKTHDR 0x3c
> > +#define DSIM_PAYLOAD 0x40
> > +#define DSIM_RXFIFO 0x44
> > +#define DSIM_FIFOTHLD 0x48
> > +#define DSIM_FIFOCTRL 0x4c
> > +#define DSIM_MEMACCHR 0x50
> > +#define DSIM_MULTI_PKT 0x78
> > +#define DSIM_PLLCTRL_1G 0x90
> > +#define DSIM_PLLCTRL 0x94
> > +#define DSIM_PLLCTRL1 0x98
> > +#define DSIM_PLLCTRL2 0x9c
> > +#define DSIM_PLLTMR 0xa0
>
> Looking at the register set, it seems to match the Exynos 5433,
> supported by drivers/gpu/drm/exynos/exynos_drm_dsi.c. Can we leverage
> that driver instead of adding a new one for the same IP core ?
I thought the same initially, but the PLLOut computation seems
different than the one in the i.MX8MM Reference Manual. I need to find
whether this exynos_dsi is compatible or working on my i.MX8MM
platform and send the next version changes accordingly. thanks.
--
Jagan Teki,
Hi Fabio,
On Thu, Jun 24, 2021 at 8:18 AM Fabio Estevam <[email protected]> wrote:
>
> Hi Jagan/Laurent,
>
> On Wed, Jun 23, 2021 at 7:23 PM Laurent Pinchart
> <[email protected]> wrote:
>
> > Looking at the register set, it seems to match the Exynos 5433,
> > supported by drivers/gpu/drm/exynos/exynos_drm_dsi.c. Can we leverage
> > that driver instead of adding a new one for the same IP core ?
>
> Yes. there was an attempt from Michael in this direction:
> https://patchwork.kernel.org/project/dri-devel/cover/[email protected]/
Thanks for the reference, I will check it out and see I can send any
updated versions wrt my i.MX8MM platform.
Jagan.
Hi Jagan,
On Thu, Jun 24, 2021 at 05:42:43PM +0530, Jagan Teki wrote:
> On Thu, Jun 24, 2021 at 8:18 AM Fabio Estevam wrote:
> > On Wed, Jun 23, 2021 at 7:23 PM Laurent Pinchart wrote:
> >
> > > Looking at the register set, it seems to match the Exynos 5433,
> > > supported by drivers/gpu/drm/exynos/exynos_drm_dsi.c. Can we leverage
> > > that driver instead of adding a new one for the same IP core ?
> >
> > Yes. there was an attempt from Michael in this direction:
> > https://patchwork.kernel.org/project/dri-devel/cover/[email protected]/
>
> Thanks for the reference, I will check it out and see I can send any
> updated versions wrt my i.MX8MM platform.
Thanks.
I had a brief look at the exynos driver, and I think it should be turned
into a DRM bridge as part of this rework to be used with the i.MX8MM.
Is there someone from Samsung who could assist, at least to test the
changes ?
--
Regards,
Laurent Pinchart
Hi Laurent,
On Thu, Jun 24, 2021 at 5:48 PM Laurent Pinchart
<[email protected]> wrote:
>
> Hi Jagan,
>
> On Thu, Jun 24, 2021 at 05:42:43PM +0530, Jagan Teki wrote:
> > On Thu, Jun 24, 2021 at 8:18 AM Fabio Estevam wrote:
> > > On Wed, Jun 23, 2021 at 7:23 PM Laurent Pinchart wrote:
> > >
> > > > Looking at the register set, it seems to match the Exynos 5433,
> > > > supported by drivers/gpu/drm/exynos/exynos_drm_dsi.c. Can we leverage
> > > > that driver instead of adding a new one for the same IP core ?
> > >
> > > Yes. there was an attempt from Michael in this direction:
> > > https://patchwork.kernel.org/project/dri-devel/cover/[email protected]/
> >
> > Thanks for the reference, I will check it out and see I can send any
> > updated versions wrt my i.MX8MM platform.
>
> Thanks.
>
> I had a brief look at the exynos driver, and I think it should be turned
> into a DRM bridge as part of this rework to be used with the i.MX8MM.
>
> Is there someone from Samsung who could assist, at least to test the
> changes ?
I have hardware to verify it on i.MX8MM but from exynos I don't have
any contact from Samsung to suggest or test. Maybe I can add Tomasz
Figa while sending the changes?
I understand that there are 2 key implementations.
1. Adjust the exynos_drm_dsi.c by dropping component_ops as i.MX8MM
flow with LCDIF doesn't have component_ops (make sure it works with
exynos platform first)
2. Sec DSIM Bridge driver common cross Exynos and i.MX8MM platform
drivers or only one Sec DSIM bridge driver to handle both the
platforms by differentiating compatible and driver data
Any more suggestions would be appreciated?
Jagan.
On Thu, Jun 24, 2021 at 06:02:36PM +0530, Jagan Teki wrote:
> Hi Laurent,
>
> On Thu, Jun 24, 2021 at 5:48 PM Laurent Pinchart
> <[email protected]> wrote:
> >
> > Hi Jagan,
> >
> > On Thu, Jun 24, 2021 at 05:42:43PM +0530, Jagan Teki wrote:
> > > On Thu, Jun 24, 2021 at 8:18 AM Fabio Estevam wrote:
> > > > On Wed, Jun 23, 2021 at 7:23 PM Laurent Pinchart wrote:
> > > >
> > > > > Looking at the register set, it seems to match the Exynos 5433,
> > > > > supported by drivers/gpu/drm/exynos/exynos_drm_dsi.c. Can we leverage
> > > > > that driver instead of adding a new one for the same IP core ?
> > > >
> > > > Yes. there was an attempt from Michael in this direction:
> > > > https://patchwork.kernel.org/project/dri-devel/cover/[email protected]/
> > >
> > > Thanks for the reference, I will check it out and see I can send any
> > > updated versions wrt my i.MX8MM platform.
> >
> > Thanks.
> >
> > I had a brief look at the exynos driver, and I think it should be turned
> > into a DRM bridge as part of this rework to be used with the i.MX8MM.
> >
> > Is there someone from Samsung who could assist, at least to test the
> > changes ?
>
> I have hardware to verify it on i.MX8MM but from exynos I don't have
> any contact from Samsung to suggest or test. Maybe I can add Tomasz
> Figa while sending the changes?
Tomasz hasn't been working for Samsung for a loooong time (I've dropped
his Samsung address from the CC list for this reason).
> I understand that there are 2 key implementations.
>
> 1. Adjust the exynos_drm_dsi.c by dropping component_ops as i.MX8MM
> flow with LCDIF doesn't have component_ops (make sure it works with
> exynos platform first)
I think it should be turned into a real drm_bridge, it's currently
implemented based on drm_encoder.
> 2. Sec DSIM Bridge driver common cross Exynos and i.MX8MM platform
> drivers or only one Sec DSIM bridge driver to handle both the
> platforms by differentiating compatible and driver data
>
> Any more suggestions would be appreciated?
--
Regards,
Laurent Pinchart
Hi Jagan,
On Thu, Jun 24, 2021 at 9:32 AM Jagan Teki <[email protected]> wrote:
> > I had a brief look at the exynos driver, and I think it should be turned
> > into a DRM bridge as part of this rework to be used with the i.MX8MM.
> >
> > Is there someone from Samsung who could assist, at least to test the
> > changes ?
>
> I have hardware to verify it on i.MX8MM but from exynos I don't have
> any contact from Samsung to suggest or test. Maybe I can add Tomasz
> Figa while sending the changes?
Adding Inki Dae and Marek Szyprowski from Samsung who helped to review
Michael's series.
> I understand that there are 2 key implementations.
>
> 1. Adjust the exynos_drm_dsi.c by dropping component_ops as i.MX8MM
> flow with LCDIF doesn't have component_ops (make sure it works with
> exynos platform first)
> 2. Sec DSIM Bridge driver common cross Exynos and i.MX8MM platform
> drivers or only one Sec DSIM bridge driver to handle both the
> platforms by differentiating compatible and driver data
>
> Any more suggestions would be appreciated?
>
> Jagan.
On Thu, Jun 24, 2021 at 6:17 PM Laurent Pinchart
<[email protected]> wrote:
>
> On Thu, Jun 24, 2021 at 06:02:36PM +0530, Jagan Teki wrote:
> > Hi Laurent,
> >
> > On Thu, Jun 24, 2021 at 5:48 PM Laurent Pinchart
> > <[email protected]> wrote:
> > >
> > > Hi Jagan,
> > >
> > > On Thu, Jun 24, 2021 at 05:42:43PM +0530, Jagan Teki wrote:
> > > > On Thu, Jun 24, 2021 at 8:18 AM Fabio Estevam wrote:
> > > > > On Wed, Jun 23, 2021 at 7:23 PM Laurent Pinchart wrote:
> > > > >
> > > > > > Looking at the register set, it seems to match the Exynos 5433,
> > > > > > supported by drivers/gpu/drm/exynos/exynos_drm_dsi.c. Can we leverage
> > > > > > that driver instead of adding a new one for the same IP core ?
> > > > >
> > > > > Yes. there was an attempt from Michael in this direction:
> > > > > https://patchwork.kernel.org/project/dri-devel/cover/[email protected]/
> > > >
> > > > Thanks for the reference, I will check it out and see I can send any
> > > > updated versions wrt my i.MX8MM platform.
> > >
> > > Thanks.
> > >
> > > I had a brief look at the exynos driver, and I think it should be turned
> > > into a DRM bridge as part of this rework to be used with the i.MX8MM.
> > >
> > > Is there someone from Samsung who could assist, at least to test the
> > > changes ?
> >
> > I have hardware to verify it on i.MX8MM but from exynos I don't have
> > any contact from Samsung to suggest or test. Maybe I can add Tomasz
> > Figa while sending the changes?
>
> Tomasz hasn't been working for Samsung for a loooong time (I've dropped
> his Samsung address from the CC list for this reason).
Okay. I think exynos drm maintainers might help out here, but not sure of it.
>
> > I understand that there are 2 key implementations.
> >
> > 1. Adjust the exynos_drm_dsi.c by dropping component_ops as i.MX8MM
> > flow with LCDIF doesn't have component_ops (make sure it works with
> > exynos platform first)
>
> I think it should be turned into a real drm_bridge, it's currently
> implemented based on drm_encoder.
Yes, ie what I'm trying for.
Jagan.
On Thu, 24 Jun 2021 at 14:19, Laurent Pinchart
<[email protected]> wrote:
>
> Hi Jagan,
>
> On Thu, Jun 24, 2021 at 05:42:43PM +0530, Jagan Teki wrote:
> > On Thu, Jun 24, 2021 at 8:18 AM Fabio Estevam wrote:
> > > On Wed, Jun 23, 2021 at 7:23 PM Laurent Pinchart wrote:
> > >
> > > > Looking at the register set, it seems to match the Exynos 5433,
> > > > supported by drivers/gpu/drm/exynos/exynos_drm_dsi.c. Can we leverage
> > > > that driver instead of adding a new one for the same IP core ?
> > >
> > > Yes. there was an attempt from Michael in this direction:
> > > https://patchwork.kernel.org/project/dri-devel/cover/[email protected]/
> >
> > Thanks for the reference, I will check it out and see I can send any
> > updated versions wrt my i.MX8MM platform.
>
> Thanks.
>
> I had a brief look at the exynos driver, and I think it should be turned
> into a DRM bridge as part of this rework to be used with the i.MX8MM.
>
> Is there someone from Samsung who could assist, at least to test the
> changes ?
Yes, I mentioned few guys in reply to PHY. Around the DRM drivers you
can get in touch with:
Inki Dae <[email protected]>
Seung-Woo Kim <[email protected]>
Marek Szyprowski <[email protected]>
Andrzej Hajda <[email protected]>
The easiest testing of the display stack would be on Hardkernel's Odroid
XU4 (https://www.hardkernel.com/shop/odroid-xu4-special-price/) however
you will not test the DSI/DSIM directly (it has only HDMI port).
Best regards,
Krzysztof
Best regards,
Krzysztof
Hi Krzysztof,
On Fri, Jun 25, 2021 at 2:51 PM Krzysztof Kozlowski
<[email protected]> wrote:
>
> On Thu, 24 Jun 2021 at 14:19, Laurent Pinchart
> <[email protected]> wrote:
> >
> > Hi Jagan,
> >
> > On Thu, Jun 24, 2021 at 05:42:43PM +0530, Jagan Teki wrote:
> > > On Thu, Jun 24, 2021 at 8:18 AM Fabio Estevam wrote:
> > > > On Wed, Jun 23, 2021 at 7:23 PM Laurent Pinchart wrote:
> > > >
> > > > > Looking at the register set, it seems to match the Exynos 5433,
> > > > > supported by drivers/gpu/drm/exynos/exynos_drm_dsi.c. Can we leverage
> > > > > that driver instead of adding a new one for the same IP core ?
> > > >
> > > > Yes. there was an attempt from Michael in this direction:
> > > > https://patchwork.kernel.org/project/dri-devel/cover/[email protected]/
> > >
> > > Thanks for the reference, I will check it out and see I can send any
> > > updated versions wrt my i.MX8MM platform.
> >
> > Thanks.
> >
> > I had a brief look at the exynos driver, and I think it should be turned
> > into a DRM bridge as part of this rework to be used with the i.MX8MM.
> >
> > Is there someone from Samsung who could assist, at least to test the
> > changes ?
>
> Yes, I mentioned few guys in reply to PHY. Around the DRM drivers you
> can get in touch with:
> Inki Dae <[email protected]>
> Seung-Woo Kim <[email protected]>
> Marek Szyprowski <[email protected]>
> Andrzej Hajda <[email protected]>
Thanks for the information.
>
> The easiest testing of the display stack would be on Hardkernel's Odroid
> XU4 (https://www.hardkernel.com/shop/odroid-xu4-special-price/) however
> you will not test the DSI/DSIM directly (it has only HDMI port).
Look like I found one board with Exynos5430 with DSI. Does this SoC is
same as mainline Exynos5433?
Jagan.
On 25/06/2021 12:08, Jagan Teki wrote:
> Hi Krzysztof,
>
> On Fri, Jun 25, 2021 at 2:51 PM Krzysztof Kozlowski
> <[email protected]> wrote:
>>
>> On Thu, 24 Jun 2021 at 14:19, Laurent Pinchart
>> <[email protected]> wrote:
>>>
>>> Hi Jagan,
>>>
>>> On Thu, Jun 24, 2021 at 05:42:43PM +0530, Jagan Teki wrote:
>>>> On Thu, Jun 24, 2021 at 8:18 AM Fabio Estevam wrote:
>>>>> On Wed, Jun 23, 2021 at 7:23 PM Laurent Pinchart wrote:
>>>>>
>>>>>> Looking at the register set, it seems to match the Exynos 5433,
>>>>>> supported by drivers/gpu/drm/exynos/exynos_drm_dsi.c. Can we leverage
>>>>>> that driver instead of adding a new one for the same IP core ?
>>>>>
>>>>> Yes. there was an attempt from Michael in this direction:
>>>>> https://patchwork.kernel.org/project/dri-devel/cover/[email protected]/
>>>>
>>>> Thanks for the reference, I will check it out and see I can send any
>>>> updated versions wrt my i.MX8MM platform.
>>>
>>> Thanks.
>>>
>>> I had a brief look at the exynos driver, and I think it should be turned
>>> into a DRM bridge as part of this rework to be used with the i.MX8MM.
>>>
>>> Is there someone from Samsung who could assist, at least to test the
>>> changes ?
>>
>> Yes, I mentioned few guys in reply to PHY. Around the DRM drivers you
>> can get in touch with:
>> Inki Dae <[email protected]>
>> Seung-Woo Kim <[email protected]>
>> Marek Szyprowski <[email protected]>
>> Andrzej Hajda <[email protected]>
>
> Thanks for the information.
>
>>
>> The easiest testing of the display stack would be on Hardkernel's Odroid
>> XU4 (https://www.hardkernel.com/shop/odroid-xu4-special-price/) however
>> you will not test the DSI/DSIM directly (it has only HDMI port).
>
> Look like I found one board with Exynos5430 with DSI. Does this SoC is
> same as mainline Exynos5433?
No, Exynos5430 is ARMv7. Looks like improvement over Exynos5422.
Exynos5422 has a very good support in mainline while Exynso5430 was
never touched at all.
Exynos5433 is ARMv8, although many things are shared with 5422. About
DSI I have no clue.
Best regards,
Krzysztof
Hi Jagan,
On 24.06.21 10:30, Krzysztof Kozlowski wrote:
> On 24/06/2021 04:48, Fabio Estevam wrote:
>> Hi Jagan/Laurent,
>>
>> On Wed, Jun 23, 2021 at 7:23 PM Laurent Pinchart
>> <[email protected]> wrote:
>>
>>> Looking at the register set, it seems to match the Exynos 5433,
>>> supported by drivers/gpu/drm/exynos/exynos_drm_dsi.c. Can we leverage
>>> that driver instead of adding a new one for the same IP core ?
>>
>> Yes. there was an attempt from Michael in this direction:
>> https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.kernel.org%2Fproject%2Fdri-devel%2Fcover%2F20200911135413.3654800-1-m.tretter%40pengutronix.de%2F&data=04%7C01%7Cfrieder.schrempf%40kontron.de%7C52db05459ef0462d5a9b08d936eab1ba%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637601203901391193%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=LTYk9kpUeB9bgfRITQT6wIij3XTOIk37AHXbzQ2UI4Y%3D&reserved=0
>
> That's the proper direction (maybe as Marek suggested - sharing common
> code like for Analogix DP), not duplicating a driver.
>
Just to make sure that you are aware of the previous patches and discussions here are some additional pointers:
* i.MX8MM glue code from Marek (+ Cc): [1]
* DPHY driver from Marek: [2]
* General discussion about driver implementation: [3]
* Daniel's (+ Cc) suggested direction to move forward: [4]
It looks like you already did a fork of the Exynos driver, so your approach might be generally in line with what Daniel suggested.
Best regards
Frieder
[1] https://patchwork.kernel.org/project/linux-arm-kernel/patch/[email protected]/
[2] https://patchwork.kernel.org/project/linux-arm-kernel/patch/[email protected]/
[3] https://patchwork.kernel.org/project/dri-devel/patch/[email protected]/
[4] https://patchwork.kernel.org/project/dri-devel/patch/[email protected]/#23995147
Hi Jagan,
> Subject: [RFC PATCH 0/9] arm64: imx8mm: Add MIPI DSI support
>
> This series support MIPI DSI on i.MX8MM.
>
> It worked directly with existing mxsfb driver but the SEC DSIM timings has to
> be validate and tested through all platforms, ie reason I'm sending it as RFC.
>
> Tested on Engicam i.Core MX8M Mini SoM.
Thanks for the work.
>
> patch 1: dt-bindings for SEC MIPI DSIM
>
> patch 2: SEC MIPI DSIM bridge driver
>
> patch 3: dt-bindings for SEC DSIM DPHY
>
> patch 4: SEC DSIM DPHY driver
>
> patch 5: MIPI DPHY reset enable in blk-ctl
>
> patch 6: display mix blk ctl node
>
> patch 7: eLCDIF node
>
> patch 8: MIPI DSI pipeline nodes
>
> patch 9: Enable LVDS panel on EDIMM2.2
>
> Note:
> - all these patches on top of Peng Fan's blk-ctl driver.
Would you please update to use V8 patchset?
And the dtb:
https://patchwork.kernel.org/project/linux-arm-kernel/
patch/[email protected]/
Thanks,
Peng.
> - anyone interest, please have a look on this repo
>
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.
> com%2Fopenedev%2Flinux%2Fcommits%2Fimx8mm&data=04%7C01%7
> Cpeng.fan%40nxp.com%7C8185c94655404000316208d93485a285%7C686ea
> 1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637598570833578734%7CU
> nknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI
> 6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=HKAHBv4YM0G6mVV3bq
> oPOyNb2mQTH03YSBU8RnrJmlE%3D&reserved=0
>
> Any inputs?
> Jagan.
>
> Jagan Teki (9):
> dt-bindings: display: bridge: Add Samsung SEC MIPI DSIM bindings
> drm: bridge: Add Samsung SEC MIPI DSIM bridge driver
> dt-bindings: phy: Add SEC DSIM DPHY bindings
> phy: samsung: Add SEC DSIM DPHY driver
> soc: imx8mm: blk-ctl: Add MIPI DPHY reset enable
> arm64: dts: imx8mm: Add display mix blk ctl
> arm64: dts: imx8mm: Add eLCDIF node support
> arm64: dts: imx8mm: Add MIPI DSI pipeline
> arm64: dts: imx8mm-icore: Enable LVDS panel for EDIMM2.2
>
> .../display/bridge/samsung,sec-dsim.yaml | 184 ++
> .../bindings/phy/samsung,sec-dsim-dphy.yaml | 56 +
> .../freescale/imx8mm-icore-mx8mm-edimm2.2.dts | 90 +
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 104 ++
> drivers/gpu/drm/bridge/Kconfig | 15 +
> drivers/gpu/drm/bridge/Makefile | 1 +
> drivers/gpu/drm/bridge/sec-dsim.c | 1535
> +++++++++++++++++
> drivers/phy/samsung/Kconfig | 9 +
> drivers/phy/samsung/Makefile | 1 +
> drivers/phy/samsung/phy-sec-dsim-dphy.c | 236 +++
> drivers/soc/imx/blk-ctl-imx8mm.c | 4 +
> include/dt-bindings/power/imx8mm-power.h | 5 +-
> 12 files changed, 2238 insertions(+), 2 deletions(-) create mode 100644
> Documentation/devicetree/bindings/display/bridge/samsung,sec-dsim.yaml
> create mode 100644
> Documentation/devicetree/bindings/phy/samsung,sec-dsim-dphy.yaml
> create mode 100644 drivers/gpu/drm/bridge/sec-dsim.c create mode
> 100644 drivers/phy/samsung/phy-sec-dsim-dphy.c
>
> --
> 2.25.1
Hi Frieder,
Thanks for sharing the details.
On Mon, Jun 28, 2021 at 1:49 PM Frieder Schrempf
<[email protected]> wrote:
>
> Hi Jagan,
>
> On 24.06.21 10:30, Krzysztof Kozlowski wrote:
> > On 24/06/2021 04:48, Fabio Estevam wrote:
> >> Hi Jagan/Laurent,
> >>
> >> On Wed, Jun 23, 2021 at 7:23 PM Laurent Pinchart
> >> <[email protected]> wrote:
> >>
> >>> Looking at the register set, it seems to match the Exynos 5433,
> >>> supported by drivers/gpu/drm/exynos/exynos_drm_dsi.c. Can we leverage
> >>> that driver instead of adding a new one for the same IP core ?
> >>
> >> Yes. there was an attempt from Michael in this direction:
> >> https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.kernel.org%2Fproject%2Fdri-devel%2Fcover%2F20200911135413.3654800-1-m.tretter%40pengutronix.de%2F&data=04%7C01%7Cfrieder.schrempf%40kontron.de%7C52db05459ef0462d5a9b08d936eab1ba%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637601203901391193%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=LTYk9kpUeB9bgfRITQT6wIij3XTOIk37AHXbzQ2UI4Y%3D&reserved=0
> >
> > That's the proper direction (maybe as Marek suggested - sharing common
> > code like for Analogix DP), not duplicating a driver.
> >
>
> Just to make sure that you are aware of the previous patches and discussions here are some additional pointers:
>
> * i.MX8MM glue code from Marek (+ Cc): [1]
> * DPHY driver from Marek: [2]
> * General discussion about driver implementation: [3]
> * Daniel's (+ Cc) suggested direction to move forward: [4]
It Looks like Daniel's suggestion is to have a common bridge driver
without sharing a code between platforms. It makes sense and clean but
the key issues lie on the exynos side, the exynos drm drives require
potential changes and tests, which indeed are hard but possible -
IMHO. However there is another issue with component_ops the i.MX8M
side MXSFB doesn't use any component_ops but the exynos are fully
component aware.
>
> It looks like you already did a fork of the Exynos driver, so your approach might be generally in line with what Daniel suggested.
I did use PMS computation from exynos and reference driver from imx8
tree. Last 2 days I worked on exynos_drm_dsi.c (with some additions)
and converted a bridge driver and it worked on my i.MX8MM platform.
Right now, I'm checking the possible implementations and will come
back to my approach for further comments.
Jagan.
Hi Peng,
On Tue, Jun 29, 2021 at 12:40 PM Peng Fan (OSS) <[email protected]> wrote:
>
> Hi Jagan,
>
> > Subject: [RFC PATCH 0/9] arm64: imx8mm: Add MIPI DSI support
> >
> > This series support MIPI DSI on i.MX8MM.
> >
> > It worked directly with existing mxsfb driver but the SEC DSIM timings has to
> > be validate and tested through all platforms, ie reason I'm sending it as RFC.
> >
> > Tested on Engicam i.Core MX8M Mini SoM.
>
> Thanks for the work.
>
> >
> > patch 1: dt-bindings for SEC MIPI DSIM
> >
> > patch 2: SEC MIPI DSIM bridge driver
> >
> > patch 3: dt-bindings for SEC DSIM DPHY
> >
> > patch 4: SEC DSIM DPHY driver
> >
> > patch 5: MIPI DPHY reset enable in blk-ctl
> >
> > patch 6: display mix blk ctl node
> >
> > patch 7: eLCDIF node
> >
> > patch 8: MIPI DSI pipeline nodes
> >
> > patch 9: Enable LVDS panel on EDIMM2.2
> >
> > Note:
> > - all these patches on top of Peng Fan's blk-ctl driver.
>
> Would you please update to use V8 patchset?
>
> And the dtb:
> https://patchwork.kernel.org/project/linux-arm-kernel/
> patch/[email protected]/
Thanks for the details.
I will rebase to use this series and test. Will update on blk-ctl patches.
Thanks,
Jagan.