2021-06-24 12:21:47

by Rajan Vaja

Subject: [PATCH v5 0/4] clk: zynqmp: Add firmware specific clock flags

Currently firmware is maintaining CCF specific flags and provides to
CCF as it is. But CCF flag numbers may change and that shouldn't mean
that the firmware needs to change. The firmware should have its own
'flag number space' that is distinct from the common clk framework's
'flag number space'. So use firmware specific clock flags in ZynqMP
clock driver instead of CCF flags.

Changes in v5:
- Added base commit
- Added patch #4 to handle divider specific read only flag

Changes in v4:
- Use if condition instead of ternary operator.

Changes in v3:
- Modify helper function signature to map zynqmp (common)flags with CCF
- Add helper function to map zynqmp (mux & divider)flags with CCF flags

Changes in v2:
- Add helper function to map zynqmp (common)flags with CCF flags.
- Mapped zynqmp clock flags with CCF flags from
zynqmp_clk_register_*() functions instead of
__zynqmp_clock_get_topology() which is changing the flags to struct
clk_init_data instead of the struct clock_topology.

Rajan Vaja (4):
clk: zynqmp: Use firmware specific common clock flags
clk: zynqmp: Use firmware specific divider clock flags
clk: zynqmp: Use firmware specific mux clock flags
clk: zynqmp: Handle divider specific read only flag

drivers/clk/zynqmp/clk-gate-zynqmp.c | 4 ++-
drivers/clk/zynqmp/clk-mux-zynqmp.c | 27 ++++++++++++++++--
drivers/clk/zynqmp/clk-zynqmp.h | 41 ++++++++++++++++++++++++++++
drivers/clk/zynqmp/clkc.c | 33 +++++++++++++++++++++-
drivers/clk/zynqmp/divider.c | 40 ++++++++++++++++++++++++---
drivers/clk/zynqmp/pll.c | 4 ++-
6 files changed, 140 insertions(+), 9 deletions(-)


base-commit: 6efb943b8616ec53a5e444193dccf1af9ad627b5
--
2.32.0.93.g670b81a

2021-06-24 12:22:01

by Rajan Vaja

Subject: [PATCH v5 4/4] clk: zynqmp: Handle divider specific read only flag

Add support for divider specific read only CCF flag
(CLK_DIVIDER_READ_ONLY).

Signed-off-by: Rajan Vaja <[email protected]>
---
drivers/clk/zynqmp/divider.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index c07423e03bc8..cb49281f9cf9 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -256,6 +256,11 @@ static const struct clk_ops zynqmp_clk_divider_ops = {
.set_rate = zynqmp_clk_divider_set_rate,
};

+static const struct clk_ops zynqmp_clk_divider_ro_ops = {
+ .recalc_rate = zynqmp_clk_divider_recalc_rate,
+ .round_rate = zynqmp_clk_divider_round_rate,
+};
+
/**
* zynqmp_clk_get_max_divisor() - Get maximum supported divisor from firmware.
* @clk_id: Id of clock
@@ -334,7 +339,10 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name,
return ERR_PTR(-ENOMEM);

init.name = name;
- init.ops = &zynqmp_clk_divider_ops;
+ if (nodes->type_flag & CLK_DIVIDER_READ_ONLY)
+ init.ops = &zynqmp_clk_divider_ro_ops;
+ else
+ init.ops = &zynqmp_clk_divider_ops;

init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);

--
2.32.0.93.g670b81a