From: Vijendar Mukunda <[email protected]>
ACP is a PCI audio device.
This patch adds PCI driver to bind to this device and get
PCI resources.
Signed-off-by: Vijendar Mukunda <[email protected]>
---
sound/soc/amd/vangogh/acp5x.h | 21 ++++++++
sound/soc/amd/vangogh/pci-acp5x.c | 87 +++++++++++++++++++++++++++++++
2 files changed, 108 insertions(+)
create mode 100644 sound/soc/amd/vangogh/acp5x.h
create mode 100644 sound/soc/amd/vangogh/pci-acp5x.c
diff --git a/sound/soc/amd/vangogh/acp5x.h b/sound/soc/amd/vangogh/acp5x.h
new file mode 100644
index 000000000000..a5e7f7cb65a1
--- /dev/null
+++ b/sound/soc/amd/vangogh/acp5x.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * AMD ALSA SoC PCM Driver
+ *
+ * Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved.
+ */
+
+#include "vg_chip_offset_byte.h"
+
+#define ACP5x_PHY_BASE_ADDRESS 0x1240000
+#define ACP_DEVICE_ID 0x15E2
+
+static inline u32 acp_readl(void __iomem *base_addr)
+{
+ return readl(base_addr - ACP5x_PHY_BASE_ADDRESS);
+}
+
+static inline void acp_writel(u32 val, void __iomem *base_addr)
+{
+ writel(val, base_addr - ACP5x_PHY_BASE_ADDRESS);
+}
diff --git a/sound/soc/amd/vangogh/pci-acp5x.c b/sound/soc/amd/vangogh/pci-acp5x.c
new file mode 100644
index 000000000000..e56d060a5cb9
--- /dev/null
+++ b/sound/soc/amd/vangogh/pci-acp5x.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// AMD Vangogh ACP PCI Driver
+//
+// Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved.
+
+#include <linux/pci.h>
+#include <linux/module.h>
+#include <linux/io.h>
+
+#include "acp5x.h"
+
+struct acp5x_dev_data {
+ void __iomem *acp5x_base;
+};
+
+static int snd_acp5x_probe(struct pci_dev *pci,
+ const struct pci_device_id *pci_id)
+{
+ struct acp5x_dev_data *adata;
+ int ret;
+ u32 addr;
+
+ if (pci->revision != 0x50)
+ return -ENODEV;
+
+ if (pci_enable_device(pci)) {
+ dev_err(&pci->dev, "pci_enable_device failed\n");
+ return -ENODEV;
+ }
+
+ ret = pci_request_regions(pci, "AMD ACP5x audio");
+ if (ret < 0) {
+ dev_err(&pci->dev, "pci_request_regions failed\n");
+ goto disable_pci;
+ }
+
+ adata = devm_kzalloc(&pci->dev, sizeof(struct acp5x_dev_data),
+ GFP_KERNEL);
+ if (!adata) {
+ ret = -ENOMEM;
+ goto release_regions;
+ }
+ addr = pci_resource_start(pci, 0);
+ adata->acp5x_base = devm_ioremap(&pci->dev, addr,
+ pci_resource_len(pci, 0));
+ if (!adata->acp5x_base) {
+ ret = -ENOMEM;
+ goto release_regions;
+ }
+ pci_set_master(pci);
+ pci_set_drvdata(pci, adata);
+
+release_regions:
+ pci_release_regions(pci);
+disable_pci:
+ pci_disable_device(pci);
+
+ return ret;
+}
+
+static void snd_acp5x_remove(struct pci_dev *pci)
+{
+ pci_release_regions(pci);
+ pci_disable_device(pci);
+}
+
+static const struct pci_device_id snd_acp5x_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, ACP_DEVICE_ID),
+ .class = PCI_CLASS_MULTIMEDIA_OTHER << 8,
+ .class_mask = 0xffffff },
+ { 0, },
+};
+MODULE_DEVICE_TABLE(pci, snd_acp5x_ids);
+
+static struct pci_driver acp5x_driver = {
+ .name = KBUILD_MODNAME,
+ .id_table = snd_acp5x_ids,
+ .probe = snd_acp5x_probe,
+ .remove = snd_acp5x_remove,
+};
+
+module_pci_driver(acp5x_driver);
+
+MODULE_AUTHOR("[email protected]");
+MODULE_DESCRIPTION("AMD Vangogh ACP PCI driver");
+MODULE_LICENSE("GPL v2");
--
2.17.1
On Wed, Jul 07, 2021 at 11:26:13AM +0530, Vijendar Mukunda wrote:
> +static inline u32 acp_readl(void __iomem *base_addr)
> +{
> + return readl(base_addr - ACP5x_PHY_BASE_ADDRESS);
> +}
I see this was the same for Renoir but it's weird that the read and
write functions are substracting rather than adding the base address
here. A comment might be good.
On 7/7/21 9:47 PM, Mark Brown wrote:
> On Wed, Jul 07, 2021 at 11:26:13AM +0530, Vijendar Mukunda wrote:
>
>> +static inline u32 acp_readl(void __iomem *base_addr)
>> +{
>> + return readl(base_addr - ACP5x_PHY_BASE_ADDRESS);
>> +}
>
> I see this was the same for Renoir but it's weird that the read and
> write functions are substracting rather than adding the base address
> here. A comment might be good.
>
We can modify code by providing relative offset from base address which
adds base address in readl and writel functions.
To make this change, we have to modify original header file.
To have sync with our HW team and Firmware teams, we are using same
common header file.
We will add comment in the code.