Commit dce7cd62754b5 ("x86/hyperv: Allow guests to enable InvariantTSC")
added the support for HV_X64_MSR_TSC_INVARIANT_CONTROL. Setting bit 0
of this synthetic MSR will allow hyper-v guests to report invariant TSC
CPU feature through CPUID. This comment adds this explanation to the code
and mentions where the Intel's generic platform init code reads this
feature bit from CPUID. The comment will help developers understand how
the two parts of the initialization (hyperV specific and non-hyperV
specific generic hw init) are related.
Signed-off-by: Ani Sinha <[email protected]>
---
arch/x86/kernel/cpu/mshyperv.c | 9 +++++++++
1 file changed, 9 insertions(+)
changelog:
v1: initial patch
v2: slight comment update based on received feedback.
diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c
index 715458b7729a..3b05dab3086e 100644
--- a/arch/x86/kernel/cpu/mshyperv.c
+++ b/arch/x86/kernel/cpu/mshyperv.c
@@ -368,6 +368,15 @@ static void __init ms_hyperv_init_platform(void)
machine_ops.crash_shutdown = hv_machine_crash_shutdown;
#endif
if (ms_hyperv.features & HV_ACCESS_TSC_INVARIANT) {
+ /*
+ * Writing to synthetic MSR 0x40000118 updates/changes the
+ * guest visible CPUIDs. Setting bit 0 of this MSR enables
+ * guests to report invariant TSC feature through CPUID
+ * instruction, CPUID 0x800000007/EDX, bit 8. See code in
+ * early_init_intel() where this bit is examined. The
+ * setting of this MSR bit should happen before init_intel()
+ * is called.
+ */
wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, 0x1);
setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
}
--
2.25.1
Ani Sinha <[email protected]> writes:
> Commit dce7cd62754b5 ("x86/hyperv: Allow guests to enable InvariantTSC")
> added the support for HV_X64_MSR_TSC_INVARIANT_CONTROL. Setting bit 0
> of this synthetic MSR will allow hyper-v guests to report invariant TSC
> CPU feature through CPUID. This comment adds this explanation to the code
> and mentions where the Intel's generic platform init code reads this
> feature bit from CPUID. The comment will help developers understand how
> the two parts of the initialization (hyperV specific and non-hyperV
> specific generic hw init) are related.
>
> Signed-off-by: Ani Sinha <[email protected]>
> ---
> arch/x86/kernel/cpu/mshyperv.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> changelog:
> v1: initial patch
> v2: slight comment update based on received feedback.
>
> diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c
> index 715458b7729a..3b05dab3086e 100644
> --- a/arch/x86/kernel/cpu/mshyperv.c
> +++ b/arch/x86/kernel/cpu/mshyperv.c
> @@ -368,6 +368,15 @@ static void __init ms_hyperv_init_platform(void)
> machine_ops.crash_shutdown = hv_machine_crash_shutdown;
> #endif
> if (ms_hyperv.features & HV_ACCESS_TSC_INVARIANT) {
> + /*
> + * Writing to synthetic MSR 0x40000118 updates/changes the
> + * guest visible CPUIDs. Setting bit 0 of this MSR enables
> + * guests to report invariant TSC feature through CPUID
> + * instruction, CPUID 0x800000007/EDX, bit 8. See code in
> + * early_init_intel() where this bit is examined. The
> + * setting of this MSR bit should happen before init_intel()
> + * is called.
> + */
This should be very clear now, thanks!
Reviewed-by: Vitaly Kuznetsov <[email protected]>
> wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, 0x1);
> setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
> }
--
Vitaly
From: Ani Sinha <[email protected]> Sent: Friday, July 16, 2021 6:33 AM
>
> Commit dce7cd62754b5 ("x86/hyperv: Allow guests to enable InvariantTSC")
> added the support for HV_X64_MSR_TSC_INVARIANT_CONTROL. Setting bit 0
> of this synthetic MSR will allow hyper-v guests to report invariant TSC
> CPU feature through CPUID. This comment adds this explanation to the code
> and mentions where the Intel's generic platform init code reads this
> feature bit from CPUID. The comment will help developers understand how
> the two parts of the initialization (hyperV specific and non-hyperV
> specific generic hw init) are related.
>
> Signed-off-by: Ani Sinha <[email protected]>
> ---
> arch/x86/kernel/cpu/mshyperv.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> changelog:
> v1: initial patch
> v2: slight comment update based on received feedback.
>
> diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c
> index 715458b7729a..3b05dab3086e 100644
> --- a/arch/x86/kernel/cpu/mshyperv.c
> +++ b/arch/x86/kernel/cpu/mshyperv.c
> @@ -368,6 +368,15 @@ static void __init ms_hyperv_init_platform(void)
> machine_ops.crash_shutdown = hv_machine_crash_shutdown;
> #endif
> if (ms_hyperv.features & HV_ACCESS_TSC_INVARIANT) {
> + /*
> + * Writing to synthetic MSR 0x40000118 updates/changes the
> + * guest visible CPUIDs. Setting bit 0 of this MSR enables
> + * guests to report invariant TSC feature through CPUID
> + * instruction, CPUID 0x800000007/EDX, bit 8. See code in
> + * early_init_intel() where this bit is examined. The
> + * setting of this MSR bit should happen before init_intel()
> + * is called.
> + */
> wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, 0x1);
> setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
> }
> --
> 2.25.1
Reviewed-by: Michael Kelley <[email protected]>
On Fri, Jul 16, 2021 at 07:02:45PM +0530, Ani Sinha wrote:
> Commit dce7cd62754b5 ("x86/hyperv: Allow guests to enable InvariantTSC")
> added the support for HV_X64_MSR_TSC_INVARIANT_CONTROL. Setting bit 0
> of this synthetic MSR will allow hyper-v guests to report invariant TSC
> CPU feature through CPUID. This comment adds this explanation to the code
> and mentions where the Intel's generic platform init code reads this
> feature bit from CPUID. The comment will help developers understand how
> the two parts of the initialization (hyperV specific and non-hyperV
> specific generic hw init) are related.
>
> Signed-off-by: Ani Sinha <[email protected]>
Applied to hyperv-next. Thanks.