2021-07-19 12:34:25

by Lokesh Vutla

Subject: [PATCH 0/4] arm64: dts: ti: k3-am64: Add PWM nodes

Add epwm and ecap nodes for AM64 boards.

Lokesh Vutla (4):
arm64: dts: ti: k3-am64-main: Add epwm nodes
arm64: dts: ti: k3-am64-main: Add ecap pwm nodes
arm64: dts: ti: k3-am642-sk: Add ecap0 node
arm64: dts: ti: k3-am642-evm: Add ecap0 node

arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 114 +++++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am642-evm.dts | 12 +++
arch/arm64/boot/dts/ti/k3-am642-sk.dts | 12 +++
3 files changed, 138 insertions(+)

--
2.30.0

2021-07-19 12:34:39

by Lokesh Vutla

Subject: [PATCH 3/4] arm64: dts: ti: k3-am642-sk: Add ecap0 node

ecap0 can be configured to use pad ECAP0_IN_APWM_OUT (D18) which has a
signal connected to Pin 1 of J3. Add support for adding this pinmux so
that pwm can be observed on pin 1 of Header J3

Signed-off-by: Lokesh Vutla <[email protected]>
Signed-off-by: Vignesh Raghavendra <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am642-sk.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index d3aa2901e6fd..eb0d10e6e787 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -210,6 +210,12 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
>;
};
+
+ main_ecap0_pins_default: main-ecap0-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
+ >;
+ };
};

&mcu_uart0 {
@@ -453,3 +459,9 @@ &pcie0_rc {
&pcie0_ep {
status = "disabled";
};
+
+&ecap0 {
+ /* PWM is available on Pin 1 of header J3 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_ecap0_pins_default>;
+};
--
2.30.0

2021-07-19 12:36:08

by Lokesh Vutla

Subject: [PATCH 4/4] arm64: dts: ti: k3-am642-evm: Add ecap0 node

ecap0 can be configured to use pad ECAP0_IN_APWM_OUT (D18) which has a
signal connected to Pin 1 of J12 on EVM. Add support for adding this
pinmux so that pwm can be observed on pin 1 of Header J12

Signed-off-by: Lokesh Vutla <[email protected]>
Signed-off-by: Vignesh Raghavendra <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am642-evm.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index 030712221188..7da1238cb1d6 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -288,6 +288,12 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
>;
};
+
+ main_ecap0_pins_default: main-ecap0-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
+ >;
+ };
};

&main_uart0 {
@@ -574,3 +580,9 @@ &pcie0_ep {
num-lanes = <1>;
status = "disabled";
};
+
+&ecap0 {
+ /* PWM is available on Pin 1 of header J12 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_ecap0_pins_default>;
+};
--
2.30.0

2021-07-19 16:08:01

by Nishanth Menon

Subject: Re: [PATCH 4/4] arm64: dts: ti: k3-am642-evm: Add ecap0 node

On 14:24-20210719, Lokesh Vutla wrote:
> ecap0 can be configured to use pad ECAP0_IN_APWM_OUT (D18) which has a
> signal connected to Pin 1 of J12 on EVM. Add support for adding this
> pinmux so that pwm can be observed on pin 1 of Header J12
>
> Signed-off-by: Lokesh Vutla <[email protected]>
> Signed-off-by: Vignesh Raghavendra <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-am642-evm.dts | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> index 030712221188..7da1238cb1d6 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> @@ -288,6 +288,12 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
> AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
> >;
> };
> +
> + main_ecap0_pins_default: main-ecap0-pins-default {
> + pinctrl-single,pins = <
> + AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
> + >;
> + };
> };
>
> &main_uart0 {
> @@ -574,3 +580,9 @@ &pcie0_ep {
> num-lanes = <1>;
> status = "disabled";
> };
> +
> +&ecap0 {
> + /* PWM is available on Pin 1 of header J12 */
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_ecap0_pins_default>;
> +};
> --
> 2.30.0
>

Do the other ecap and pwm nodes need to be disabled since they may not
be pinned out?

--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D

2021-07-20 01:49:20

by Nishanth Menon

Subject: Re: [PATCH 3/4] arm64: dts: ti: k3-am642-sk: Add ecap0 node

On 14:24-20210719, Lokesh Vutla wrote:
> ecap0 can be configured to use pad ECAP0_IN_APWM_OUT (D18) which has a
> signal connected to Pin 1 of J3. Add support for adding this pinmux so
> that pwm can be observed on pin 1 of Header J3
>
> Signed-off-by: Lokesh Vutla <[email protected]>
> Signed-off-by: Vignesh Raghavendra <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-am642-sk.dts | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> index d3aa2901e6fd..eb0d10e6e787 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> @@ -210,6 +210,12 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
> AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
> >;
> };
> +
> + main_ecap0_pins_default: main-ecap0-pins-default {
> + pinctrl-single,pins = <
> + AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
> + >;
> + };
> };
>
> &mcu_uart0 {
> @@ -453,3 +459,9 @@ &pcie0_rc {
> &pcie0_ep {
> status = "disabled";
> };
> +
> +&ecap0 {
> + /* PWM is available on Pin 1 of header J3 */
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_ecap0_pins_default>;
> +};
> --
> 2.30.0
>


Do the other ecap and pwm nodes need to be disabled since they may not
be pinned out?

--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D

2021-07-20 05:20:13

by Lokesh Vutla

Subject: Re: [PATCH 3/4] arm64: dts: ti: k3-am642-sk: Add ecap0 node

On 19/07/21 8:53 pm, Nishanth Menon wrote:
> On 14:24-20210719, Lokesh Vutla wrote:
>> ecap0 can be configured to use pad ECAP0_IN_APWM_OUT (D18) which has a
>> signal connected to Pin 1 of J3. Add support for adding this pinmux so
>> that pwm can be observed on pin 1 of Header J3
>>
>> Signed-off-by: Lokesh Vutla <[email protected]>
>> Signed-off-by: Vignesh Raghavendra <[email protected]>
>> ---
>> arch/arm64/boot/dts/ti/k3-am642-sk.dts | 12 ++++++++++++
>> 1 file changed, 12 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
>> index d3aa2901e6fd..eb0d10e6e787 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
>> +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
>> @@ -210,6 +210,12 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
>> AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
>> >;
>> };
>> +
>> + main_ecap0_pins_default: main-ecap0-pins-default {
>> + pinctrl-single,pins = <
>> + AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
>> + >;
>> + };
>> };
>>
>> &mcu_uart0 {
>> @@ -453,3 +459,9 @@ &pcie0_rc {
>> &pcie0_ep {
>> status = "disabled";
>> };
>> +
>> +&ecap0 {
>> + /* PWM is available on Pin 1 of header J3 */
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&main_ecap0_pins_default>;
>> +};
>> --
>> 2.30.0
>>
>
>
> Do the other ecap and pwm nodes need to be disabled since they may not
> be pinned out?

Sure, Ill mark other ecap and epwm nodes as disabled. After looking at
schematics, epwm4 and 5 is pinned out on RPI header. But the header will most
likely be used for other use-cases. Shall I mark epwm4 and epwm5 disabled as
well with a comment with this information?

Thanks and regards,
Lokesh

>

2021-07-20 12:09:37

by Nishanth Menon

Subject: Re: [PATCH 3/4] arm64: dts: ti: k3-am642-sk: Add ecap0 node

On 10:46-20210720, Lokesh Vutla wrote:
>
>
> On 19/07/21 8:53 pm, Nishanth Menon wrote:
> > On 14:24-20210719, Lokesh Vutla wrote:
> >> ecap0 can be configured to use pad ECAP0_IN_APWM_OUT (D18) which has a
> >> signal connected to Pin 1 of J3. Add support for adding this pinmux so
> >> that pwm can be observed on pin 1 of Header J3
> >>
> >> Signed-off-by: Lokesh Vutla <[email protected]>
> >> Signed-off-by: Vignesh Raghavendra <[email protected]>
> >> ---
> >> arch/arm64/boot/dts/ti/k3-am642-sk.dts | 12 ++++++++++++
> >> 1 file changed, 12 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> >> index d3aa2901e6fd..eb0d10e6e787 100644
> >> --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> >> +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> >> @@ -210,6 +210,12 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
> >> AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
> >> >;
> >> };
> >> +
> >> + main_ecap0_pins_default: main-ecap0-pins-default {
> >> + pinctrl-single,pins = <
> >> + AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
> >> + >;
> >> + };
> >> };
> >>
> >> &mcu_uart0 {
> >> @@ -453,3 +459,9 @@ &pcie0_rc {
> >> &pcie0_ep {
> >> status = "disabled";
> >> };
> >> +
> >> +&ecap0 {
> >> + /* PWM is available on Pin 1 of header J3 */
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&main_ecap0_pins_default>;
> >> +};
> >> --
> >> 2.30.0
> >>
> >
> >
> > Do the other ecap and pwm nodes need to be disabled since they may not
> > be pinned out?
>
> Sure, Ill mark other ecap and epwm nodes as disabled. After looking at
> schematics, epwm4 and 5 is pinned out on RPI header. But the header will most
> likely be used for other use-cases. Shall I mark epwm4 and epwm5 disabled as
> well with a comment with this information?


Yes, please. Thanks.

--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D