Limits Management Hardware(LMh) is a hardware infrastructure on some
Qualcomm SoCs that can enforce temperature and current limits as programmed
by software for certain IPs like CPU. On many newer SoCs LMh is configured
by firmware/TZ and no programming is needed from the kernel side. But on
certain SoCs like sdm845 the firmware does not do a complete programming of
the h/w block. On such SoCs kernel software has to explicitly set up the
temperature limits and turn on various monitoring and enforcing algorithms
on the hardware.
Introduce support for enabling and programming various limit settings and
monitoring capabilities of Limits Management Hardware(LMh) associated with
cpu clusters. Also introduce support in cpufreq hardware driver to monitor
the interrupt associated with cpu frequency throttling so that this
information can be conveyed to the schdeuler via thermal pressure
interface.
With this patch series following cpu performance improvement(30-70%) is
observed on sdm845. The reasoning here is that without LMh being programmed
properly from the kernel, the default settings were enabling thermal
mitigation for CPUs at too low a temperature (around 70-75 degree C). This
in turn meant that many a time CPUs were never actually allowed to hit the
maximum possible/required frequencies.
UnixBench whets and dhry (./Run whets dhry)
System Benchmarks Index Score
Without LMh Support With LMh Support
1 copy test 1353.7 1773.2
8 copy tests 4473.6 7402.3
Sysbench cpu
sysbench cpu --threads=8 --time=60 --cpu-max-prime=100000 run
Without LMh Support With LMh Support
Events per
second 355 614
Avg Latency(ms) 21.84 13.02
v4->v5:
- Rebased to v5.14-rc5.
v3->v4:
- Rebased to v5.14-rc2.
v2->v3:
- Included patch adding dt binding documentation for LMh nodes.
- Rebased to v5.13
Thara Gopinath (6):
firmware: qcom_scm: Introduce SCM calls to access LMh
thermal: qcom: Add support for LMh driver
cpufreq: qcom-cpufreq-hw: Add dcvs interrupt support
arm64: dts: qcom: sdm45: Add support for LMh node
arm64: dts: qcom: sdm845: Remove cpufreq cooling devices for CPU
thermal zones
dt-bindings: thermal: Add dt binding for QCOM LMh
.../devicetree/bindings/thermal/qcom-lmh.yaml | 82 +++++++
arch/arm64/boot/dts/qcom/sdm845.dtsi | 162 ++----------
drivers/cpufreq/qcom-cpufreq-hw.c | 147 +++++++++++
drivers/firmware/qcom_scm.c | 58 +++++
drivers/firmware/qcom_scm.h | 4 +
drivers/thermal/qcom/Kconfig | 10 +
drivers/thermal/qcom/Makefile | 1 +
drivers/thermal/qcom/lmh.c | 232 ++++++++++++++++++
include/linux/qcom_scm.h | 14 ++
9 files changed, 574 insertions(+), 136 deletions(-)
create mode 100644 Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
create mode 100644 drivers/thermal/qcom/lmh.c
--
2.25.1
Introduce SCM calls to access/configure limits management hardware(LMH).
Reviewed-by: Bjorn Andersson <[email protected]>
Signed-off-by: Thara Gopinath <[email protected]>
---
v2->v3:
Added freeing of payload_buf after the scm call in qcom_scm_lmh_dcvsh as per
Matthias review comments.
v1->v2:
Changed the input parameters in qcom_scm_lmh_dcvsh from payload_buf and
payload_size to payload_fn, payload_reg, payload_val as per Bjorn's review
comments.
drivers/firmware/qcom_scm.c | 58 +++++++++++++++++++++++++++++++++++++
drivers/firmware/qcom_scm.h | 4 +++
include/linux/qcom_scm.h | 14 +++++++++
3 files changed, 76 insertions(+)
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 47ea2bd42b10..8a503753fe2a 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -1147,6 +1147,64 @@ int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
}
EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle);
+bool qcom_scm_lmh_dcvsh_available(void)
+{
+ return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_LMH, QCOM_SCM_LMH_LIMIT_DCVSH);
+}
+EXPORT_SYMBOL(qcom_scm_lmh_dcvsh_available);
+
+int qcom_scm_lmh_profile_change(u32 profile_id)
+{
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_LMH,
+ .cmd = QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE,
+ .arginfo = QCOM_SCM_ARGS(1, QCOM_SCM_VAL),
+ .args[0] = profile_id,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+
+ return qcom_scm_call(__scm->dev, &desc, NULL);
+}
+EXPORT_SYMBOL(qcom_scm_lmh_profile_change);
+
+int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
+ u64 limit_node, u32 node_id, u64 version)
+{
+ dma_addr_t payload_phys;
+ u32 *payload_buf;
+ int ret, payload_size = 5 * sizeof(u32);
+
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_LMH,
+ .cmd = QCOM_SCM_LMH_LIMIT_DCVSH,
+ .arginfo = QCOM_SCM_ARGS(5, QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_VAL,
+ QCOM_SCM_VAL, QCOM_SCM_VAL),
+ .args[1] = payload_size,
+ .args[2] = limit_node,
+ .args[3] = node_id,
+ .args[4] = version,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+
+ payload_buf = dma_alloc_coherent(__scm->dev, payload_size, &payload_phys, GFP_KERNEL);
+ if (!payload_buf)
+ return -ENOMEM;
+
+ payload_buf[0] = payload_fn;
+ payload_buf[1] = 0;
+ payload_buf[2] = payload_reg;
+ payload_buf[3] = 1;
+ payload_buf[4] = payload_val;
+
+ desc.args[0] = payload_phys;
+
+ ret = qcom_scm_call(__scm->dev, &desc, NULL);
+
+ dma_free_coherent(__scm->dev, payload_size, payload_buf, payload_phys);
+ return ret;
+}
+EXPORT_SYMBOL(qcom_scm_lmh_dcvsh);
+
static int qcom_scm_find_dload_address(struct device *dev, u64 *addr)
{
struct device_node *tcsr;
diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h
index 632fe3142462..d92156ceb3ac 100644
--- a/drivers/firmware/qcom_scm.h
+++ b/drivers/firmware/qcom_scm.h
@@ -114,6 +114,10 @@ extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc,
#define QCOM_SCM_SVC_HDCP 0x11
#define QCOM_SCM_HDCP_INVOKE 0x01
+#define QCOM_SCM_SVC_LMH 0x13
+#define QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE 0x01
+#define QCOM_SCM_LMH_LIMIT_DCVSH 0x10
+
#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15
#define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03
#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02
diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h
index 0165824c5128..c0475d1c9885 100644
--- a/include/linux/qcom_scm.h
+++ b/include/linux/qcom_scm.h
@@ -109,6 +109,12 @@ extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
u32 *resp);
extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
+
+extern int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
+ u64 limit_node, u32 node_id, u64 version);
+extern int qcom_scm_lmh_profile_change(u32 profile_id);
+extern bool qcom_scm_lmh_dcvsh_available(void);
+
#else
#include <linux/errno.h>
@@ -170,5 +176,13 @@ static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
{ return -ENODEV; }
+
+static inline int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
+ u64 limit_node, u32 node_id, u64 version)
+ { return -ENODEV; }
+
+static inline int qcom_scm_lmh_profile_change(u32 profile_id) { return -ENODEV; }
+
+static inline bool qcom_scm_lmh_dcvsh_available(void) { return -ENODEV; }
#endif
#endif
--
2.25.1
Add interrupt support to notify the kernel of h/w initiated frequency
throttling by LMh. Convey this to scheduler via thermal presssure
interface.
Signed-off-by: Thara Gopinath <[email protected]>
---
v4->v5:
- Changed throttle_lock from a spinlock to mutex to take potential
race between LMh de-init sequence and reenabling of
interrupts/polling after a thermal throttle event.
- Other cosmetic fixes as pointed out by Viresh.
v3->v4:
- Dropped devm_ versions of request_irq and free_irq as per comments on
mailing list.
- Introduced locking to prevent race between LMh de-init sequence and
re-enabling of interrupts/polling after a thermal throttle event.
- Moved the LMh de-init sequence to qcom_cpufreq_hw_lmh_exit as per
Viresh's review comments
- Code rearrangement as per Bjorn's review comments.
- Moved the interrupt handling to threaded interrupt handling since Steev
reported some scheduling while atomic bug on the mailing list.
v2->v3:
- Cosmetic fixes from review comments on the list.
- Moved all LMh initializations to qcom_cpufreq_hw_lmh_init.
- Added freeing of LMh interrupt and cancelling the polling worker to
qcom_cpufreq_hw_cpu_exit as per Viresh's suggestion.
- LMh interrupts are now tied to cpu dev and not cpufreq dev. This will be
useful for further generation of SoCs where the same interrupt signals
multiple cpu clusters.
v1->v2:
- Introduced qcom_cpufreq_hw_lmh_init to consolidate LMh related initializations
as per Viresh's review comment.
- Moved the piece of code restarting polling/re-enabling LMh interrupt to
qcom_lmh_dcvs_notify therby simplifying isr and timer callback as per Viresh's
suggestion.
- Droped cpus from qcom_cpufreq_data and instead using cpus from cpufreq_policy in
qcom_lmh_dcvs_notify as per Viresh's review comment.
- Dropped dt property qcom,support-lmh as per Bjorn's suggestion.
- Other minor/cosmetic fixes
drivers/cpufreq/qcom-cpufreq-hw.c | 147 ++++++++++++++++++++++++++++++
1 file changed, 147 insertions(+)
diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c
index f86859bf76f1..d9f6da99af3a 100644
--- a/drivers/cpufreq/qcom-cpufreq-hw.c
+++ b/drivers/cpufreq/qcom-cpufreq-hw.c
@@ -7,12 +7,14 @@
#include <linux/cpufreq.h>
#include <linux/init.h>
#include <linux/interconnect.h>
+#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/pm_opp.h>
#include <linux/slab.h>
+#include <linux/spinlock.h>
#define LUT_MAX_ENTRIES 40U
#define LUT_SRC GENMASK(31, 30)
@@ -22,10 +24,13 @@
#define CLK_HW_DIV 2
#define LUT_TURBO_IND 1
+#define HZ_PER_KHZ 1000
+
struct qcom_cpufreq_soc_data {
u32 reg_enable;
u32 reg_freq_lut;
u32 reg_volt_lut;
+ u32 reg_current_vote;
u32 reg_perf_state;
u8 lut_row_size;
};
@@ -34,6 +39,16 @@ struct qcom_cpufreq_data {
void __iomem *base;
struct resource *res;
const struct qcom_cpufreq_soc_data *soc_data;
+
+ /*
+ * Mutex to synchronize between de-init sequence and re-starting LMh
+ * polling/interrupts
+ */
+ struct mutex throttle_lock;
+ int throttle_irq;
+ bool cancel_throttle;
+ struct delayed_work throttle_work;
+ struct cpufreq_policy *policy;
};
static unsigned long cpu_hw_rate, xo_rate;
@@ -251,10 +266,92 @@ static void qcom_get_related_cpus(int index, struct cpumask *m)
}
}
+static unsigned int qcom_lmh_get_throttle_freq(struct qcom_cpufreq_data *data)
+{
+ unsigned int val = readl_relaxed(data->base + data->soc_data->reg_current_vote);
+
+ return (val & 0x3FF) * 19200;
+}
+
+static void qcom_lmh_dcvs_notify(struct qcom_cpufreq_data *data)
+{
+ unsigned long max_capacity, capacity, freq_hz, throttled_freq;
+ struct cpufreq_policy *policy = data->policy;
+ int cpu = cpumask_first(policy->cpus);
+ struct device *dev = get_cpu_device(cpu);
+ struct dev_pm_opp *opp;
+ unsigned int freq;
+
+ /*
+ * Get the h/w throttled frequency, normalize it using the
+ * registered opp table and use it to calculate thermal pressure.
+ */
+ freq = qcom_lmh_get_throttle_freq(data);
+ freq_hz = freq * HZ_PER_KHZ;
+
+ opp = dev_pm_opp_find_freq_floor(dev, &freq_hz);
+ if (IS_ERR(opp) && PTR_ERR(opp) == -ERANGE)
+ opp = dev_pm_opp_find_freq_ceil(dev, &freq_hz);
+
+ throttled_freq = freq_hz / HZ_PER_KHZ;
+
+ /* Update thermal pressure */
+
+ max_capacity = arch_scale_cpu_capacity(cpu);
+ capacity = mult_frac(max_capacity, throttled_freq, policy->cpuinfo.max_freq);
+
+ /* Don't pass boost capacity to scheduler */
+ if (capacity > max_capacity)
+ capacity = max_capacity;
+
+ arch_set_thermal_pressure(policy->cpus, max_capacity - capacity);
+
+ /*
+ * In the unlikely case policy is unregistered do not enable
+ * polling or h/w interrupt
+ */
+ mutex_lock(&data->throttle_lock);
+ if (data->cancel_throttle)
+ goto out;
+
+ /*
+ * If h/w throttled frequency is higher than what cpufreq has requested
+ * for, then stop polling and switch back to interrupt mechanism.
+ */
+ if (throttled_freq >= qcom_cpufreq_hw_get(cpu))
+ enable_irq(data->throttle_irq);
+ else
+ mod_delayed_work(system_highpri_wq, &data->throttle_work,
+ msecs_to_jiffies(10));
+
+out:
+ mutex_unlock(&data->throttle_lock);
+}
+
+static void qcom_lmh_dcvs_poll(struct work_struct *work)
+{
+ struct qcom_cpufreq_data *data;
+
+ data = container_of(work, struct qcom_cpufreq_data, throttle_work.work);
+ qcom_lmh_dcvs_notify(data);
+}
+
+static irqreturn_t qcom_lmh_dcvs_handle_irq(int irq, void *data)
+{
+ struct qcom_cpufreq_data *c_data = data;
+
+ /* Disable interrupt and enable polling */
+ disable_irq_nosync(c_data->throttle_irq);
+ qcom_lmh_dcvs_notify(c_data);
+
+ return 0;
+}
+
static const struct qcom_cpufreq_soc_data qcom_soc_data = {
.reg_enable = 0x0,
.reg_freq_lut = 0x110,
.reg_volt_lut = 0x114,
+ .reg_current_vote = 0x704,
.reg_perf_state = 0x920,
.lut_row_size = 32,
};
@@ -274,6 +371,51 @@ static const struct of_device_id qcom_cpufreq_hw_match[] = {
};
MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
+static int qcom_cpufreq_hw_lmh_init(struct cpufreq_policy *policy, int index)
+{
+ struct qcom_cpufreq_data *data = policy->driver_data;
+ struct platform_device *pdev = cpufreq_get_driver_data();
+ char irq_name[15];
+ int ret;
+
+ /*
+ * Look for LMh interrupt. If no interrupt line is specified /
+ * if there is an error, allow cpufreq to be enabled as usual.
+ */
+ data->throttle_irq = platform_get_irq(pdev, index);
+ if (data->throttle_irq <= 0)
+ return data->throttle_irq == -EPROBE_DEFER ? -EPROBE_DEFER : 0;
+
+ data->cancel_throttle = false;
+ data->policy = policy;
+
+ mutex_init(&data->throttle_lock);
+ INIT_DEFERRABLE_WORK(&data->throttle_work, qcom_lmh_dcvs_poll);
+
+ snprintf(irq_name, sizeof(irq_name), "dcvsh-irq-%u", policy->cpu);
+ ret = request_threaded_irq(data->throttle_irq, NULL, qcom_lmh_dcvs_handle_irq,
+ IRQF_ONESHOT, irq_name, data);
+ if (ret) {
+ dev_err(&pdev->dev, "Error registering %s: %d\n", irq_name, ret);
+ return 0;
+ }
+
+ return 0;
+}
+
+static void qcom_cpufreq_hw_lmh_exit(struct qcom_cpufreq_data *data)
+{
+ if (data->throttle_irq <= 0)
+ return;
+
+ mutex_lock(&data->throttle_lock);
+ data->cancel_throttle = true;
+ mutex_unlock(&data->throttle_lock);
+
+ cancel_delayed_work_sync(&data->throttle_work);
+ free_irq(data->throttle_irq, data);
+}
+
static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
{
struct platform_device *pdev = cpufreq_get_driver_data();
@@ -370,6 +512,10 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
dev_warn(cpu_dev, "failed to enable boost: %d\n", ret);
}
+ ret = qcom_cpufreq_hw_lmh_init(policy, index);
+ if (ret)
+ goto error;
+
return 0;
error:
kfree(data);
@@ -389,6 +535,7 @@ static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)
dev_pm_opp_remove_all_dynamic(cpu_dev);
dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);
+ qcom_cpufreq_hw_lmh_exit(data);
kfree(policy->freq_table);
kfree(data);
iounmap(base);
--
2.25.1
Now that Limits h/w is enabled to monitor thermal events around cpus and
throttle the cpu frequencies, remove cpufreq cooling device for the CPU
thermal zones which does software throttling of cpu frequencies.
Reviewed-by: Bjorn Andersson <[email protected]>
Signed-off-by: Thara Gopinath <[email protected]>
---
v2->v3:
- Improved the subject header and descrption to better reflect the
patch as per Matthias's review comments.
v1->v2:
Removing only cooling maps for cpu specific thermal zones keeping the
trip point definitions intact as per Daniel's suggestion. This is to
ensure that thermal zone temparature and trip violation information is
available to any userspace daemon monitoring these zones.
arch/arm64/boot/dts/qcom/sdm845.dtsi | 136 ---------------------------
1 file changed, 136 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index d90c896cbac8..b348c1efa1fb 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -4994,23 +4994,6 @@ cpu0_crit: cpu_crit {
type = "critical";
};
};
-
- cooling-maps {
- map0 {
- trip = <&cpu0_alert0>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- map1 {
- trip = <&cpu0_alert1>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
};
cpu1-thermal {
@@ -5038,23 +5021,6 @@ cpu1_crit: cpu_crit {
type = "critical";
};
};
-
- cooling-maps {
- map0 {
- trip = <&cpu1_alert0>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- map1 {
- trip = <&cpu1_alert1>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
};
cpu2-thermal {
@@ -5082,23 +5048,6 @@ cpu2_crit: cpu_crit {
type = "critical";
};
};
-
- cooling-maps {
- map0 {
- trip = <&cpu2_alert0>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- map1 {
- trip = <&cpu2_alert1>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
};
cpu3-thermal {
@@ -5126,23 +5075,6 @@ cpu3_crit: cpu_crit {
type = "critical";
};
};
-
- cooling-maps {
- map0 {
- trip = <&cpu3_alert0>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- map1 {
- trip = <&cpu3_alert1>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
};
cpu4-thermal {
@@ -5170,23 +5102,6 @@ cpu4_crit: cpu_crit {
type = "critical";
};
};
-
- cooling-maps {
- map0 {
- trip = <&cpu4_alert0>;
- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- map1 {
- trip = <&cpu4_alert1>;
- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
};
cpu5-thermal {
@@ -5214,23 +5129,6 @@ cpu5_crit: cpu_crit {
type = "critical";
};
};
-
- cooling-maps {
- map0 {
- trip = <&cpu5_alert0>;
- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- map1 {
- trip = <&cpu5_alert1>;
- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
};
cpu6-thermal {
@@ -5258,23 +5156,6 @@ cpu6_crit: cpu_crit {
type = "critical";
};
};
-
- cooling-maps {
- map0 {
- trip = <&cpu6_alert0>;
- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- map1 {
- trip = <&cpu6_alert1>;
- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
};
cpu7-thermal {
@@ -5302,23 +5183,6 @@ cpu7_crit: cpu_crit {
type = "critical";
};
};
-
- cooling-maps {
- map0 {
- trip = <&cpu7_alert0>;
- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- map1 {
- trip = <&cpu7_alert1>;
- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
};
aoss0-thermal {
--
2.25.1
Add LMh nodes for cpu cluster0 and cpu cluster1. Also add interrupt
support in cpufreq node to capture the LMh interrupt and let the scheduler
know of the max frequency throttling.
Reviewed-by: Bjorn Andersson <[email protected]>
Signed-off-by: Thara Gopinath <[email protected]>
---
v4->v5:
- Renamed dt binding property qcom,lmh-cpu to cpus as per
Rob Herring's review comments.
- Changed LMh reg space size from the wierd size 0x401 to 0x400.
v3->v4:
- Changed dt property qcom,lmh-cpu-id to qcom,lmh-cpu and made it
a phandle pointing to the cpu node instead of a number as per
Rob Herring's review comments.
- Added suffix -millicelsius to all temperature properties as per
Rob Herring's review comments.
v2->v3:
- Changed the LMh low and high trip to 94500 and 95000 mC from
74500 and 75000 mC. This was a bug that got introduced in v2.
v1->v2:
- Dropped dt property qcom,support-lmh as per Bjorn's review comments.
- Changed lmh compatible from generic to platform specific.
- Introduced properties specifying arm, low and high temp thresholds for LMh
as per Daniel's suggestion.
arch/arm64/boot/dts/qcom/sdm845.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 0a86fe71a66d..d90c896cbac8 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -3646,6 +3646,30 @@ swm: swm@c85 {
};
};
+ lmh_cluster1: lmh@17d70800 {
+ compatible = "qcom,sdm845-lmh";
+ reg = <0 0x17d70800 0 0x400>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ cpus = <&CPU4>;
+ qcom,lmh-temp-arm-millicelsius = <65000>;
+ qcom,lmh-temp-low-millicelsius = <94500>;
+ qcom,lmh-temp-high-millicelsius = <95000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ lmh_cluster0: lmh@17d78800 {
+ compatible = "qcom,sdm845-lmh";
+ reg = <0 0x17d78800 0 0x400>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ cpus = <&CPU0>;
+ qcom,lmh-temp-arm-millicelsius = <65000>;
+ qcom,lmh-temp-low-millicelsius = <94500>;
+ qcom,lmh-temp-high-millicelsius = <95000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
sound: sound {
};
@@ -4911,6 +4935,8 @@ cpufreq_hw: cpufreq@17d43000 {
reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
reg-names = "freq-domain0", "freq-domain1";
+ interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
+
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
--
2.25.1
Add dt binding documentation to describe Qualcomm
Limits Management Hardware node.
Signed-off-by: Thara Gopinath <[email protected]>
---
v4->v5:
- Renamed dt binding property qcom,lmh-cpu to cpus as per
Rob Herring's review comments.
- Fixed examples and consolidated to just one example.
- Other minor fixes as pointed out by Rob Herring.
v3->v4:
- Changed dt property qcom,lmh-cpu-id to qcom,lmh-cpu and made it
a phandle pointing to the cpu node instead of a number as per
Rob Herring's review comments.
- Added suffix -millicelsius to all temperature properties as per
Rob Herring's review comments.
- Dropped unnecessary #includes in the example as pointed out by Bjorn.
- Other minor fixes.
.../devicetree/bindings/thermal/qcom-lmh.yaml | 82 +++++++++++++++++++
1 file changed, 82 insertions(+)
create mode 100644 Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
diff --git a/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml b/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
new file mode 100644
index 000000000000..289e9a845600
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2021 Linaro Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/qcom-lmh.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Limits Management Hardware(LMh)
+
+maintainers:
+ - Thara Gopinath <[email protected]>
+
+description:
+ Limits Management Hardware(LMh) is a hardware infrastructure on some
+ Qualcomm SoCs that can enforce temperature and current limits as
+ programmed by software for certain IPs like CPU.
+
+properties:
+ compatible:
+ enum:
+ - qcom,sdm845-lmh
+
+ reg:
+ items:
+ - description: core registers
+
+ interrupts:
+ maxItems: 1
+
+ '#interrupt-cells':
+ const: 1
+
+ interrupt-controller: true
+
+ cpus:
+ description:
+ phandle of the first cpu in the LMh cluster
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ qcom,lmh-temp-arm-millicelsius:
+ description:
+ An integer expressing temperature threshold at which the LMh thermal
+ FSM is engaged.
+
+ qcom,lmh-temp-low-millicelsius:
+ description:
+ An integer expressing temperature threshold at which the state machine
+ will attempt to remove frequency throttling.
+
+ qcom,lmh-temp-high-millicelsius:
+ description:
+ An integer expressing temperature threshold at which the state machine
+ will attempt to throttle the frequency.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - '#interrupt-cells'
+ - interrupt-controller
+ - cpus
+ - qcom,lmh-temp-arm-millicelsius
+ - qcom,lmh-temp-low-millicelsius
+ - qcom,lmh-temp-high-millicelsius
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ lmh@17d70800 {
+ compatible = "qcom,sdm845-lmh";
+ reg = <0x17d70800 0x400>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ cpus = <&CPU4>;
+ qcom,lmh-temp-arm-millicelsius = <65000>;
+ qcom,lmh-temp-low-millicelsius = <94500>;
+ qcom,lmh-temp-high-millicelsius = <95000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
--
2.25.1
Driver enabling various pieces of Limits Management Hardware(LMh) for cpu
cluster0 and cpu cluster1 namely kick starting monitoring of temperature,
current, battery current violations, enabling reliability algorithm and
setting up various temperature limits.
The following has been explained in the cover letter. I am including this
here so that this remains in the commit message as well.
LMh is a hardware infrastructure on some Qualcomm SoCs that can enforce
temperature and current limits as programmed by software for certain IPs
like CPU. On many newer LMh is configured by firmware/TZ and no programming
is needed from the kernel side. But on certain SoCs like sdm845 the
firmware does not do a complete programming of the h/w. On such soc's
kernel software has to explicitly set up the temperature limits and turn on
various monitoring and enforcing algorithms on the hardware.
Tested-by: Steev Klimaszewski <[email protected]> # Lenovo Yoga C630
Signed-off-by: Thara Gopinath <[email protected]>
---
v4->v5:
- Minor change related to renaming of dt binding property qcom,lmh-cpu
to cpus as per Rob Herring's review comments.
v3->v4:
- Minor code re-arrangement and removal of redundant code as per Bjorn's
review comments
- Added suppress_bind_attrs to driver as per Bjorn's review comments.
- Changes to support changes in LMh dt node properties naming and types.
v2->v3:
- Rearranged enabling of various LMh subfunction and removed returning
on error in enabling any one subfunction as the different pieces can
operate and thus be enabled independently.
- Other minor cosmetic fixes.
v1->v2:
- Cosmetic and spelling fixes from review comments from Randy Dunlap
- Added irq_disable to lmh_irq_ops and removed disabling of irq from
lmh_handle_irq. Now cpufreq explicitly disables irq prior to
handling it as per Bjorn's suggestion.
- Rebased to new version of qcom_scm_lmh_dcvsh as changed in patch 1.
- Removed generic dt compatible string and introduced platform specific one
as per Bjorn's suggestion.
- Take arm, low and high temp thresholds for LMh from dt properties instead of
#defines in the driver as per Daniel's suggestion.
- Other minor fixes.
drivers/thermal/qcom/Kconfig | 10 ++
drivers/thermal/qcom/Makefile | 1 +
drivers/thermal/qcom/lmh.c | 232 ++++++++++++++++++++++++++++++++++
3 files changed, 243 insertions(+)
create mode 100644 drivers/thermal/qcom/lmh.c
diff --git a/drivers/thermal/qcom/Kconfig b/drivers/thermal/qcom/Kconfig
index 8d5ac2df26dc..7d942f71e532 100644
--- a/drivers/thermal/qcom/Kconfig
+++ b/drivers/thermal/qcom/Kconfig
@@ -31,3 +31,13 @@ config QCOM_SPMI_TEMP_ALARM
trip points. The temperature reported by the thermal sensor reflects the
real time die temperature if an ADC is present or an estimate of the
temperature based upon the over temperature stage value.
+
+config QCOM_LMH
+ tristate "Qualcomm Limits Management Hardware"
+ depends on ARCH_QCOM
+ help
+ This enables initialization of Qualcomm limits management
+ hardware(LMh). LMh allows for hardware-enforced mitigation for cpus based on
+ input from temperature and current sensors. On many newer Qualcomm SoCs
+ LMh is configured in the firmware and this feature need not be enabled.
+ However, on certain SoCs like sdm845 LMh has to be configured from kernel.
diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile
index 252ea7d9da0b..0fa2512042e7 100644
--- a/drivers/thermal/qcom/Makefile
+++ b/drivers/thermal/qcom/Makefile
@@ -5,3 +5,4 @@ qcom_tsens-y += tsens.o tsens-v2.o tsens-v1.o tsens-v0_1.o \
tsens-8960.o
obj-$(CONFIG_QCOM_SPMI_ADC_TM5) += qcom-spmi-adc-tm5.o
obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o
+obj-$(CONFIG_QCOM_LMH) += lmh.o
diff --git a/drivers/thermal/qcom/lmh.c b/drivers/thermal/qcom/lmh.c
new file mode 100644
index 000000000000..eafa7526eb8b
--- /dev/null
+++ b/drivers/thermal/qcom/lmh.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/*
+ * Copyright (C) 2021, Linaro Limited. All rights reserved.
+ */
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/irqdomain.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/of_platform.h>
+#include <linux/slab.h>
+#include <linux/qcom_scm.h>
+
+#define LMH_NODE_DCVS 0x44435653
+#define LMH_CLUSTER0_NODE_ID 0x6370302D
+#define LMH_CLUSTER1_NODE_ID 0x6370312D
+
+#define LMH_SUB_FN_THERMAL 0x54484D4C
+#define LMH_SUB_FN_CRNT 0x43524E54
+#define LMH_SUB_FN_REL 0x52454C00
+#define LMH_SUB_FN_BCL 0x42434C00
+
+#define LMH_ALGO_MODE_ENABLE 0x454E424C
+#define LMH_TH_HI_THRESHOLD 0x48494748
+#define LMH_TH_LOW_THRESHOLD 0x4C4F5700
+#define LMH_TH_ARM_THRESHOLD 0x41524D00
+
+#define LMH_REG_DCVS_INTR_CLR 0x8
+
+struct lmh_hw_data {
+ void __iomem *base;
+ struct irq_domain *domain;
+ int irq;
+};
+
+static irqreturn_t lmh_handle_irq(int hw_irq, void *data)
+{
+ struct lmh_hw_data *lmh_data = data;
+ int irq = irq_find_mapping(lmh_data->domain, 0);
+
+ /* Call the cpufreq driver to handle the interrupt */
+ if (irq)
+ generic_handle_irq(irq);
+
+ return 0;
+}
+
+static void lmh_enable_interrupt(struct irq_data *d)
+{
+ struct lmh_hw_data *lmh_data = irq_data_get_irq_chip_data(d);
+
+ /* Clear the existing interrupt */
+ writel(0xff, lmh_data->base + LMH_REG_DCVS_INTR_CLR);
+ enable_irq(lmh_data->irq);
+}
+
+static void lmh_disable_interrupt(struct irq_data *d)
+{
+ struct lmh_hw_data *lmh_data = irq_data_get_irq_chip_data(d);
+
+ disable_irq_nosync(lmh_data->irq);
+}
+
+static struct irq_chip lmh_irq_chip = {
+ .name = "lmh",
+ .irq_enable = lmh_enable_interrupt,
+ .irq_disable = lmh_disable_interrupt
+};
+
+static int lmh_irq_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
+{
+ struct lmh_hw_data *lmh_data = d->host_data;
+
+ irq_set_chip_and_handler(irq, &lmh_irq_chip, handle_simple_irq);
+ irq_set_chip_data(irq, lmh_data);
+
+ return 0;
+}
+
+static const struct irq_domain_ops lmh_irq_ops = {
+ .map = lmh_irq_map,
+ .xlate = irq_domain_xlate_onecell,
+};
+
+static int lmh_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct device_node *cpu_node;
+ struct lmh_hw_data *lmh_data;
+ int temp_low, temp_high, temp_arm, cpu_id, ret;
+ u32 node_id;
+
+ lmh_data = devm_kzalloc(dev, sizeof(*lmh_data), GFP_KERNEL);
+ if (!lmh_data)
+ return -ENOMEM;
+
+ lmh_data->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(lmh_data->base))
+ return PTR_ERR(lmh_data->base);
+
+ cpu_node = of_parse_phandle(np, "cpus", 0);
+ if (!cpu_node)
+ return -EINVAL;
+ cpu_id = of_cpu_node_to_id(cpu_node);
+ of_node_put(cpu_node);
+
+ ret = of_property_read_u32(np, "qcom,lmh-temp-high-millicelsius", &temp_high);
+ if (ret) {
+ dev_err(dev, "missing qcom,lmh-temp-high-millicelsius property\n");
+ return ret;
+ }
+
+ ret = of_property_read_u32(np, "qcom,lmh-temp-low-millicelsius", &temp_low);
+ if (ret) {
+ dev_err(dev, "missing qcom,lmh-temp-low-millicelsius property\n");
+ return ret;
+ }
+
+ ret = of_property_read_u32(np, "qcom,lmh-temp-arm-millicelsius", &temp_arm);
+ if (ret) {
+ dev_err(dev, "missing qcom,lmh-temp-arm-millicelsius property\n");
+ return ret;
+ }
+
+ /*
+ * Only sdm845 has lmh hardware currently enabled from hlos. If this is needed
+ * for other platforms, revisit this to check if the <cpu-id, node-id> should be part
+ * of a dt match table.
+ */
+ if (cpu_id == 0) {
+ node_id = LMH_CLUSTER0_NODE_ID;
+ } else if (cpu_id == 4) {
+ node_id = LMH_CLUSTER1_NODE_ID;
+ } else {
+ dev_err(dev, "Wrong CPU id associated with LMh node\n");
+ return -EINVAL;
+ }
+
+ if (!qcom_scm_lmh_dcvsh_available())
+ return -EINVAL;
+
+ ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_CRNT, LMH_ALGO_MODE_ENABLE, 1,
+ LMH_NODE_DCVS, node_id, 0);
+ if (ret)
+ dev_err(dev, "Error %d enabling current subfunction\n", ret);
+
+ ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_REL, LMH_ALGO_MODE_ENABLE, 1,
+ LMH_NODE_DCVS, node_id, 0);
+ if (ret)
+ dev_err(dev, "Error %d enabling reliability subfunction\n", ret);
+
+ ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_BCL, LMH_ALGO_MODE_ENABLE, 1,
+ LMH_NODE_DCVS, node_id, 0);
+ if (ret)
+ dev_err(dev, "Error %d enabling BCL subfunction\n", ret);
+
+ ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_ALGO_MODE_ENABLE, 1,
+ LMH_NODE_DCVS, node_id, 0);
+ if (ret) {
+ dev_err(dev, "Error %d enabling thermal subfunction\n", ret);
+ return ret;
+ }
+
+ ret = qcom_scm_lmh_profile_change(0x1);
+ if (ret) {
+ dev_err(dev, "Error %d changing profile\n", ret);
+ return ret;
+ }
+
+ /* Set default thermal trips */
+ ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_ARM_THRESHOLD, temp_arm,
+ LMH_NODE_DCVS, node_id, 0);
+ if (ret) {
+ dev_err(dev, "Error setting thermal ARM threshold%d\n", ret);
+ return ret;
+ }
+
+ ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_HI_THRESHOLD, temp_high,
+ LMH_NODE_DCVS, node_id, 0);
+ if (ret) {
+ dev_err(dev, "Error setting thermal HI threshold%d\n", ret);
+ return ret;
+ }
+
+ ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_LOW_THRESHOLD, temp_low,
+ LMH_NODE_DCVS, node_id, 0);
+ if (ret) {
+ dev_err(dev, "Error setting thermal ARM threshold%d\n", ret);
+ return ret;
+ }
+
+ lmh_data->irq = platform_get_irq(pdev, 0);
+ lmh_data->domain = irq_domain_add_linear(np, 1, &lmh_irq_ops, lmh_data);
+ if (!lmh_data->domain) {
+ dev_err(dev, "Error adding irq_domain\n");
+ return -EINVAL;
+ }
+
+ /* Disable the irq and let cpufreq enable it when ready to handle the interrupt */
+ irq_set_status_flags(lmh_data->irq, IRQ_NOAUTOEN);
+ ret = devm_request_irq(dev, lmh_data->irq, lmh_handle_irq,
+ IRQF_ONESHOT | IRQF_NO_SUSPEND,
+ "lmh-irq", lmh_data);
+ if (ret) {
+ dev_err(dev, "Error %d registering irq %x\n", ret, lmh_data->irq);
+ irq_domain_remove(lmh_data->domain);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct of_device_id lmh_table[] = {
+ { .compatible = "qcom,sdm845-lmh", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, lmh_table);
+
+static struct platform_driver lmh_driver = {
+ .probe = lmh_probe,
+ .driver = {
+ .name = "qcom-lmh",
+ .of_match_table = lmh_table,
+ .suppress_bind_attrs = true,
+ },
+};
+module_platform_driver(lmh_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("QCOM LMh driver");
--
2.25.1
Add dt binding documentation to describe Qualcomm
Limits Management Hardware node.
Signed-off-by: Thara Gopinath <[email protected]>
---
v4->v5:
- Renam
v3->v4:
- Changed dt property qcom,lmh-cpu-id to qcom,lmh-cpu and made it
a phandle pointing to the cpu node instead of a number as per
Rob Herring's review comments.
- Added suffix -millicelsius to all temperature properties as per
Rob Herring's review comments.
- Dropped unnecessary #includes in the example as pointed out by Bjorn.
- Other minor fixes.
.../devicetree/bindings/thermal/qcom-lmh.yaml | 82 +++++++++++++++++++
1 file changed, 82 insertions(+)
create mode 100644 Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
diff --git a/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml b/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
new file mode 100644
index 000000000000..289e9a845600
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2021 Linaro Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/qcom-lmh.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Limits Management Hardware(LMh)
+
+maintainers:
+ - Thara Gopinath <[email protected]>
+
+description:
+ Limits Management Hardware(LMh) is a hardware infrastructure on some
+ Qualcomm SoCs that can enforce temperature and current limits as
+ programmed by software for certain IPs like CPU.
+
+properties:
+ compatible:
+ enum:
+ - qcom,sdm845-lmh
+
+ reg:
+ items:
+ - description: core registers
+
+ interrupts:
+ maxItems: 1
+
+ '#interrupt-cells':
+ const: 1
+
+ interrupt-controller: true
+
+ cpus:
+ description:
+ phandle of the first cpu in the LMh cluster
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ qcom,lmh-temp-arm-millicelsius:
+ description:
+ An integer expressing temperature threshold at which the LMh thermal
+ FSM is engaged.
+
+ qcom,lmh-temp-low-millicelsius:
+ description:
+ An integer expressing temperature threshold at which the state machine
+ will attempt to remove frequency throttling.
+
+ qcom,lmh-temp-high-millicelsius:
+ description:
+ An integer expressing temperature threshold at which the state machine
+ will attempt to throttle the frequency.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - '#interrupt-cells'
+ - interrupt-controller
+ - cpus
+ - qcom,lmh-temp-arm-millicelsius
+ - qcom,lmh-temp-low-millicelsius
+ - qcom,lmh-temp-high-millicelsius
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ lmh@17d70800 {
+ compatible = "qcom,sdm845-lmh";
+ reg = <0x17d70800 0x400>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ cpus = <&CPU4>;
+ qcom,lmh-temp-arm-millicelsius = <65000>;
+ qcom,lmh-temp-low-millicelsius = <94500>;
+ qcom,lmh-temp-high-millicelsius = <95000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
--
2.25.1
On 09-08-21, 15:16, Thara Gopinath wrote:
> Add interrupt support to notify the kernel of h/w initiated frequency
> throttling by LMh. Convey this to scheduler via thermal presssure
> interface.
>
> Signed-off-by: Thara Gopinath <[email protected]>
> ---
>
> v4->v5:
> - Changed throttle_lock from a spinlock to mutex to take potential
> race between LMh de-init sequence and reenabling of
> interrupts/polling after a thermal throttle event.
> - Other cosmetic fixes as pointed out by Viresh.
How do you expect this to get merged ? I pick up this patch alone ?
--
viresh
On 8/9/21 10:47 PM, Viresh Kumar wrote:
> On 09-08-21, 15:16, Thara Gopinath wrote:
>> Add interrupt support to notify the kernel of h/w initiated frequency
>> throttling by LMh. Convey this to scheduler via thermal presssure
>> interface.
>>
>> Signed-off-by: Thara Gopinath <[email protected]>
>> ---
>>
>> v4->v5:
>> - Changed throttle_lock from a spinlock to mutex to take potential
>> race between LMh de-init sequence and reenabling of
>> interrupts/polling after a thermal throttle event.
>> - Other cosmetic fixes as pointed out by Viresh.
>
> How do you expect this to get merged ? I pick up this patch alone ?
Hi.
Yes, you can pick up this patch alone. This patch is standalone and has
no dependencies. Once you do that, I will drop it from my series.
>
--
Warm Regards
Thara (She/Her/Hers)
On 09/08/2021 21:15, Thara Gopinath wrote:
> Introduce SCM calls to access/configure limits management hardware(LMH).
>
> Reviewed-by: Bjorn Andersson <[email protected]>
> Signed-off-by: Thara Gopinath <[email protected]>
Hi Bjorn, Andy,
do you mind if I pick this patch along with patch 2/6 ?
Thanks
-- Daniel
> ---
>
> v2->v3:
> Added freeing of payload_buf after the scm call in qcom_scm_lmh_dcvsh as per
> Matthias review comments.
>
> v1->v2:
> Changed the input parameters in qcom_scm_lmh_dcvsh from payload_buf and
> payload_size to payload_fn, payload_reg, payload_val as per Bjorn's review
> comments.
>
> drivers/firmware/qcom_scm.c | 58 +++++++++++++++++++++++++++++++++++++
> drivers/firmware/qcom_scm.h | 4 +++
> include/linux/qcom_scm.h | 14 +++++++++
> 3 files changed, 76 insertions(+)
>
> diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
> index 47ea2bd42b10..8a503753fe2a 100644
> --- a/drivers/firmware/qcom_scm.c
> +++ b/drivers/firmware/qcom_scm.c
> @@ -1147,6 +1147,64 @@ int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
> }
> EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle);
>
> +bool qcom_scm_lmh_dcvsh_available(void)
> +{
> + return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_LMH, QCOM_SCM_LMH_LIMIT_DCVSH);
> +}
> +EXPORT_SYMBOL(qcom_scm_lmh_dcvsh_available);
> +
> +int qcom_scm_lmh_profile_change(u32 profile_id)
> +{
> + struct qcom_scm_desc desc = {
> + .svc = QCOM_SCM_SVC_LMH,
> + .cmd = QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE,
> + .arginfo = QCOM_SCM_ARGS(1, QCOM_SCM_VAL),
> + .args[0] = profile_id,
> + .owner = ARM_SMCCC_OWNER_SIP,
> + };
> +
> + return qcom_scm_call(__scm->dev, &desc, NULL);
> +}
> +EXPORT_SYMBOL(qcom_scm_lmh_profile_change);
> +
> +int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
> + u64 limit_node, u32 node_id, u64 version)
> +{
> + dma_addr_t payload_phys;
> + u32 *payload_buf;
> + int ret, payload_size = 5 * sizeof(u32);
> +
> + struct qcom_scm_desc desc = {
> + .svc = QCOM_SCM_SVC_LMH,
> + .cmd = QCOM_SCM_LMH_LIMIT_DCVSH,
> + .arginfo = QCOM_SCM_ARGS(5, QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_VAL,
> + QCOM_SCM_VAL, QCOM_SCM_VAL),
> + .args[1] = payload_size,
> + .args[2] = limit_node,
> + .args[3] = node_id,
> + .args[4] = version,
> + .owner = ARM_SMCCC_OWNER_SIP,
> + };
> +
> + payload_buf = dma_alloc_coherent(__scm->dev, payload_size, &payload_phys, GFP_KERNEL);
> + if (!payload_buf)
> + return -ENOMEM;
> +
> + payload_buf[0] = payload_fn;
> + payload_buf[1] = 0;
> + payload_buf[2] = payload_reg;
> + payload_buf[3] = 1;
> + payload_buf[4] = payload_val;
> +
> + desc.args[0] = payload_phys;
> +
> + ret = qcom_scm_call(__scm->dev, &desc, NULL);
> +
> + dma_free_coherent(__scm->dev, payload_size, payload_buf, payload_phys);
> + return ret;
> +}
> +EXPORT_SYMBOL(qcom_scm_lmh_dcvsh);
> +
> static int qcom_scm_find_dload_address(struct device *dev, u64 *addr)
> {
> struct device_node *tcsr;
> diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h
> index 632fe3142462..d92156ceb3ac 100644
> --- a/drivers/firmware/qcom_scm.h
> +++ b/drivers/firmware/qcom_scm.h
> @@ -114,6 +114,10 @@ extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc,
> #define QCOM_SCM_SVC_HDCP 0x11
> #define QCOM_SCM_HDCP_INVOKE 0x01
>
> +#define QCOM_SCM_SVC_LMH 0x13
> +#define QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE 0x01
> +#define QCOM_SCM_LMH_LIMIT_DCVSH 0x10
> +
> #define QCOM_SCM_SVC_SMMU_PROGRAM 0x15
> #define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03
> #define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02
> diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h
> index 0165824c5128..c0475d1c9885 100644
> --- a/include/linux/qcom_scm.h
> +++ b/include/linux/qcom_scm.h
> @@ -109,6 +109,12 @@ extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
> u32 *resp);
>
> extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
> +
> +extern int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
> + u64 limit_node, u32 node_id, u64 version);
> +extern int qcom_scm_lmh_profile_change(u32 profile_id);
> +extern bool qcom_scm_lmh_dcvsh_available(void);
> +
> #else
>
> #include <linux/errno.h>
> @@ -170,5 +176,13 @@ static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
>
> static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
> { return -ENODEV; }
> +
> +static inline int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
> + u64 limit_node, u32 node_id, u64 version)
> + { return -ENODEV; }
> +
> +static inline int qcom_scm_lmh_profile_change(u32 profile_id) { return -ENODEV; }
> +
> +static inline bool qcom_scm_lmh_dcvsh_available(void) { return -ENODEV; }
> #endif
> #endif
>
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
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<http://www.linaro.org/linaro-blog/> Blog
On Tue 17 Aug 08:17 CDT 2021, Daniel Lezcano wrote:
> On 09/08/2021 21:15, Thara Gopinath wrote:
> > Introduce SCM calls to access/configure limits management hardware(LMH).
> >
> > Reviewed-by: Bjorn Andersson <[email protected]>
> > Signed-off-by: Thara Gopinath <[email protected]>
>
> Hi Bjorn, Andy,
>
> do you mind if I pick this patch along with patch 2/6 ?
>
Please do!
Regards,
Bjorn
On 17/08/2021 16:07, Bjorn Andersson wrote:
> On Tue 17 Aug 08:17 CDT 2021, Daniel Lezcano wrote:
>
>> On 09/08/2021 21:15, Thara Gopinath wrote:
>>> Introduce SCM calls to access/configure limits management hardware(LMH).
>>>
>>> Reviewed-by: Bjorn Andersson <[email protected]>
>>> Signed-off-by: Thara Gopinath <[email protected]>
>>
>> Hi Bjorn, Andy,
>>
>> do you mind if I pick this patch along with patch 2/6 ?
>>
>
> Please do!
Thanks
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
On Mon, 09 Aug 2021 15:16:05 -0400, Thara Gopinath wrote:
> Add dt binding documentation to describe Qualcomm
> Limits Management Hardware node.
>
> Signed-off-by: Thara Gopinath <[email protected]>
> ---
>
> v4->v5:
> - Renam
> v3->v4:
> - Changed dt property qcom,lmh-cpu-id to qcom,lmh-cpu and made it
> a phandle pointing to the cpu node instead of a number as per
> Rob Herring's review comments.
> - Added suffix -millicelsius to all temperature properties as per
> Rob Herring's review comments.
> - Dropped unnecessary #includes in the example as pointed out by Bjorn.
> - Other minor fixes.
>
> .../devicetree/bindings/thermal/qcom-lmh.yaml | 82 +++++++++++++++++++
> 1 file changed, 82 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
>
Reviewed-by: Rob Herring <[email protected]>
On 09-08-21, 15:16, Thara Gopinath wrote:
> Add interrupt support to notify the kernel of h/w initiated frequency
> throttling by LMh. Convey this to scheduler via thermal presssure
> interface.
>
> Signed-off-by: Thara Gopinath <[email protected]>
> ---
>
> v4->v5:
> - Changed throttle_lock from a spinlock to mutex to take potential
> race between LMh de-init sequence and reenabling of
> interrupts/polling after a thermal throttle event.
> - Other cosmetic fixes as pointed out by Viresh.
Applied. Thanks.
--
viresh
Hi Thara,
On 09/08/2021 21:16, Thara Gopinath wrote:
> Driver enabling various pieces of Limits Management Hardware(LMh) for cpu
> cluster0 and cpu cluster1 namely kick starting monitoring of temperature,
> current, battery current violations, enabling reliability algorithm and
> setting up various temperature limits.
>
> The following has been explained in the cover letter. I am including this
> here so that this remains in the commit message as well.
>
> LMh is a hardware infrastructure on some Qualcomm SoCs that can enforce
> temperature and current limits as programmed by software for certain IPs
> like CPU. On many newer LMh is configured by firmware/TZ and no programming
> is needed from the kernel side. But on certain SoCs like sdm845 the
> firmware does not do a complete programming of the h/w. On such soc's
> kernel software has to explicitly set up the temperature limits and turn on
> various monitoring and enforcing algorithms on the hardware.
>
> Tested-by: Steev Klimaszewski <[email protected]> # Lenovo Yoga C630
> Signed-off-by: Thara Gopinath <[email protected]>
Is it possible to have an option to disable/enable the LMh driver at
runtime, for instance with a module parameter ?
> ---
>
> v4->v5:
> - Minor change related to renaming of dt binding property qcom,lmh-cpu
> to cpus as per Rob Herring's review comments.
>
> v3->v4:
> - Minor code re-arrangement and removal of redundant code as per Bjorn's
> review comments
> - Added suppress_bind_attrs to driver as per Bjorn's review comments.
> - Changes to support changes in LMh dt node properties naming and types.
>
> v2->v3:
> - Rearranged enabling of various LMh subfunction and removed returning
> on error in enabling any one subfunction as the different pieces can
> operate and thus be enabled independently.
> - Other minor cosmetic fixes.
>
> v1->v2:
> - Cosmetic and spelling fixes from review comments from Randy Dunlap
> - Added irq_disable to lmh_irq_ops and removed disabling of irq from
> lmh_handle_irq. Now cpufreq explicitly disables irq prior to
> handling it as per Bjorn's suggestion.
> - Rebased to new version of qcom_scm_lmh_dcvsh as changed in patch 1.
> - Removed generic dt compatible string and introduced platform specific one
> as per Bjorn's suggestion.
> - Take arm, low and high temp thresholds for LMh from dt properties instead of
> #defines in the driver as per Daniel's suggestion.
> - Other minor fixes.
>
> drivers/thermal/qcom/Kconfig | 10 ++
> drivers/thermal/qcom/Makefile | 1 +
> drivers/thermal/qcom/lmh.c | 232 ++++++++++++++++++++++++++++++++++
> 3 files changed, 243 insertions(+)
> create mode 100644 drivers/thermal/qcom/lmh.c
>
> diff --git a/drivers/thermal/qcom/Kconfig b/drivers/thermal/qcom/Kconfig
> index 8d5ac2df26dc..7d942f71e532 100644
> --- a/drivers/thermal/qcom/Kconfig
> +++ b/drivers/thermal/qcom/Kconfig
> @@ -31,3 +31,13 @@ config QCOM_SPMI_TEMP_ALARM
> trip points. The temperature reported by the thermal sensor reflects the
> real time die temperature if an ADC is present or an estimate of the
> temperature based upon the over temperature stage value.
> +
> +config QCOM_LMH
> + tristate "Qualcomm Limits Management Hardware"
> + depends on ARCH_QCOM
> + help
> + This enables initialization of Qualcomm limits management
> + hardware(LMh). LMh allows for hardware-enforced mitigation for cpus based on
> + input from temperature and current sensors. On many newer Qualcomm SoCs
> + LMh is configured in the firmware and this feature need not be enabled.
> + However, on certain SoCs like sdm845 LMh has to be configured from kernel.
> diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile
> index 252ea7d9da0b..0fa2512042e7 100644
> --- a/drivers/thermal/qcom/Makefile
> +++ b/drivers/thermal/qcom/Makefile
> @@ -5,3 +5,4 @@ qcom_tsens-y += tsens.o tsens-v2.o tsens-v1.o tsens-v0_1.o \
> tsens-8960.o
> obj-$(CONFIG_QCOM_SPMI_ADC_TM5) += qcom-spmi-adc-tm5.o
> obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o
> +obj-$(CONFIG_QCOM_LMH) += lmh.o
> diff --git a/drivers/thermal/qcom/lmh.c b/drivers/thermal/qcom/lmh.c
> new file mode 100644
> index 000000000000..eafa7526eb8b
> --- /dev/null
> +++ b/drivers/thermal/qcom/lmh.c
> @@ -0,0 +1,232 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +
> +/*
> + * Copyright (C) 2021, Linaro Limited. All rights reserved.
> + */
> +#include <linux/module.h>
> +#include <linux/interrupt.h>
> +#include <linux/irqdomain.h>
> +#include <linux/err.h>
> +#include <linux/platform_device.h>
> +#include <linux/of_platform.h>
> +#include <linux/slab.h>
> +#include <linux/qcom_scm.h>
> +
> +#define LMH_NODE_DCVS 0x44435653
> +#define LMH_CLUSTER0_NODE_ID 0x6370302D
> +#define LMH_CLUSTER1_NODE_ID 0x6370312D
> +
> +#define LMH_SUB_FN_THERMAL 0x54484D4C
> +#define LMH_SUB_FN_CRNT 0x43524E54
> +#define LMH_SUB_FN_REL 0x52454C00
> +#define LMH_SUB_FN_BCL 0x42434C00
> +
> +#define LMH_ALGO_MODE_ENABLE 0x454E424C
> +#define LMH_TH_HI_THRESHOLD 0x48494748
> +#define LMH_TH_LOW_THRESHOLD 0x4C4F5700
> +#define LMH_TH_ARM_THRESHOLD 0x41524D00
> +
> +#define LMH_REG_DCVS_INTR_CLR 0x8
> +
> +struct lmh_hw_data {
> + void __iomem *base;
> + struct irq_domain *domain;
> + int irq;
> +};
> +
> +static irqreturn_t lmh_handle_irq(int hw_irq, void *data)
> +{
> + struct lmh_hw_data *lmh_data = data;
> + int irq = irq_find_mapping(lmh_data->domain, 0);
> +
> + /* Call the cpufreq driver to handle the interrupt */
> + if (irq)
> + generic_handle_irq(irq);
> +
> + return 0;
> +}
> +
> +static void lmh_enable_interrupt(struct irq_data *d)
> +{
> + struct lmh_hw_data *lmh_data = irq_data_get_irq_chip_data(d);
> +
> + /* Clear the existing interrupt */
> + writel(0xff, lmh_data->base + LMH_REG_DCVS_INTR_CLR);
> + enable_irq(lmh_data->irq);
> +}
> +
> +static void lmh_disable_interrupt(struct irq_data *d)
> +{
> + struct lmh_hw_data *lmh_data = irq_data_get_irq_chip_data(d);
> +
> + disable_irq_nosync(lmh_data->irq);
> +}
> +
> +static struct irq_chip lmh_irq_chip = {
> + .name = "lmh",
> + .irq_enable = lmh_enable_interrupt,
> + .irq_disable = lmh_disable_interrupt
> +};
> +
> +static int lmh_irq_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
> +{
> + struct lmh_hw_data *lmh_data = d->host_data;
> +
> + irq_set_chip_and_handler(irq, &lmh_irq_chip, handle_simple_irq);
> + irq_set_chip_data(irq, lmh_data);
> +
> + return 0;
> +}
> +
> +static const struct irq_domain_ops lmh_irq_ops = {
> + .map = lmh_irq_map,
> + .xlate = irq_domain_xlate_onecell,
> +};
> +
> +static int lmh_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + struct device_node *cpu_node;
> + struct lmh_hw_data *lmh_data;
> + int temp_low, temp_high, temp_arm, cpu_id, ret;
> + u32 node_id;
> +
> + lmh_data = devm_kzalloc(dev, sizeof(*lmh_data), GFP_KERNEL);
> + if (!lmh_data)
> + return -ENOMEM;
> +
> + lmh_data->base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(lmh_data->base))
> + return PTR_ERR(lmh_data->base);
> +
> + cpu_node = of_parse_phandle(np, "cpus", 0);
> + if (!cpu_node)
> + return -EINVAL;
> + cpu_id = of_cpu_node_to_id(cpu_node);
> + of_node_put(cpu_node);
> +
> + ret = of_property_read_u32(np, "qcom,lmh-temp-high-millicelsius", &temp_high);
> + if (ret) {
> + dev_err(dev, "missing qcom,lmh-temp-high-millicelsius property\n");
> + return ret;
> + }
> +
> + ret = of_property_read_u32(np, "qcom,lmh-temp-low-millicelsius", &temp_low);
> + if (ret) {
> + dev_err(dev, "missing qcom,lmh-temp-low-millicelsius property\n");
> + return ret;
> + }
> +
> + ret = of_property_read_u32(np, "qcom,lmh-temp-arm-millicelsius", &temp_arm);
> + if (ret) {
> + dev_err(dev, "missing qcom,lmh-temp-arm-millicelsius property\n");
> + return ret;
> + }
> +
> + /*
> + * Only sdm845 has lmh hardware currently enabled from hlos. If this is needed
> + * for other platforms, revisit this to check if the <cpu-id, node-id> should be part
> + * of a dt match table.
> + */
> + if (cpu_id == 0) {
> + node_id = LMH_CLUSTER0_NODE_ID;
> + } else if (cpu_id == 4) {
> + node_id = LMH_CLUSTER1_NODE_ID;
> + } else {
> + dev_err(dev, "Wrong CPU id associated with LMh node\n");
> + return -EINVAL;
> + }
> +
> + if (!qcom_scm_lmh_dcvsh_available())
> + return -EINVAL;
> +
> + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_CRNT, LMH_ALGO_MODE_ENABLE, 1,
> + LMH_NODE_DCVS, node_id, 0);
> + if (ret)
> + dev_err(dev, "Error %d enabling current subfunction\n", ret);
> +
> + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_REL, LMH_ALGO_MODE_ENABLE, 1,
> + LMH_NODE_DCVS, node_id, 0);
> + if (ret)
> + dev_err(dev, "Error %d enabling reliability subfunction\n", ret);
> +
> + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_BCL, LMH_ALGO_MODE_ENABLE, 1,
> + LMH_NODE_DCVS, node_id, 0);
> + if (ret)
> + dev_err(dev, "Error %d enabling BCL subfunction\n", ret);
> +
> + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_ALGO_MODE_ENABLE, 1,
> + LMH_NODE_DCVS, node_id, 0);
> + if (ret) {
> + dev_err(dev, "Error %d enabling thermal subfunction\n", ret);
> + return ret;
> + }
> +
> + ret = qcom_scm_lmh_profile_change(0x1);
> + if (ret) {
> + dev_err(dev, "Error %d changing profile\n", ret);
> + return ret;
> + }
> +
> + /* Set default thermal trips */
> + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_ARM_THRESHOLD, temp_arm,
> + LMH_NODE_DCVS, node_id, 0);
> + if (ret) {
> + dev_err(dev, "Error setting thermal ARM threshold%d\n", ret);
> + return ret;
> + }
> +
> + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_HI_THRESHOLD, temp_high,
> + LMH_NODE_DCVS, node_id, 0);
> + if (ret) {
> + dev_err(dev, "Error setting thermal HI threshold%d\n", ret);
> + return ret;
> + }
> +
> + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_LOW_THRESHOLD, temp_low,
> + LMH_NODE_DCVS, node_id, 0);
> + if (ret) {
> + dev_err(dev, "Error setting thermal ARM threshold%d\n", ret);
> + return ret;
> + }
> +
> + lmh_data->irq = platform_get_irq(pdev, 0);
> + lmh_data->domain = irq_domain_add_linear(np, 1, &lmh_irq_ops, lmh_data);
> + if (!lmh_data->domain) {
> + dev_err(dev, "Error adding irq_domain\n");
> + return -EINVAL;
> + }
> +
> + /* Disable the irq and let cpufreq enable it when ready to handle the interrupt */
> + irq_set_status_flags(lmh_data->irq, IRQ_NOAUTOEN);
> + ret = devm_request_irq(dev, lmh_data->irq, lmh_handle_irq,
> + IRQF_ONESHOT | IRQF_NO_SUSPEND,
> + "lmh-irq", lmh_data);
> + if (ret) {
> + dev_err(dev, "Error %d registering irq %x\n", ret, lmh_data->irq);
> + irq_domain_remove(lmh_data->domain);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static const struct of_device_id lmh_table[] = {
> + { .compatible = "qcom,sdm845-lmh", },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, lmh_table);
> +
> +static struct platform_driver lmh_driver = {
> + .probe = lmh_probe,
> + .driver = {
> + .name = "qcom-lmh",
> + .of_match_table = lmh_table,
> + .suppress_bind_attrs = true,
> + },
> +};
> +module_platform_driver(lmh_driver);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_DESCRIPTION("QCOM LMh driver");
>
--
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On Sat 21 Aug 02:41 PDT 2021, Daniel Lezcano wrote:
>
> Hi Thara,
>
> On 09/08/2021 21:16, Thara Gopinath wrote:
> > Driver enabling various pieces of Limits Management Hardware(LMh) for cpu
> > cluster0 and cpu cluster1 namely kick starting monitoring of temperature,
> > current, battery current violations, enabling reliability algorithm and
> > setting up various temperature limits.
> >
> > The following has been explained in the cover letter. I am including this
> > here so that this remains in the commit message as well.
> >
> > LMh is a hardware infrastructure on some Qualcomm SoCs that can enforce
> > temperature and current limits as programmed by software for certain IPs
> > like CPU. On many newer LMh is configured by firmware/TZ and no programming
> > is needed from the kernel side. But on certain SoCs like sdm845 the
> > firmware does not do a complete programming of the h/w. On such soc's
> > kernel software has to explicitly set up the temperature limits and turn on
> > various monitoring and enforcing algorithms on the hardware.
> >
> > Tested-by: Steev Klimaszewski <[email protected]> # Lenovo Yoga C630
> > Signed-off-by: Thara Gopinath <[email protected]>
>
> Is it possible to have an option to disable/enable the LMh driver at
> runtime, for instance with a module parameter ?
>
Are you referring to being able to disable the hardware throttling, or
the driver's changes to thermal pressure?
I'm not aware of any way to disable the hardware. I do remember that
there was some experiments done (with a hacked up boot chain) early on
and iirc it was concluded that it's not a good idea.
Either way, if there is a way and there is a use for it, we can always
add such parameter incrementally. So I suggest that we merge this as is.
Regards,
Bjorn
> > ---
> >
> > v4->v5:
> > - Minor change related to renaming of dt binding property qcom,lmh-cpu
> > to cpus as per Rob Herring's review comments.
> >
> > v3->v4:
> > - Minor code re-arrangement and removal of redundant code as per Bjorn's
> > review comments
> > - Added suppress_bind_attrs to driver as per Bjorn's review comments.
> > - Changes to support changes in LMh dt node properties naming and types.
> >
> > v2->v3:
> > - Rearranged enabling of various LMh subfunction and removed returning
> > on error in enabling any one subfunction as the different pieces can
> > operate and thus be enabled independently.
> > - Other minor cosmetic fixes.
> >
> > v1->v2:
> > - Cosmetic and spelling fixes from review comments from Randy Dunlap
> > - Added irq_disable to lmh_irq_ops and removed disabling of irq from
> > lmh_handle_irq. Now cpufreq explicitly disables irq prior to
> > handling it as per Bjorn's suggestion.
> > - Rebased to new version of qcom_scm_lmh_dcvsh as changed in patch 1.
> > - Removed generic dt compatible string and introduced platform specific one
> > as per Bjorn's suggestion.
> > - Take arm, low and high temp thresholds for LMh from dt properties instead of
> > #defines in the driver as per Daniel's suggestion.
> > - Other minor fixes.
> >
> > drivers/thermal/qcom/Kconfig | 10 ++
> > drivers/thermal/qcom/Makefile | 1 +
> > drivers/thermal/qcom/lmh.c | 232 ++++++++++++++++++++++++++++++++++
> > 3 files changed, 243 insertions(+)
> > create mode 100644 drivers/thermal/qcom/lmh.c
> >
> > diff --git a/drivers/thermal/qcom/Kconfig b/drivers/thermal/qcom/Kconfig
> > index 8d5ac2df26dc..7d942f71e532 100644
> > --- a/drivers/thermal/qcom/Kconfig
> > +++ b/drivers/thermal/qcom/Kconfig
> > @@ -31,3 +31,13 @@ config QCOM_SPMI_TEMP_ALARM
> > trip points. The temperature reported by the thermal sensor reflects the
> > real time die temperature if an ADC is present or an estimate of the
> > temperature based upon the over temperature stage value.
> > +
> > +config QCOM_LMH
> > + tristate "Qualcomm Limits Management Hardware"
> > + depends on ARCH_QCOM
> > + help
> > + This enables initialization of Qualcomm limits management
> > + hardware(LMh). LMh allows for hardware-enforced mitigation for cpus based on
> > + input from temperature and current sensors. On many newer Qualcomm SoCs
> > + LMh is configured in the firmware and this feature need not be enabled.
> > + However, on certain SoCs like sdm845 LMh has to be configured from kernel.
> > diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile
> > index 252ea7d9da0b..0fa2512042e7 100644
> > --- a/drivers/thermal/qcom/Makefile
> > +++ b/drivers/thermal/qcom/Makefile
> > @@ -5,3 +5,4 @@ qcom_tsens-y += tsens.o tsens-v2.o tsens-v1.o tsens-v0_1.o \
> > tsens-8960.o
> > obj-$(CONFIG_QCOM_SPMI_ADC_TM5) += qcom-spmi-adc-tm5.o
> > obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o
> > +obj-$(CONFIG_QCOM_LMH) += lmh.o
> > diff --git a/drivers/thermal/qcom/lmh.c b/drivers/thermal/qcom/lmh.c
> > new file mode 100644
> > index 000000000000..eafa7526eb8b
> > --- /dev/null
> > +++ b/drivers/thermal/qcom/lmh.c
> > @@ -0,0 +1,232 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +
> > +/*
> > + * Copyright (C) 2021, Linaro Limited. All rights reserved.
> > + */
> > +#include <linux/module.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/irqdomain.h>
> > +#include <linux/err.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/slab.h>
> > +#include <linux/qcom_scm.h>
> > +
> > +#define LMH_NODE_DCVS 0x44435653
> > +#define LMH_CLUSTER0_NODE_ID 0x6370302D
> > +#define LMH_CLUSTER1_NODE_ID 0x6370312D
> > +
> > +#define LMH_SUB_FN_THERMAL 0x54484D4C
> > +#define LMH_SUB_FN_CRNT 0x43524E54
> > +#define LMH_SUB_FN_REL 0x52454C00
> > +#define LMH_SUB_FN_BCL 0x42434C00
> > +
> > +#define LMH_ALGO_MODE_ENABLE 0x454E424C
> > +#define LMH_TH_HI_THRESHOLD 0x48494748
> > +#define LMH_TH_LOW_THRESHOLD 0x4C4F5700
> > +#define LMH_TH_ARM_THRESHOLD 0x41524D00
> > +
> > +#define LMH_REG_DCVS_INTR_CLR 0x8
> > +
> > +struct lmh_hw_data {
> > + void __iomem *base;
> > + struct irq_domain *domain;
> > + int irq;
> > +};
> > +
> > +static irqreturn_t lmh_handle_irq(int hw_irq, void *data)
> > +{
> > + struct lmh_hw_data *lmh_data = data;
> > + int irq = irq_find_mapping(lmh_data->domain, 0);
> > +
> > + /* Call the cpufreq driver to handle the interrupt */
> > + if (irq)
> > + generic_handle_irq(irq);
> > +
> > + return 0;
> > +}
> > +
> > +static void lmh_enable_interrupt(struct irq_data *d)
> > +{
> > + struct lmh_hw_data *lmh_data = irq_data_get_irq_chip_data(d);
> > +
> > + /* Clear the existing interrupt */
> > + writel(0xff, lmh_data->base + LMH_REG_DCVS_INTR_CLR);
> > + enable_irq(lmh_data->irq);
> > +}
> > +
> > +static void lmh_disable_interrupt(struct irq_data *d)
> > +{
> > + struct lmh_hw_data *lmh_data = irq_data_get_irq_chip_data(d);
> > +
> > + disable_irq_nosync(lmh_data->irq);
> > +}
> > +
> > +static struct irq_chip lmh_irq_chip = {
> > + .name = "lmh",
> > + .irq_enable = lmh_enable_interrupt,
> > + .irq_disable = lmh_disable_interrupt
> > +};
> > +
> > +static int lmh_irq_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
> > +{
> > + struct lmh_hw_data *lmh_data = d->host_data;
> > +
> > + irq_set_chip_and_handler(irq, &lmh_irq_chip, handle_simple_irq);
> > + irq_set_chip_data(irq, lmh_data);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct irq_domain_ops lmh_irq_ops = {
> > + .map = lmh_irq_map,
> > + .xlate = irq_domain_xlate_onecell,
> > +};
> > +
> > +static int lmh_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct device_node *np = dev->of_node;
> > + struct device_node *cpu_node;
> > + struct lmh_hw_data *lmh_data;
> > + int temp_low, temp_high, temp_arm, cpu_id, ret;
> > + u32 node_id;
> > +
> > + lmh_data = devm_kzalloc(dev, sizeof(*lmh_data), GFP_KERNEL);
> > + if (!lmh_data)
> > + return -ENOMEM;
> > +
> > + lmh_data->base = devm_platform_ioremap_resource(pdev, 0);
> > + if (IS_ERR(lmh_data->base))
> > + return PTR_ERR(lmh_data->base);
> > +
> > + cpu_node = of_parse_phandle(np, "cpus", 0);
> > + if (!cpu_node)
> > + return -EINVAL;
> > + cpu_id = of_cpu_node_to_id(cpu_node);
> > + of_node_put(cpu_node);
> > +
> > + ret = of_property_read_u32(np, "qcom,lmh-temp-high-millicelsius", &temp_high);
> > + if (ret) {
> > + dev_err(dev, "missing qcom,lmh-temp-high-millicelsius property\n");
> > + return ret;
> > + }
> > +
> > + ret = of_property_read_u32(np, "qcom,lmh-temp-low-millicelsius", &temp_low);
> > + if (ret) {
> > + dev_err(dev, "missing qcom,lmh-temp-low-millicelsius property\n");
> > + return ret;
> > + }
> > +
> > + ret = of_property_read_u32(np, "qcom,lmh-temp-arm-millicelsius", &temp_arm);
> > + if (ret) {
> > + dev_err(dev, "missing qcom,lmh-temp-arm-millicelsius property\n");
> > + return ret;
> > + }
> > +
> > + /*
> > + * Only sdm845 has lmh hardware currently enabled from hlos. If this is needed
> > + * for other platforms, revisit this to check if the <cpu-id, node-id> should be part
> > + * of a dt match table.
> > + */
> > + if (cpu_id == 0) {
> > + node_id = LMH_CLUSTER0_NODE_ID;
> > + } else if (cpu_id == 4) {
> > + node_id = LMH_CLUSTER1_NODE_ID;
> > + } else {
> > + dev_err(dev, "Wrong CPU id associated with LMh node\n");
> > + return -EINVAL;
> > + }
> > +
> > + if (!qcom_scm_lmh_dcvsh_available())
> > + return -EINVAL;
> > +
> > + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_CRNT, LMH_ALGO_MODE_ENABLE, 1,
> > + LMH_NODE_DCVS, node_id, 0);
> > + if (ret)
> > + dev_err(dev, "Error %d enabling current subfunction\n", ret);
> > +
> > + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_REL, LMH_ALGO_MODE_ENABLE, 1,
> > + LMH_NODE_DCVS, node_id, 0);
> > + if (ret)
> > + dev_err(dev, "Error %d enabling reliability subfunction\n", ret);
> > +
> > + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_BCL, LMH_ALGO_MODE_ENABLE, 1,
> > + LMH_NODE_DCVS, node_id, 0);
> > + if (ret)
> > + dev_err(dev, "Error %d enabling BCL subfunction\n", ret);
> > +
> > + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_ALGO_MODE_ENABLE, 1,
> > + LMH_NODE_DCVS, node_id, 0);
> > + if (ret) {
> > + dev_err(dev, "Error %d enabling thermal subfunction\n", ret);
> > + return ret;
> > + }
> > +
> > + ret = qcom_scm_lmh_profile_change(0x1);
> > + if (ret) {
> > + dev_err(dev, "Error %d changing profile\n", ret);
> > + return ret;
> > + }
> > +
> > + /* Set default thermal trips */
> > + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_ARM_THRESHOLD, temp_arm,
> > + LMH_NODE_DCVS, node_id, 0);
> > + if (ret) {
> > + dev_err(dev, "Error setting thermal ARM threshold%d\n", ret);
> > + return ret;
> > + }
> > +
> > + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_HI_THRESHOLD, temp_high,
> > + LMH_NODE_DCVS, node_id, 0);
> > + if (ret) {
> > + dev_err(dev, "Error setting thermal HI threshold%d\n", ret);
> > + return ret;
> > + }
> > +
> > + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_LOW_THRESHOLD, temp_low,
> > + LMH_NODE_DCVS, node_id, 0);
> > + if (ret) {
> > + dev_err(dev, "Error setting thermal ARM threshold%d\n", ret);
> > + return ret;
> > + }
> > +
> > + lmh_data->irq = platform_get_irq(pdev, 0);
> > + lmh_data->domain = irq_domain_add_linear(np, 1, &lmh_irq_ops, lmh_data);
> > + if (!lmh_data->domain) {
> > + dev_err(dev, "Error adding irq_domain\n");
> > + return -EINVAL;
> > + }
> > +
> > + /* Disable the irq and let cpufreq enable it when ready to handle the interrupt */
> > + irq_set_status_flags(lmh_data->irq, IRQ_NOAUTOEN);
> > + ret = devm_request_irq(dev, lmh_data->irq, lmh_handle_irq,
> > + IRQF_ONESHOT | IRQF_NO_SUSPEND,
> > + "lmh-irq", lmh_data);
> > + if (ret) {
> > + dev_err(dev, "Error %d registering irq %x\n", ret, lmh_data->irq);
> > + irq_domain_remove(lmh_data->domain);
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id lmh_table[] = {
> > + { .compatible = "qcom,sdm845-lmh", },
> > + {}
> > +};
> > +MODULE_DEVICE_TABLE(of, lmh_table);
> > +
> > +static struct platform_driver lmh_driver = {
> > + .probe = lmh_probe,
> > + .driver = {
> > + .name = "qcom-lmh",
> > + .of_match_table = lmh_table,
> > + .suppress_bind_attrs = true,
> > + },
> > +};
> > +module_platform_driver(lmh_driver);
> > +
> > +MODULE_LICENSE("GPL v2");
> > +MODULE_DESCRIPTION("QCOM LMh driver");
> >
>
>
> --
> <http://www.linaro.org/> Linaro.org ??? Open source software for ARM SoCs
>
> Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
> <http://twitter.com/#!/linaroorg> Twitter |
> <http://www.linaro.org/linaro-blog/> Blog
Hi Bjorn,
On 23/08/2021 17:05, Bjorn Andersson wrote:
> On Sat 21 Aug 02:41 PDT 2021, Daniel Lezcano wrote:
>
>>
>> Hi Thara,
>>
>> On 09/08/2021 21:16, Thara Gopinath wrote:
>>> Driver enabling various pieces of Limits Management Hardware(LMh) for cpu
>>> cluster0 and cpu cluster1 namely kick starting monitoring of temperature,
>>> current, battery current violations, enabling reliability algorithm and
>>> setting up various temperature limits.
>>>
>>> The following has been explained in the cover letter. I am including this
>>> here so that this remains in the commit message as well.
>>>
>>> LMh is a hardware infrastructure on some Qualcomm SoCs that can enforce
>>> temperature and current limits as programmed by software for certain IPs
>>> like CPU. On many newer LMh is configured by firmware/TZ and no programming
>>> is needed from the kernel side. But on certain SoCs like sdm845 the
>>> firmware does not do a complete programming of the h/w. On such soc's
>>> kernel software has to explicitly set up the temperature limits and turn on
>>> various monitoring and enforcing algorithms on the hardware.
>>>
>>> Tested-by: Steev Klimaszewski <[email protected]> # Lenovo Yoga C630
>>> Signed-off-by: Thara Gopinath <[email protected]>
>>
>> Is it possible to have an option to disable/enable the LMh driver at
>> runtime, for instance with a module parameter ?
>>
>
> Are you referring to being able to disable the hardware throttling, or
> the driver's changes to thermal pressure?
The former.
> I'm not aware of any way to disable the hardware. I do remember that
> there was some experiments done (with a hacked up boot chain) early on
> and iirc it was concluded that it's not a good idea.
My objective was to test the board with the thermal framework handling
the mitigation instead of the hardware.
I guess I can set the hardware temperature higher than the thermal zone
temperature.
On which sensor the lmh does refer to ? The cluster one ?
(by the way the thermal zone temperatures per core are lower by 5°C than
the hardware mitigation ? is it done on purpose ?)
> Either way, if there is a way and there is a use for it, we can always
> add such parameter incrementally. So I suggest that we merge this as is.
Yes, that was for my information. It is already merged.
Thanks
-- Daniel
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
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<http://www.linaro.org/linaro-blog/> Blog
On 8/23/21 11:57 AM, Daniel Lezcano wrote:
>
> Hi Bjorn,
>
> On 23/08/2021 17:05, Bjorn Andersson wrote:
>> On Sat 21 Aug 02:41 PDT 2021, Daniel Lezcano wrote:
>>
>>>
>>> Hi Thara,
>>>
>>> On 09/08/2021 21:16, Thara Gopinath wrote:
>>>> Driver enabling various pieces of Limits Management Hardware(LMh) for cpu
>>>> cluster0 and cpu cluster1 namely kick starting monitoring of temperature,
>>>> current, battery current violations, enabling reliability algorithm and
>>>> setting up various temperature limits.
>>>>
>>>> The following has been explained in the cover letter. I am including this
>>>> here so that this remains in the commit message as well.
>>>>
>>>> LMh is a hardware infrastructure on some Qualcomm SoCs that can enforce
>>>> temperature and current limits as programmed by software for certain IPs
>>>> like CPU. On many newer LMh is configured by firmware/TZ and no programming
>>>> is needed from the kernel side. But on certain SoCs like sdm845 the
>>>> firmware does not do a complete programming of the h/w. On such soc's
>>>> kernel software has to explicitly set up the temperature limits and turn on
>>>> various monitoring and enforcing algorithms on the hardware.
>>>>
>>>> Tested-by: Steev Klimaszewski <[email protected]> # Lenovo Yoga C630
>>>> Signed-off-by: Thara Gopinath <[email protected]>
>>>
>>> Is it possible to have an option to disable/enable the LMh driver at
>>> runtime, for instance with a module parameter ?
>>>
>>
>> Are you referring to being able to disable the hardware throttling, or
>> the driver's changes to thermal pressure?
>
> The former.
Hi Daniel,
It is not recommended to turn off LMh once enabled. From h/w point of
view, it can be done for debug purposes but it is not to be implemented
as a feature.
>
>> I'm not aware of any way to disable the hardware. I do remember that
>> there was some experiments done (with a hacked up boot chain) early on
>> and iirc it was concluded that it's not a good idea.
>
> My objective was to test the board with the thermal framework handling
> the mitigation instead of the hardware.
>
> I guess I can set the hardware temperature higher than the thermal zone
> temperature.
Right. Also remember that patch 5 in this series removes the cooling
devices for the cpu thermal zones. So if you are testing this you will
have to add them back.
>
> On which sensor the lmh does refer to ? The cluster one ?
>
> (by the way the thermal zone temperatures per core are lower by 5°C than
> the hardware mitigation ? is it done on purpose ?)
So IIUC, it refers to tsens for individual cpus and collates the input.
But the documentation is not clear on this one. I took the mitigation
temperature from downstream code. Yes I did realize that the thermal
zone trip1 temp is 90 degree where as the LMh mitigation point is 95
degree. My thinking is this is because the h/w mitigation can happen
faster than s/w and hence the 5 degree bump up in temperature.
>
>> Either way, if there is a way and there is a use for it, we can always
>> add such parameter incrementally. So I suggest that we merge this as is.
>
> Yes, that was for my information. It is already merged.
Thank you very much
>
> Thanks
>
> -- Daniel
>
--
Warm Regards
Thara (She/Her/Hers)