For register names that are unsupported by the assembler or the ones
without architectural names, add the macros write_sysreg_s and
read_sysreg_s to support them.
The functionality is derived from kvm-unit-tests and kernel's
arch/arm64/include/asm/sysreg.h.
Signed-off-by: Raghavendra Rao Ananta <[email protected]>
---
.../selftests/kvm/include/aarch64/processor.h | 61 +++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/tools/testing/selftests/kvm/include/aarch64/processor.h b/tools/testing/selftests/kvm/include/aarch64/processor.h
index 3cbaf5c1e26b..082cc97ad8d3 100644
--- a/tools/testing/selftests/kvm/include/aarch64/processor.h
+++ b/tools/testing/selftests/kvm/include/aarch64/processor.h
@@ -118,6 +118,67 @@ void vm_install_exception_handler(struct kvm_vm *vm,
void vm_install_sync_handler(struct kvm_vm *vm,
int vector, int ec, handler_fn handler);
+/*
+ * ARMv8 ARM reserves the following encoding for system registers:
+ * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
+ * C5.2, version:ARM DDI 0487A.f)
+ * [20-19] : Op0
+ * [18-16] : Op1
+ * [15-12] : CRn
+ * [11-8] : CRm
+ * [7-5] : Op2
+ */
+#define Op0_shift 19
+#define Op0_mask 0x3
+#define Op1_shift 16
+#define Op1_mask 0x7
+#define CRn_shift 12
+#define CRn_mask 0xf
+#define CRm_shift 8
+#define CRm_mask 0xf
+#define Op2_shift 5
+#define Op2_mask 0x7
+
+/*
+ * When accessed from guests, the ARM64_SYS_REG() doesn't work since it
+ * generates a different encoding for additional KVM processing, and is
+ * only suitable for userspace to access the register via ioctls.
+ * Hence, define a 'pure' sys_reg() here to generate the encodings as per spec.
+ */
+#define sys_reg(op0, op1, crn, crm, op2) \
+ (((op0) << Op0_shift) | ((op1) << Op1_shift) | \
+ ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
+ ((op2) << Op2_shift))
+
+asm(
+" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
+" .equ .L__reg_num_x\\num, \\num\n"
+" .endr\n"
+" .equ .L__reg_num_xzr, 31\n"
+"\n"
+" .macro mrs_s, rt, sreg\n"
+" .inst 0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n"
+" .endm\n"
+"\n"
+" .macro msr_s, sreg, rt\n"
+" .inst 0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n"
+" .endm\n"
+);
+
+/*
+ * read_sysreg_s() and write_sysreg_s()'s 'reg' has to be encoded via sys_reg()
+ */
+#define read_sysreg_s(reg) ({ \
+ u64 __val; \
+ asm volatile("mrs_s %0, "__stringify(reg) : "=r" (__val)); \
+ __val; \
+})
+
+#define write_sysreg_s(reg, val) do { \
+ u64 __val = (u64)val; \
+ asm volatile("msr_s "__stringify(reg) ", %x0" : : "rZ" (__val));\
+} while (0)
+
#define write_sysreg(reg, val) \
({ \
u64 __val = (u64)(val); \
--
2.33.0.153.gba50c8fa24-goog
On Wed, Sep 01, 2021 at 09:14:02PM +0000, Raghavendra Rao Ananta wrote:
> For register names that are unsupported by the assembler or the ones
> without architectural names, add the macros write_sysreg_s and
> read_sysreg_s to support them.
>
> The functionality is derived from kvm-unit-tests and kernel's
> arch/arm64/include/asm/sysreg.h.
>
> Signed-off-by: Raghavendra Rao Ananta <[email protected]>
Would it be possible to just include <asm/sysreg.h>? See
tools/arch/arm64/include/asm/sysreg.h
> ---
> .../selftests/kvm/include/aarch64/processor.h | 61 +++++++++++++++++++
> 1 file changed, 61 insertions(+)
>
> diff --git a/tools/testing/selftests/kvm/include/aarch64/processor.h b/tools/testing/selftests/kvm/include/aarch64/processor.h
> index 3cbaf5c1e26b..082cc97ad8d3 100644
> --- a/tools/testing/selftests/kvm/include/aarch64/processor.h
> +++ b/tools/testing/selftests/kvm/include/aarch64/processor.h
> @@ -118,6 +118,67 @@ void vm_install_exception_handler(struct kvm_vm *vm,
> void vm_install_sync_handler(struct kvm_vm *vm,
> int vector, int ec, handler_fn handler);
>
> +/*
> + * ARMv8 ARM reserves the following encoding for system registers:
> + * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
> + * C5.2, version:ARM DDI 0487A.f)
> + * [20-19] : Op0
> + * [18-16] : Op1
> + * [15-12] : CRn
> + * [11-8] : CRm
> + * [7-5] : Op2
> + */
> +#define Op0_shift 19
> +#define Op0_mask 0x3
> +#define Op1_shift 16
> +#define Op1_mask 0x7
> +#define CRn_shift 12
> +#define CRn_mask 0xf
> +#define CRm_shift 8
> +#define CRm_mask 0xf
> +#define Op2_shift 5
> +#define Op2_mask 0x7
> +
> +/*
> + * When accessed from guests, the ARM64_SYS_REG() doesn't work since it
> + * generates a different encoding for additional KVM processing, and is
> + * only suitable for userspace to access the register via ioctls.
> + * Hence, define a 'pure' sys_reg() here to generate the encodings as per spec.
> + */
> +#define sys_reg(op0, op1, crn, crm, op2) \
> + (((op0) << Op0_shift) | ((op1) << Op1_shift) | \
> + ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
> + ((op2) << Op2_shift))
> +
> +asm(
> +" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
> +" .equ .L__reg_num_x\\num, \\num\n"
> +" .endr\n"
> +" .equ .L__reg_num_xzr, 31\n"
> +"\n"
> +" .macro mrs_s, rt, sreg\n"
> +" .inst 0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n"
> +" .endm\n"
> +"\n"
> +" .macro msr_s, sreg, rt\n"
> +" .inst 0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n"
> +" .endm\n"
> +);
> +
> +/*
> + * read_sysreg_s() and write_sysreg_s()'s 'reg' has to be encoded via sys_reg()
> + */
> +#define read_sysreg_s(reg) ({ \
> + u64 __val; \
> + asm volatile("mrs_s %0, "__stringify(reg) : "=r" (__val)); \
> + __val; \
> +})
> +
> +#define write_sysreg_s(reg, val) do { \
> + u64 __val = (u64)val; \
> + asm volatile("msr_s "__stringify(reg) ", %x0" : : "rZ" (__val));\
> +} while (0)
> +
> #define write_sysreg(reg, val) \
> ({ \
> u64 __val = (u64)(val); \
> --
> 2.33.0.153.gba50c8fa24-goog
>
On Wed, Sep 01, 2021 at 03:48:40PM -0700, Raghavendra Rao Ananta wrote:
> On Wed, Sep 1, 2021 at 3:08 PM Oliver Upton <[email protected]> wrote:
> >
> > On Wed, Sep 01, 2021 at 09:28:28PM +0000, Oliver Upton wrote:
> > > On Wed, Sep 01, 2021 at 09:14:02PM +0000, Raghavendra Rao Ananta wrote:
> > > > For register names that are unsupported by the assembler or the ones
> > > > without architectural names, add the macros write_sysreg_s and
> > > > read_sysreg_s to support them.
> > > >
> > > > The functionality is derived from kvm-unit-tests and kernel's
> > > > arch/arm64/include/asm/sysreg.h.
> > > >
> > > > Signed-off-by: Raghavendra Rao Ananta <[email protected]>
> > >
> > > Would it be possible to just include <asm/sysreg.h>? See
> > > tools/arch/arm64/include/asm/sysreg.h
> >
> > Geez, sorry for the noise. I mistakenly searched from the root of my
> > repository, not the tools/ directory.
> >
> No worries :)
>
> > In any case, you could perhaps just drop the kernel header there just to
> > use the exact same source for kernel and selftest.
> >
> You mean just copy/paste the entire header? There's a lot of stuff in
> there which we
> don't need it (yet).
Right. It's mostly register definitions, which I don't think is too high
of an overhead. Don't know where others stand, but I would prefer a
header that is equivalent between kernel & selftests over a concise
header.
--
Thanks,
Oliver
> > Thanks,
> > Oliver
> >
> > > > ---
> > > > .../selftests/kvm/include/aarch64/processor.h | 61 +++++++++++++++++++
> > > > 1 file changed, 61 insertions(+)
> > > >
> > > > diff --git a/tools/testing/selftests/kvm/include/aarch64/processor.h b/tools/testing/selftests/kvm/include/aarch64/processor.h
> > > > index 3cbaf5c1e26b..082cc97ad8d3 100644
> > > > --- a/tools/testing/selftests/kvm/include/aarch64/processor.h
> > > > +++ b/tools/testing/selftests/kvm/include/aarch64/processor.h
> > > > @@ -118,6 +118,67 @@ void vm_install_exception_handler(struct kvm_vm *vm,
> > > > void vm_install_sync_handler(struct kvm_vm *vm,
> > > > int vector, int ec, handler_fn handler);
> > > >
> > > > +/*
> > > > + * ARMv8 ARM reserves the following encoding for system registers:
> > > > + * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
> > > > + * C5.2, version:ARM DDI 0487A.f)
> > > > + * [20-19] : Op0
> > > > + * [18-16] : Op1
> > > > + * [15-12] : CRn
> > > > + * [11-8] : CRm
> > > > + * [7-5] : Op2
> > > > + */
> > > > +#define Op0_shift 19
> > > > +#define Op0_mask 0x3
> > > > +#define Op1_shift 16
> > > > +#define Op1_mask 0x7
> > > > +#define CRn_shift 12
> > > > +#define CRn_mask 0xf
> > > > +#define CRm_shift 8
> > > > +#define CRm_mask 0xf
> > > > +#define Op2_shift 5
> > > > +#define Op2_mask 0x7
> > > > +
> > > > +/*
> > > > + * When accessed from guests, the ARM64_SYS_REG() doesn't work since it
> > > > + * generates a different encoding for additional KVM processing, and is
> > > > + * only suitable for userspace to access the register via ioctls.
> > > > + * Hence, define a 'pure' sys_reg() here to generate the encodings as per spec.
> > > > + */
> > > > +#define sys_reg(op0, op1, crn, crm, op2) \
> > > > + (((op0) << Op0_shift) | ((op1) << Op1_shift) | \
> > > > + ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
> > > > + ((op2) << Op2_shift))
> > > > +
> > > > +asm(
> > > > +" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
> > > > +" .equ .L__reg_num_x\\num, \\num\n"
> > > > +" .endr\n"
> > > > +" .equ .L__reg_num_xzr, 31\n"
> > > > +"\n"
> > > > +" .macro mrs_s, rt, sreg\n"
> > > > +" .inst 0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n"
> > > > +" .endm\n"
> > > > +"\n"
> > > > +" .macro msr_s, sreg, rt\n"
> > > > +" .inst 0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n"
> > > > +" .endm\n"
> > > > +);
> > > > +
> > > > +/*
> > > > + * read_sysreg_s() and write_sysreg_s()'s 'reg' has to be encoded via sys_reg()
> > > > + */
> > > > +#define read_sysreg_s(reg) ({ \
> > > > + u64 __val; \
> > > > + asm volatile("mrs_s %0, "__stringify(reg) : "=r" (__val)); \
> > > > + __val; \
> > > > +})
> > > > +
> > > > +#define write_sysreg_s(reg, val) do { \
> > > > + u64 __val = (u64)val; \
> > > > + asm volatile("msr_s "__stringify(reg) ", %x0" : : "rZ" (__val));\
> > > > +} while (0)
> > > > +
> > > > #define write_sysreg(reg, val) \
> > > > ({ \
> > > > u64 __val = (u64)(val); \
> > > > --
> > > > 2.33.0.153.gba50c8fa24-goog
> > > >
On Wed, Sep 01, 2021 at 09:28:28PM +0000, Oliver Upton wrote:
> On Wed, Sep 01, 2021 at 09:14:02PM +0000, Raghavendra Rao Ananta wrote:
> > For register names that are unsupported by the assembler or the ones
> > without architectural names, add the macros write_sysreg_s and
> > read_sysreg_s to support them.
> >
> > The functionality is derived from kvm-unit-tests and kernel's
> > arch/arm64/include/asm/sysreg.h.
> >
> > Signed-off-by: Raghavendra Rao Ananta <[email protected]>
>
> Would it be possible to just include <asm/sysreg.h>? See
> tools/arch/arm64/include/asm/sysreg.h
Geez, sorry for the noise. I mistakenly searched from the root of my
repository, not the tools/ directory.
In any case, you could perhaps just drop the kernel header there just to
use the exact same source for kernel and selftest.
Thanks,
Oliver
> > ---
> > .../selftests/kvm/include/aarch64/processor.h | 61 +++++++++++++++++++
> > 1 file changed, 61 insertions(+)
> >
> > diff --git a/tools/testing/selftests/kvm/include/aarch64/processor.h b/tools/testing/selftests/kvm/include/aarch64/processor.h
> > index 3cbaf5c1e26b..082cc97ad8d3 100644
> > --- a/tools/testing/selftests/kvm/include/aarch64/processor.h
> > +++ b/tools/testing/selftests/kvm/include/aarch64/processor.h
> > @@ -118,6 +118,67 @@ void vm_install_exception_handler(struct kvm_vm *vm,
> > void vm_install_sync_handler(struct kvm_vm *vm,
> > int vector, int ec, handler_fn handler);
> >
> > +/*
> > + * ARMv8 ARM reserves the following encoding for system registers:
> > + * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
> > + * C5.2, version:ARM DDI 0487A.f)
> > + * [20-19] : Op0
> > + * [18-16] : Op1
> > + * [15-12] : CRn
> > + * [11-8] : CRm
> > + * [7-5] : Op2
> > + */
> > +#define Op0_shift 19
> > +#define Op0_mask 0x3
> > +#define Op1_shift 16
> > +#define Op1_mask 0x7
> > +#define CRn_shift 12
> > +#define CRn_mask 0xf
> > +#define CRm_shift 8
> > +#define CRm_mask 0xf
> > +#define Op2_shift 5
> > +#define Op2_mask 0x7
> > +
> > +/*
> > + * When accessed from guests, the ARM64_SYS_REG() doesn't work since it
> > + * generates a different encoding for additional KVM processing, and is
> > + * only suitable for userspace to access the register via ioctls.
> > + * Hence, define a 'pure' sys_reg() here to generate the encodings as per spec.
> > + */
> > +#define sys_reg(op0, op1, crn, crm, op2) \
> > + (((op0) << Op0_shift) | ((op1) << Op1_shift) | \
> > + ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
> > + ((op2) << Op2_shift))
> > +
> > +asm(
> > +" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
> > +" .equ .L__reg_num_x\\num, \\num\n"
> > +" .endr\n"
> > +" .equ .L__reg_num_xzr, 31\n"
> > +"\n"
> > +" .macro mrs_s, rt, sreg\n"
> > +" .inst 0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n"
> > +" .endm\n"
> > +"\n"
> > +" .macro msr_s, sreg, rt\n"
> > +" .inst 0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n"
> > +" .endm\n"
> > +);
> > +
> > +/*
> > + * read_sysreg_s() and write_sysreg_s()'s 'reg' has to be encoded via sys_reg()
> > + */
> > +#define read_sysreg_s(reg) ({ \
> > + u64 __val; \
> > + asm volatile("mrs_s %0, "__stringify(reg) : "=r" (__val)); \
> > + __val; \
> > +})
> > +
> > +#define write_sysreg_s(reg, val) do { \
> > + u64 __val = (u64)val; \
> > + asm volatile("msr_s "__stringify(reg) ", %x0" : : "rZ" (__val));\
> > +} while (0)
> > +
> > #define write_sysreg(reg, val) \
> > ({ \
> > u64 __val = (u64)(val); \
> > --
> > 2.33.0.153.gba50c8fa24-goog
> >
On Wed, Sep 1, 2021 at 3:08 PM Oliver Upton <[email protected]> wrote:
>
> On Wed, Sep 01, 2021 at 09:28:28PM +0000, Oliver Upton wrote:
> > On Wed, Sep 01, 2021 at 09:14:02PM +0000, Raghavendra Rao Ananta wrote:
> > > For register names that are unsupported by the assembler or the ones
> > > without architectural names, add the macros write_sysreg_s and
> > > read_sysreg_s to support them.
> > >
> > > The functionality is derived from kvm-unit-tests and kernel's
> > > arch/arm64/include/asm/sysreg.h.
> > >
> > > Signed-off-by: Raghavendra Rao Ananta <[email protected]>
> >
> > Would it be possible to just include <asm/sysreg.h>? See
> > tools/arch/arm64/include/asm/sysreg.h
>
> Geez, sorry for the noise. I mistakenly searched from the root of my
> repository, not the tools/ directory.
>
No worries :)
> In any case, you could perhaps just drop the kernel header there just to
> use the exact same source for kernel and selftest.
>
You mean just copy/paste the entire header? There's a lot of stuff in
there which we
don't need it (yet).
Regards,
Raghavendra
> Thanks,
> Oliver
>
> > > ---
> > > .../selftests/kvm/include/aarch64/processor.h | 61 +++++++++++++++++++
> > > 1 file changed, 61 insertions(+)
> > >
> > > diff --git a/tools/testing/selftests/kvm/include/aarch64/processor.h b/tools/testing/selftests/kvm/include/aarch64/processor.h
> > > index 3cbaf5c1e26b..082cc97ad8d3 100644
> > > --- a/tools/testing/selftests/kvm/include/aarch64/processor.h
> > > +++ b/tools/testing/selftests/kvm/include/aarch64/processor.h
> > > @@ -118,6 +118,67 @@ void vm_install_exception_handler(struct kvm_vm *vm,
> > > void vm_install_sync_handler(struct kvm_vm *vm,
> > > int vector, int ec, handler_fn handler);
> > >
> > > +/*
> > > + * ARMv8 ARM reserves the following encoding for system registers:
> > > + * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
> > > + * C5.2, version:ARM DDI 0487A.f)
> > > + * [20-19] : Op0
> > > + * [18-16] : Op1
> > > + * [15-12] : CRn
> > > + * [11-8] : CRm
> > > + * [7-5] : Op2
> > > + */
> > > +#define Op0_shift 19
> > > +#define Op0_mask 0x3
> > > +#define Op1_shift 16
> > > +#define Op1_mask 0x7
> > > +#define CRn_shift 12
> > > +#define CRn_mask 0xf
> > > +#define CRm_shift 8
> > > +#define CRm_mask 0xf
> > > +#define Op2_shift 5
> > > +#define Op2_mask 0x7
> > > +
> > > +/*
> > > + * When accessed from guests, the ARM64_SYS_REG() doesn't work since it
> > > + * generates a different encoding for additional KVM processing, and is
> > > + * only suitable for userspace to access the register via ioctls.
> > > + * Hence, define a 'pure' sys_reg() here to generate the encodings as per spec.
> > > + */
> > > +#define sys_reg(op0, op1, crn, crm, op2) \
> > > + (((op0) << Op0_shift) | ((op1) << Op1_shift) | \
> > > + ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
> > > + ((op2) << Op2_shift))
> > > +
> > > +asm(
> > > +" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
> > > +" .equ .L__reg_num_x\\num, \\num\n"
> > > +" .endr\n"
> > > +" .equ .L__reg_num_xzr, 31\n"
> > > +"\n"
> > > +" .macro mrs_s, rt, sreg\n"
> > > +" .inst 0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n"
> > > +" .endm\n"
> > > +"\n"
> > > +" .macro msr_s, sreg, rt\n"
> > > +" .inst 0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n"
> > > +" .endm\n"
> > > +);
> > > +
> > > +/*
> > > + * read_sysreg_s() and write_sysreg_s()'s 'reg' has to be encoded via sys_reg()
> > > + */
> > > +#define read_sysreg_s(reg) ({ \
> > > + u64 __val; \
> > > + asm volatile("mrs_s %0, "__stringify(reg) : "=r" (__val)); \
> > > + __val; \
> > > +})
> > > +
> > > +#define write_sysreg_s(reg, val) do { \
> > > + u64 __val = (u64)val; \
> > > + asm volatile("msr_s "__stringify(reg) ", %x0" : : "rZ" (__val));\
> > > +} while (0)
> > > +
> > > #define write_sysreg(reg, val) \
> > > ({ \
> > > u64 __val = (u64)(val); \
> > > --
> > > 2.33.0.153.gba50c8fa24-goog
> > >
On Wed, Sep 01, 2021 at 09:14:02PM +0000, Raghavendra Rao Ananta wrote:
> For register names that are unsupported by the assembler or the ones
> without architectural names, add the macros write_sysreg_s and
> read_sysreg_s to support them.
>
> The functionality is derived from kvm-unit-tests and kernel's
> arch/arm64/include/asm/sysreg.h.
>
> Signed-off-by: Raghavendra Rao Ananta <[email protected]>
> ---
> .../selftests/kvm/include/aarch64/processor.h | 61 +++++++++++++++++++
> 1 file changed, 61 insertions(+)
If we don't replace with an import of arch/arm64/include/asm/sysreg.h
Reviewed-by: Andrew Jones <[email protected]>
On Thu, Sep 2, 2021 at 5:31 AM Andrew Jones <[email protected]> wrote:
>
> On Wed, Sep 01, 2021 at 11:06:10PM +0000, Oliver Upton wrote:
> > On Wed, Sep 01, 2021 at 03:48:40PM -0700, Raghavendra Rao Ananta wrote:
> > > On Wed, Sep 1, 2021 at 3:08 PM Oliver Upton <[email protected]> wrote:
> > > >
> > > > On Wed, Sep 01, 2021 at 09:28:28PM +0000, Oliver Upton wrote:
> > > > > On Wed, Sep 01, 2021 at 09:14:02PM +0000, Raghavendra Rao Ananta wrote:
> > > > > > For register names that are unsupported by the assembler or the ones
> > > > > > without architectural names, add the macros write_sysreg_s and
> > > > > > read_sysreg_s to support them.
> > > > > >
> > > > > > The functionality is derived from kvm-unit-tests and kernel's
> > > > > > arch/arm64/include/asm/sysreg.h.
> > > > > >
> > > > > > Signed-off-by: Raghavendra Rao Ananta <[email protected]>
> > > > >
> > > > > Would it be possible to just include <asm/sysreg.h>? See
> > > > > tools/arch/arm64/include/asm/sysreg.h
> > > >
> > > > Geez, sorry for the noise. I mistakenly searched from the root of my
> > > > repository, not the tools/ directory.
> > > >
> > > No worries :)
> > >
> > > > In any case, you could perhaps just drop the kernel header there just to
> > > > use the exact same source for kernel and selftest.
> > > >
> > > You mean just copy/paste the entire header? There's a lot of stuff in
> > > there which we
> > > don't need it (yet).
> >
> > Right. It's mostly register definitions, which I don't think is too high
> > of an overhead. Don't know where others stand, but I would prefer a
> > header that is equivalent between kernel & selftests over a concise
> > header.
> >
>
> Until now we haven't needed the sys_reg(...) type of definitions for
> sysregs in selftests. In case we did, we defined the registers we
> needed for get/set_one_reg by their parts, e.g.
>
> #define ID_AA64DFR0_EL1 3, 0, 0, 5, 0
>
> allowing us to choose how we use them, ARM64_SYS_REG(...) vs.
> sys_reg(...).
>
> Bringing over sysreg.h is probably a good idea though. If we do, then
> I'd suggest we define a new macro that allows us to convert a SYS_*
> register definition from sysreg.h into an ARM64_SYS_REG definition
> for get/set_one_reg in order to avoid redundant definitions.
>
I agree. Will look into it, and plan to pull the original sysreg.h
into selftests.
Regards,
Raghavendra
> Thanks,
> drew
>
On Wed, Sep 01, 2021 at 11:06:10PM +0000, Oliver Upton wrote:
> On Wed, Sep 01, 2021 at 03:48:40PM -0700, Raghavendra Rao Ananta wrote:
> > On Wed, Sep 1, 2021 at 3:08 PM Oliver Upton <[email protected]> wrote:
> > >
> > > On Wed, Sep 01, 2021 at 09:28:28PM +0000, Oliver Upton wrote:
> > > > On Wed, Sep 01, 2021 at 09:14:02PM +0000, Raghavendra Rao Ananta wrote:
> > > > > For register names that are unsupported by the assembler or the ones
> > > > > without architectural names, add the macros write_sysreg_s and
> > > > > read_sysreg_s to support them.
> > > > >
> > > > > The functionality is derived from kvm-unit-tests and kernel's
> > > > > arch/arm64/include/asm/sysreg.h.
> > > > >
> > > > > Signed-off-by: Raghavendra Rao Ananta <[email protected]>
> > > >
> > > > Would it be possible to just include <asm/sysreg.h>? See
> > > > tools/arch/arm64/include/asm/sysreg.h
> > >
> > > Geez, sorry for the noise. I mistakenly searched from the root of my
> > > repository, not the tools/ directory.
> > >
> > No worries :)
> >
> > > In any case, you could perhaps just drop the kernel header there just to
> > > use the exact same source for kernel and selftest.
> > >
> > You mean just copy/paste the entire header? There's a lot of stuff in
> > there which we
> > don't need it (yet).
>
> Right. It's mostly register definitions, which I don't think is too high
> of an overhead. Don't know where others stand, but I would prefer a
> header that is equivalent between kernel & selftests over a concise
> header.
>
Until now we haven't needed the sys_reg(...) type of definitions for
sysregs in selftests. In case we did, we defined the registers we
needed for get/set_one_reg by their parts, e.g.
#define ID_AA64DFR0_EL1 3, 0, 0, 5, 0
allowing us to choose how we use them, ARM64_SYS_REG(...) vs.
sys_reg(...).
Bringing over sysreg.h is probably a good idea though. If we do, then
I'd suggest we define a new macro that allows us to convert a SYS_*
register definition from sysreg.h into an ARM64_SYS_REG definition
for get/set_one_reg in order to avoid redundant definitions.
Thanks,
drew