From: Shivamurthy Shastri <[email protected]>
Added new Micron SPI NOR flashes to structure flash_info, which supports
advanced protection and security features.
Signed-off-by: Shivamurthy Shastri <[email protected]>
---
drivers/mtd/spi-nor/micron-st.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index b5d82e85fb92..2bebd76b091a 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -158,10 +158,17 @@ static const struct flash_info st_parts[] = {
SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128,
SECT_4K | SPI_NOR_QUAD_READ) },
+ { "mt25qu128abb", INFO6(0x20bb18, 0x12008c, 64 * 1024, 256,
+ SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
+ SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) },
{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256,
SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) },
+ { "mt25ql128abb", INFO6(0x20ba18, 0x12008c, 64 * 1024, 256,
+ SECT_4K | USE_FSR | SPI_NOR_HAS_LOCK |
+ SPI_NOR_QUAD_READ) },
{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256,
SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
{ "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512,
--
2.25.1
On 27/10/2021 11:33, [email protected] wrote:
> From: Shivamurthy Shastri <[email protected]>
>
> Added new Micron SPI NOR flashes to structure flash_info, which supports
> advanced protection and security features.
>
> Signed-off-by: Shivamurthy Shastri <[email protected]>
> ---
> drivers/mtd/spi-nor/micron-st.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
> index b5d82e85fb92..2bebd76b091a 100644
> --- a/drivers/mtd/spi-nor/micron-st.c
> +++ b/drivers/mtd/spi-nor/micron-st.c
> @@ -158,10 +158,17 @@ static const struct flash_info st_parts[] = {
> SECT_4K | SPI_NOR_QUAD_READ) },
> { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128,
> SECT_4K | SPI_NOR_QUAD_READ) },
> + { "mt25qu128abb", INFO6(0x20bb18, 0x12008c, 64 * 1024, 256,
> + SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
> + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
> + SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) },
> { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256,
> SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
> SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
> SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) },
> + { "mt25ql128abb", INFO6(0x20ba18, 0x12008c, 64 * 1024, 256,
> + SECT_4K | USE_FSR | SPI_NOR_HAS_LOCK |
> + SPI_NOR_QUAD_READ) },
> { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256,
> SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
> { "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512,
>
I suspect this patch can be submitted as a standalone. It doesn't seem
to depend on the others in this series.
Thanks,
--
Paul Barker
Principal Software Engineer
SanCloud Ltd
e: [email protected]
w: https://sancloud.co.uk/