This patches series adds a new driver for the timers found in the Mstar
MSC313e SoCs and newer. It adds a basic clocksource driver, the
corresponding devicetree bindings and its documentation.
Romain Perier (5):
clocksource: Add MStar MSC313e timer support
clocksource: msc313e: Add support for ssd20xd-based platforms
dt-bindings: timer: Add Mstar MSC313e timer devicetree bindings
documentation
ARM: dts: mstar: Add timers device nodes
ARM: dts: mstar: Switch to compatible "mstar,ssd20xd-timer" on ssd20xd
.../bindings/timer/mstar,msc313e-timer.yaml | 48 ++++
MAINTAINERS | 1 +
.../boot/dts/mstar-infinity2m-ssd20xd.dtsi | 18 ++
arch/arm/boot/dts/mstar-v7.dtsi | 20 ++
drivers/clocksource/Kconfig | 10 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-msc313e.c | 237 ++++++++++++++++++
7 files changed, 335 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/mstar,msc313e-timer.yaml
create mode 100644 drivers/clocksource/timer-msc313e.c
--
2.33.0
The rtc device node use an oscillator @12Mhz right now, namely
xtal_div2. rtc_xtal is no longer used, remove it.
Signed-off-by: Romain Perier <[email protected]>
---
arch/arm/boot/dts/mstar-v7.dtsi | 7 -------
1 file changed, 7 deletions(-)
diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi
index 89ebfe4f29da..9b335ee4512c 100644
--- a/arch/arm/boot/dts/mstar-v7.dtsi
+++ b/arch/arm/boot/dts/mstar-v7.dtsi
@@ -55,13 +55,6 @@ xtal: xtal {
clock-frequency = <24000000>;
};
- rtc_xtal: rtc_xtal {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- status = "disabled";
- };
-
xtal_div2: xtal_div2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
--
2.33.0
The MSC313e-compatible SoCs have 3 timer hardware blocks. All of these
are free running 32-bit increasing counters and can generate interrupts.
This commit adds basic support for these timers, the first timer block
being used as clocksource/sched_clock and delay, while the others will
be used as clockevents.
Signed-off-by: Romain Perier <[email protected]>
Co-developed-by: Daniel Palmer <[email protected]>
Signed-off-by: Daniel Palmer <[email protected]>
---
MAINTAINERS | 1 +
drivers/clocksource/Kconfig | 10 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-msc313e.c | 228 ++++++++++++++++++++++++++++
4 files changed, 240 insertions(+)
create mode 100644 drivers/clocksource/timer-msc313e.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 7a2345ce8521..f39a1617bf50 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2282,6 +2282,7 @@ F: Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml
F: arch/arm/boot/dts/mstar-*
F: arch/arm/mach-mstar/
F: drivers/clk/mstar/
+F: drivers/clocksource/timer-msc313e.c
F: drivers/gpio/gpio-msc313.c
F: drivers/rtc/rtc-msc313.c
F: drivers/watchdog/msc313e_wdt.c
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index f65e31bab9ae..822e711da284 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -671,6 +671,16 @@ config MILBEAUT_TIMER
help
Enables the support for Milbeaut timer driver.
+config MSC313E_TIMER
+ bool "MSC313E timer driver"
+ depends on ARCH_MSTARV7 || COMPILE_TEST
+ select TIMER_OF
+ select CLKSRC_MMIO
+ help
+ Enables support for the MStar MSC313E timer driver.
+ This provides access to multiple interrupt generating
+ programmable 32-bit free running incrementing counters.
+
config INGENIC_TIMER
bool "Clocksource/timer using the TCU in Ingenic JZ SoCs"
default MACH_INGENIC
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index c17ee32a7151..fa5f624eadb6 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -88,3 +88,4 @@ obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o
obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o
obj-$(CONFIG_HYPERV_TIMER) += hyperv_timer.o
obj-$(CONFIG_MICROCHIP_PIT64B) += timer-microchip-pit64b.o
+obj-$(CONFIG_MSC313E_TIMER) += timer-msc313e.o
diff --git a/drivers/clocksource/timer-msc313e.c b/drivers/clocksource/timer-msc313e.c
new file mode 100644
index 000000000000..81f161744349
--- /dev/null
+++ b/drivers/clocksource/timer-msc313e.c
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MStar timer driver
+ *
+ * Copyright (C) 2021 Daniel Palmer
+ * Copyright (C) 2021 Romain Perier
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqreturn.h>
+#include <linux/sched_clock.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/delay.h>
+
+#include "timer-of.h"
+
+#define TIMER_NAME "msc313e_timer"
+
+#define MSC313E_REG_CTRL 0x00
+#define MSC313E_REG_CTRL_TIMER_EN BIT(0)
+#define MSC313E_REG_CTRL_TIMER_TRIG BIT(1)
+#define MSC313E_REG_CTRL_TIMER_INT_EN BIT(8)
+#define MSC313E_REG_TIMER_MAX_LOW 0x08
+#define MSC313E_REG_TIMER_MAX_HIGH 0x0c
+#define MSC313E_REG_COUNTER_LOW 0x10
+#define MSC313E_REG_COUNTER_HIGH 0x14
+
+#define TIMER_SYNC_TICKS 3
+
+struct msc313e_delay {
+ void __iomem *base;
+ struct delay_timer delay;
+};
+
+static void __iomem *msc313e_clksrc;
+static struct msc313e_delay msc313e_delay;
+
+static void msc313e_timer_stop(void __iomem *base)
+{
+ writew(0, base + MSC313E_REG_CTRL);
+}
+
+static void msc313e_timer_start(void __iomem *base, bool periodic)
+{
+ u16 reg;
+
+ reg = readw(base + MSC313E_REG_CTRL);
+ if (periodic)
+ reg |= MSC313E_REG_CTRL_TIMER_EN;
+ else
+ reg |= MSC313E_REG_CTRL_TIMER_TRIG;
+ writew(reg | MSC313E_REG_CTRL_TIMER_INT_EN, base + MSC313E_REG_CTRL);
+}
+
+static void msc313e_timer_setup(void __iomem *base, unsigned long delay)
+{
+ writew(delay >> 16, base + MSC313E_REG_TIMER_MAX_HIGH);
+ writew(delay & 0xffff, base + MSC313E_REG_TIMER_MAX_LOW);
+}
+
+static unsigned long msc313e_timer_current_value(void __iomem *base)
+{
+ unsigned long result;
+
+ result = readw(base + MSC313E_REG_COUNTER_LOW);
+ result |= readw(base + MSC313E_REG_COUNTER_HIGH) << 16;
+
+ return result;
+}
+
+static int msc313e_timer_clkevt_shutdown(struct clock_event_device *evt)
+{
+ struct timer_of *timer = to_timer_of(evt);
+
+ msc313e_timer_stop(timer_of_base(timer));
+
+ return 0;
+}
+
+static int msc313e_timer_clkevt_set_oneshot(struct clock_event_device *evt)
+{
+ struct timer_of *timer = to_timer_of(evt);
+
+ msc313e_timer_stop(timer_of_base(timer));
+ msc313e_timer_start(timer_of_base(timer), false);
+
+ return 0;
+}
+
+static int msc313e_timer_clkevt_set_periodic(struct clock_event_device *evt)
+{
+ struct timer_of *timer = to_timer_of(evt);
+
+ msc313e_timer_stop(timer_of_base(timer));
+ msc313e_timer_setup(timer_of_base(timer), timer_of_period(timer));
+ msc313e_timer_start(timer_of_base(timer), true);
+
+ return 0;
+}
+
+static int msc313e_timer_clkevt_next_event(unsigned long evt, struct clock_event_device *clkevt)
+{
+ struct timer_of *timer = to_timer_of(clkevt);
+
+ msc313e_timer_stop(timer_of_base(timer));
+ msc313e_timer_setup(timer_of_base(timer), evt);
+ msc313e_timer_start(timer_of_base(timer), false);
+
+ return 0;
+}
+
+static irqreturn_t msc313e_timer_clkevt_irq(int irq, void *dev_id)
+{
+ struct clock_event_device *evt = dev_id;
+
+ evt->event_handler(evt);
+
+ return IRQ_HANDLED;
+}
+
+static u64 msc313e_timer_clksrc_read(struct clocksource *cs)
+{
+ return msc313e_timer_current_value(msc313e_clksrc) & cs->mask;
+}
+
+static unsigned long msc313e_read_delay_timer_read(void)
+{
+ return msc313e_timer_current_value(msc313e_delay.base);
+}
+
+static u64 msc313e_timer_sched_clock_read(void)
+{
+ return msc313e_timer_current_value(msc313e_clksrc);
+}
+
+static struct clock_event_device msc313e_clkevt = {
+ .name = TIMER_NAME,
+ .rating = 300,
+ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+ .set_state_shutdown = msc313e_timer_clkevt_shutdown,
+ .set_state_periodic = msc313e_timer_clkevt_set_periodic,
+ .set_state_oneshot = msc313e_timer_clkevt_set_oneshot,
+ .tick_resume = msc313e_timer_clkevt_shutdown,
+ .set_next_event = msc313e_timer_clkevt_next_event,
+};
+
+static int __init msc313e_clkevt_init(struct device_node *np)
+{
+ int ret;
+ struct timer_of *to;
+
+ to = kzalloc(sizeof(*to), GFP_KERNEL);
+ if (!to)
+ return -ENOMEM;
+
+ to->flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE;
+ to->of_irq.handler = msc313e_timer_clkevt_irq;
+ ret = timer_of_init(np, to);
+ if (ret)
+ return ret;
+
+ msc313e_clkevt.cpumask = cpu_possible_mask;
+ msc313e_clkevt.irq = to->of_irq.irq;
+ to->clkevt = msc313e_clkevt;
+
+ clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
+ TIMER_SYNC_TICKS, 0xffffffff);
+ return 0;
+}
+
+static int __init msc313e_clksrc_init(struct device_node *np)
+{
+ struct timer_of to = { 0 };
+ int ret;
+ u16 reg;
+
+ to.flags = TIMER_OF_BASE | TIMER_OF_CLOCK;
+ ret = timer_of_init(np, &to);
+ if (ret)
+ return ret;
+
+ msc313e_delay.base = timer_of_base(&to);
+ msc313e_delay.delay.read_current_timer = msc313e_read_delay_timer_read;
+ msc313e_delay.delay.freq = timer_of_rate(&to);
+
+ msc313e_clksrc = timer_of_base(&to);
+ reg = readw(msc313e_clksrc + MSC313E_REG_CTRL);
+ reg |= MSC313E_REG_CTRL_TIMER_EN;
+ writew(reg, msc313e_clksrc + MSC313E_REG_CTRL);
+
+ register_current_timer_delay(&msc313e_delay.delay);
+
+ sched_clock_register(msc313e_timer_sched_clock_read, 32, timer_of_rate(&to));
+ return clocksource_mmio_init(timer_of_base(&to), TIMER_NAME, timer_of_rate(&to), 300, 32,
+ msc313e_timer_clksrc_read);
+}
+
+static int __init msc313e_timer_init(struct device_node *np)
+{
+ int ret = 0;
+ static int num_called;
+
+ switch (num_called) {
+ case 0:
+ ret = msc313e_clksrc_init(np);
+ if (ret)
+ return ret;
+ break;
+
+ default:
+ ret = msc313e_clkevt_init(np);
+ if (ret)
+ return ret;
+ break;
+ }
+
+ num_called++;
+
+ return 0;
+}
+
+TIMER_OF_DECLARE(msc313, "mstar,msc313e-timer", msc313e_timer_init);
--
2.33.0
SSD20X family SoCs have an oscillator running at ~432Mhz for timer1 and
timer2, while timer0 is running at 12Mhz. There are no ways to reduce or
divide these clocks in the clktree. However, SSD20X SoCs provide an
internal "timer_divide" register that can act on this input oscillator.
This commit adds support for this register, as timer1 and timer2 are
used as clockevents these will run at 48Mhz.
Signed-off-by: Romain Perier <[email protected]>
---
drivers/clocksource/timer-msc313e.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/clocksource/timer-msc313e.c b/drivers/clocksource/timer-msc313e.c
index 81f161744349..6e7a0ece6601 100644
--- a/drivers/clocksource/timer-msc313e.c
+++ b/drivers/clocksource/timer-msc313e.c
@@ -30,7 +30,9 @@
#define MSC313E_REG_TIMER_MAX_HIGH 0x0c
#define MSC313E_REG_COUNTER_LOW 0x10
#define MSC313E_REG_COUNTER_HIGH 0x14
+#define MSC313E_REG_TIMER_DIVIDE 0x18
+#define MSC313E_CLK_DIVIDER 9
#define TIMER_SYNC_TICKS 3
struct msc313e_delay {
@@ -165,6 +167,12 @@ static int __init msc313e_clkevt_init(struct device_node *np)
if (ret)
return ret;
+ if (of_device_is_compatible(np, "mstar,ssd20xd-timer")) {
+ to->of_clk.rate = clk_get_rate(to->of_clk.clk) / MSC313E_CLK_DIVIDER;
+ to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ);
+ writew(MSC313E_CLK_DIVIDER - 1, timer_of_base(to) + MSC313E_REG_TIMER_DIVIDE);
+ }
+
msc313e_clkevt.cpumask = cpu_possible_mask;
msc313e_clkevt.irq = to->of_irq.irq;
to->clkevt = msc313e_clkevt;
@@ -226,3 +234,4 @@ static int __init msc313e_timer_init(struct device_node *np)
}
TIMER_OF_DECLARE(msc313, "mstar,msc313e-timer", msc313e_timer_init);
+TIMER_OF_DECLARE(ssd20xd, "mstar,ssd20xd-timer", msc313e_timer_init);
--
2.33.0
This adds the documentation for the devicetree bindings of the Mstar
MSC313e timer driver, found from MSC313e SoCs and newer.
Signed-off-by: Romain Perier <[email protected]>
---
.../bindings/timer/mstar,msc313e-timer.yaml | 48 +++++++++++++++++++
1 file changed, 48 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/mstar,msc313e-timer.yaml
diff --git a/Documentation/devicetree/bindings/timer/mstar,msc313e-timer.yaml b/Documentation/devicetree/bindings/timer/mstar,msc313e-timer.yaml
new file mode 100644
index 000000000000..f4d43e141dd0
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/mstar,msc313e-timer.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/mstar,msc313e-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mstar MSC313e Timer Device Tree Bindings
+
+maintainers:
+ - Daniel Palmer <[email protected]>
+ - Romain Perier <[email protected]>
+
+properties:
+ compatible:
+ enum:
+ - mstar,msc313e-timer
+ - mstar,ssd20xd-timer
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ start-year: true
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ timer@6040 {
+ compatible = "mstar,msc313e-timer";
+ reg = <0x6040 0x40>;
+ clocks = <&xtal_div2>;
+ interrupts-extended = <&intc_fiq GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+...
--
2.33.0
This adds the definition of the timers device node.
Signed-off-by: Romain Perier <[email protected]>
---
arch/arm/boot/dts/mstar-v7.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi
index 89ebfe4f29da..7ede4cec0af9 100644
--- a/arch/arm/boot/dts/mstar-v7.dtsi
+++ b/arch/arm/boot/dts/mstar-v7.dtsi
@@ -123,6 +123,26 @@ watchdog@6000 {
clocks = <&xtal_div2>;
};
+ timer@6040 {
+ compatible = "mstar,msc313e-timer";
+ reg = <0x6040 0x40>;
+ clocks = <&xtal_div2>;
+ interrupts-extended = <&intc_fiq GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ timer1: timer@6080 {
+ compatible = "mstar,msc313e-timer";
+ reg = <0x6080 0x40>;
+ clocks = <&xtal_div2>;
+ interrupts-extended = <&intc_fiq GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ timer2: timer@60c0 {
+ compatible = "mstar,msc313e-timer";
+ reg = <0x60c0 0x40>;
+ clocks = <&xtal_div2>;
+ interrupts-extended = <&intc_fiq GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ };
intc_fiq: interrupt-controller@201310 {
compatible = "mstar,mst-intc";
--
2.33.0
This defines the real oscillators as input of timer1 and timer2 and
switch to "mstar,ssd20xd-timer".
Signed-off-by: Romain Perier <[email protected]>
---
.../arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi
index 6f067da61ba3..6ff1f02e00a0 100644
--- a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi
+++ b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi
@@ -6,6 +6,14 @@
#include "mstar-infinity2m.dtsi"
+/ {
+ xtal_timer: timer_xtal {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <432000000>;
+ };
+};
+
&gpio {
compatible = "sstar,ssd20xd-gpio";
status = "okay";
@@ -15,3 +23,13 @@ &smpctrl {
compatible = "sstar,ssd201-smpctrl", "mstar,smpctrl";
status = "okay";
};
+
+&timer1 {
+ compatible = "mstar,ssd20xd-timer";
+ clocks = <&xtal_timer>;
+};
+
+&timer2 {
+ compatible = "mstar,ssd20xd-timer";
+ clocks = <&xtal_timer>;
+};
--
2.33.0
Hi Romain,
On Sat, 27 Nov 2021 at 05:22, Romain Perier <[email protected]> wrote:
>
> The rtc device node use an oscillator @12Mhz right now, namely
> xtal_div2. rtc_xtal is no longer used, remove it.
Drop this one. We will use rtc_xtal eventually.
Cheers,
Daniel
Hi Romain,
On Sat, 27 Nov 2021 at 05:22, Romain Perier <[email protected]> wrote:
>
> This adds the documentation for the devicetree bindings of the Mstar
> MSC313e timer driver, found from MSC313e SoCs and newer.
>
> Signed-off-by: Romain Perier <[email protected]>
> ---
> .../bindings/timer/mstar,msc313e-timer.yaml | 48 +++++++++++++++++++
> 1 file changed, 48 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/mstar,msc313e-timer.yaml
>
> diff --git a/Documentation/devicetree/bindings/timer/mstar,msc313e-timer.yaml b/Documentation/devicetree/bindings/timer/mstar,msc313e-timer.yaml
> new file mode 100644
> index 000000000000..f4d43e141dd0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/mstar,msc313e-timer.yaml
> @@ -0,0 +1,48 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/timer/mstar,msc313e-timer.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mstar MSC313e Timer Device Tree Bindings
> +
> +maintainers:
> + - Daniel Palmer <[email protected]>
> + - Romain Perier <[email protected]>
> +
> +properties:
> + compatible:
> + enum:
> + - mstar,msc313e-timer
> + - mstar,ssd20xd-timer
I think s/mstar,ssd20xd-timer/sstar-ssd20xd-timer/ as the SSD201 and
SSD202D were never MStar parts.
The SigmaStar prefix is already in the vendor prefixes.
Cheers,
Daniel
Hi Romain,
On Sat, 27 Nov 2021 at 05:22, Romain Perier <[email protected]> wrote:
>
> This defines the real oscillators as input of timer1 and timer2 and
> switch to "mstar,ssd20xd-timer".
>
> Signed-off-by: Romain Perier <[email protected]>
> ---
> .../arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi
> index 6f067da61ba3..6ff1f02e00a0 100644
> --- a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi
> +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi
> @@ -6,6 +6,14 @@
>
> #include "mstar-infinity2m.dtsi"
>
> +/ {
> + xtal_timer: timer_xtal {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <432000000>;
> + };
> +};
mm I think xtal is a bit confusing here. This isn't an external
crystal but a fixed clock because we can't find where the clock is
coming from yet.
So maybe this should be s/xtal/clk/ or something?
Maybe a comment about why we need this like "A header in the vendor
kernel says the timers clk comes from XIU clock but we don't know
what/where XIU clock is yet".
> &gpio {
> compatible = "sstar,ssd20xd-gpio";
> status = "okay";
> @@ -15,3 +23,13 @@ &smpctrl {
> compatible = "sstar,ssd201-smpctrl", "mstar,smpctrl";
> status = "okay";
> };
> +
> +&timer1 {
> + compatible = "mstar,ssd20xd-timer";
> + clocks = <&xtal_timer>;
> +};
I think we should do this for timer0 too. As the below hunk in the
driver will change the clock divider (For others reading this: The
boot ROM in the chip sets a divider for timer0 to get something ~12MHz
to stay compatible with their u-boot that expects 12MHz)) and timer0
will have the right clock rate instead of the roughly 12MHz but not
really 12MHz frequency it has from boot and we don't need to rely on
the divider value for timer0 being correct on boot.
+ if (of_device_is_compatible(np, "mstar,ssd20xd-timer")) {
+ to->of_clk.rate = clk_get_rate(to->of_clk.clk) /
MSC313E_CLK_DIVIDER;
+ to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ);
+ writew(MSC313E_CLK_DIVIDER - 1, timer_of_base(to) +
MSC313E_REG_TIMER_DIVIDE);
+ }
+
Cheers,
Daniel
Hi Romain,
On Sat, 27 Nov 2021 at 05:22, Romain Perier <[email protected]> wrote:
>
> This defines the real oscillators as input of timer1 and timer2 and
> switch to "mstar,ssd20xd-timer".
>
> Signed-off-by: Romain Perier <[email protected]>
> ---
> .../arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi
I just noticed this during testing. I think we should put this in
mstar-infinity2m.dts. All of the infinity2m chips use the same die
from what I can tell so if the ssd201/ssd202d needs this then anything
else that includes mstar-infinity2m.dtsi will too.
Cheers,
Daniel
On 26/11/2021 21:21, Romain Perier wrote:
> The MSC313e-compatible SoCs have 3 timer hardware blocks. All of these
> are free running 32-bit increasing counters and can generate interrupts.
> This commit adds basic support for these timers, the first timer block
> being used as clocksource/sched_clock and delay, while the others will
> be used as clockevents.
Please you elaborate a bit more the internals of this timer as it is a
initial submission
> Signed-off-by: Romain Perier <[email protected]>
> Co-developed-by: Daniel Palmer <[email protected]>
> Signed-off-by: Daniel Palmer <[email protected]>
> ---
> MAINTAINERS | 1 +
> drivers/clocksource/Kconfig | 10 ++
> drivers/clocksource/Makefile | 1 +
> drivers/clocksource/timer-msc313e.c | 228 ++++++++++++++++++++++++++++
> 4 files changed, 240 insertions(+)
> create mode 100644 drivers/clocksource/timer-msc313e.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 7a2345ce8521..f39a1617bf50 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2282,6 +2282,7 @@ F: Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml
> F: arch/arm/boot/dts/mstar-*
> F: arch/arm/mach-mstar/
> F: drivers/clk/mstar/
> +F: drivers/clocksource/timer-msc313e.c
> F: drivers/gpio/gpio-msc313.c
> F: drivers/rtc/rtc-msc313.c
> F: drivers/watchdog/msc313e_wdt.c
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index f65e31bab9ae..822e711da284 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -671,6 +671,16 @@ config MILBEAUT_TIMER
> help
> Enables the support for Milbeaut timer driver.
>
> +config MSC313E_TIMER
> + bool "MSC313E timer driver"
Silent option please and platform config option enables it.
> + depends on ARCH_MSTARV7 || COMPILE_TEST
> + select TIMER_OF
> + select CLKSRC_MMIO
> + help
> + Enables support for the MStar MSC313E timer driver.
> + This provides access to multiple interrupt generating
> + programmable 32-bit free running incrementing counters.
> +
> config INGENIC_TIMER
> bool "Clocksource/timer using the TCU in Ingenic JZ SoCs"
> default MACH_INGENIC
> diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
> index c17ee32a7151..fa5f624eadb6 100644
> --- a/drivers/clocksource/Makefile
> +++ b/drivers/clocksource/Makefile
> @@ -88,3 +88,4 @@ obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o
> obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o
> obj-$(CONFIG_HYPERV_TIMER) += hyperv_timer.o
> obj-$(CONFIG_MICROCHIP_PIT64B) += timer-microchip-pit64b.o
> +obj-$(CONFIG_MSC313E_TIMER) += timer-msc313e.o
> diff --git a/drivers/clocksource/timer-msc313e.c b/drivers/clocksource/timer-msc313e.c
> new file mode 100644
> index 000000000000..81f161744349
> --- /dev/null
> +++ b/drivers/clocksource/timer-msc313e.c
> @@ -0,0 +1,228 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * MStar timer driver
> + *
> + * Copyright (C) 2021 Daniel Palmer
> + * Copyright (C) 2021 Romain Perier
> + *
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clockchips.h>
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/irqreturn.h>
> +#include <linux/sched_clock.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/delay.h>
> +
> +#include "timer-of.h"
> +
> +#define TIMER_NAME "msc313e_timer"
> +
> +#define MSC313E_REG_CTRL 0x00
> +#define MSC313E_REG_CTRL_TIMER_EN BIT(0)
> +#define MSC313E_REG_CTRL_TIMER_TRIG BIT(1)
> +#define MSC313E_REG_CTRL_TIMER_INT_EN BIT(8)
> +#define MSC313E_REG_TIMER_MAX_LOW 0x08
> +#define MSC313E_REG_TIMER_MAX_HIGH 0x0c
> +#define MSC313E_REG_COUNTER_LOW 0x10
> +#define MSC313E_REG_COUNTER_HIGH 0x14
> +
> +#define TIMER_SYNC_TICKS 3
> +
> +struct msc313e_delay {
> + void __iomem *base;
> + struct delay_timer delay;
> +};
> +
> +static void __iomem *msc313e_clksrc;
> +static struct msc313e_delay msc313e_delay;
I'm not sure that compiles on other platform than mstarv7
> +static void msc313e_timer_stop(void __iomem *base)
> +{
> + writew(0, base + MSC313E_REG_CTRL);
> +}
> +
> +static void msc313e_timer_start(void __iomem *base, bool periodic)
> +{
> + u16 reg;
> +
> + reg = readw(base + MSC313E_REG_CTRL);
> + if (periodic)
> + reg |= MSC313E_REG_CTRL_TIMER_EN;
> + else
> + reg |= MSC313E_REG_CTRL_TIMER_TRIG;
> + writew(reg | MSC313E_REG_CTRL_TIMER_INT_EN, base + MSC313E_REG_CTRL);
> +}
> +
> +static void msc313e_timer_setup(void __iomem *base, unsigned long delay)
> +{
> + writew(delay >> 16, base + MSC313E_REG_TIMER_MAX_HIGH);
> + writew(delay & 0xffff, base + MSC313E_REG_TIMER_MAX_LOW);
Is it safe? (eg. arc_timer.c?)
> +}
> +
> +static unsigned long msc313e_timer_current_value(void __iomem *base)
> +{
> + unsigned long result;
> +
> + result = readw(base + MSC313E_REG_COUNTER_LOW);
> + result |= readw(base + MSC313E_REG_COUNTER_HIGH) << 16;
Is it safe?
cf. timer-microchip-pit64b.c and/or arc_timer.c
> + return result;
> +}
> +
> +static int msc313e_timer_clkevt_shutdown(struct clock_event_device *evt)
> +{
> + struct timer_of *timer = to_timer_of(evt);
> +
> + msc313e_timer_stop(timer_of_base(timer));
> +
> + return 0;
> +}
> +
> +static int msc313e_timer_clkevt_set_oneshot(struct clock_event_device *evt)
> +{
> + struct timer_of *timer = to_timer_of(evt);
> +
> + msc313e_timer_stop(timer_of_base(timer));
> + msc313e_timer_start(timer_of_base(timer), false);
> +
> + return 0;
> +}
> +
> +static int msc313e_timer_clkevt_set_periodic(struct clock_event_device *evt)
> +{
> + struct timer_of *timer = to_timer_of(evt);
> +
> + msc313e_timer_stop(timer_of_base(timer));
> + msc313e_timer_setup(timer_of_base(timer), timer_of_period(timer));
> + msc313e_timer_start(timer_of_base(timer), true);
> +
> + return 0;
> +}
> +
> +static int msc313e_timer_clkevt_next_event(unsigned long evt, struct clock_event_device *clkevt)
> +{
> + struct timer_of *timer = to_timer_of(clkevt);
> +
> + msc313e_timer_stop(timer_of_base(timer));
> + msc313e_timer_setup(timer_of_base(timer), evt);
> + msc313e_timer_start(timer_of_base(timer), false);
> +
> + return 0;
> +}
> +
> +static irqreturn_t msc313e_timer_clkevt_irq(int irq, void *dev_id)
> +{
> + struct clock_event_device *evt = dev_id;
> +
> + evt->event_handler(evt);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static u64 msc313e_timer_clksrc_read(struct clocksource *cs)
> +{
> + return msc313e_timer_current_value(msc313e_clksrc) & cs->mask;
> +}
> +
> +static unsigned long msc313e_read_delay_timer_read(void)
> +{
> + return msc313e_timer_current_value(msc313e_delay.base);
> +}
> +
> +static u64 msc313e_timer_sched_clock_read(void)
> +{
> + return msc313e_timer_current_value(msc313e_clksrc);
> +}
> +
> +static struct clock_event_device msc313e_clkevt = {
> + .name = TIMER_NAME,
> + .rating = 300,
> + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
> + .set_state_shutdown = msc313e_timer_clkevt_shutdown,
> + .set_state_periodic = msc313e_timer_clkevt_set_periodic,
> + .set_state_oneshot = msc313e_timer_clkevt_set_oneshot,
> + .tick_resume = msc313e_timer_clkevt_shutdown,
> + .set_next_event = msc313e_timer_clkevt_next_event,
> +};
> +
> +static int __init msc313e_clkevt_init(struct device_node *np)
> +{
> + int ret;
> + struct timer_of *to;
> +
> + to = kzalloc(sizeof(*to), GFP_KERNEL);
> + if (!to)
> + return -ENOMEM;
> +
> + to->flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE;
> + to->of_irq.handler = msc313e_timer_clkevt_irq;
> + ret = timer_of_init(np, to);
> + if (ret)
> + return ret;
> +
> + msc313e_clkevt.cpumask = cpu_possible_mask;
> + msc313e_clkevt.irq = to->of_irq.irq;
> + to->clkevt = msc313e_clkevt;
> +
> + clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
> + TIMER_SYNC_TICKS, 0xffffffff);
> + return 0;
> +}
> +
> +static int __init msc313e_clksrc_init(struct device_node *np)
> +{
> + struct timer_of to = { 0 };
> + int ret;
> + u16 reg;
> +
> + to.flags = TIMER_OF_BASE | TIMER_OF_CLOCK;
> + ret = timer_of_init(np, &to);
> + if (ret)
> + return ret;
> +
> + msc313e_delay.base = timer_of_base(&to);
> + msc313e_delay.delay.read_current_timer = msc313e_read_delay_timer_read;
> + msc313e_delay.delay.freq = timer_of_rate(&to);
> +
> + msc313e_clksrc = timer_of_base(&to);
> + reg = readw(msc313e_clksrc + MSC313E_REG_CTRL);
> + reg |= MSC313E_REG_CTRL_TIMER_EN;
> + writew(reg, msc313e_clksrc + MSC313E_REG_CTRL);
> +
> + register_current_timer_delay(&msc313e_delay.delay);
> +
> + sched_clock_register(msc313e_timer_sched_clock_read, 32, timer_of_rate(&to));
> + return clocksource_mmio_init(timer_of_base(&to), TIMER_NAME, timer_of_rate(&to), 300, 32,
> + msc313e_timer_clksrc_read);
format 80char max please, run checkpatch.pl before submitting
> +}
> +
> +static int __init msc313e_timer_init(struct device_node *np)
> +{
> + int ret = 0;
> + static int num_called;
> +
> + switch (num_called) {
> + case 0:
> + ret = msc313e_clksrc_init(np);
> + if (ret)
> + return ret;
> + break;
> +
> + default:
> + ret = msc313e_clkevt_init(np);
> + if (ret)
> + return ret;
> + break;
> + }
> +
> + num_called++;
> +
> + return 0;
> +}
> +
> +TIMER_OF_DECLARE(msc313, "mstar,msc313e-timer", msc313e_timer_init);
>
--
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On 30/11/2021 15:12, Romain Perier wrote:
> Hi,
>
> Le lun. 29 nov. 2021 à 18:02, Daniel Lezcano <[email protected]
> <mailto:[email protected]>> a écrit :
>
> On 26/11/2021 21:21, Romain Perier wrote:
> > The MSC313e-compatible SoCs have 3 timer hardware blocks. All of these
> > are free running 32-bit increasing counters and can generate
> interrupts.
> > This commit adds basic support for these timers, the first timer block
> > being used as clocksource/sched_clock and delay, while the others will
> > be used as clockevents.
>
> Please you elaborate a bit more the internals of this timer as it is a
> initial submission
>
>
> Ok, will try to elaborate.
>
>
>
>
> > Signed-off-by: Romain Perier <[email protected]
> <mailto:[email protected]>>
> > Co-developed-by: Daniel Palmer <[email protected]
> <mailto:[email protected]>>
> > Signed-off-by: Daniel Palmer <[email protected]
> <mailto:[email protected]>>
> > ---
> > MAINTAINERS | 1 +
> > drivers/clocksource/Kconfig | 10 ++
> > drivers/clocksource/Makefile | 1 +
> > drivers/clocksource/timer-msc313e.c | 228
> ++++++++++++++++++++++++++++
> > 4 files changed, 240 insertions(+)
> > create mode 100644 drivers/clocksource/timer-msc313e.c
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 7a2345ce8521..f39a1617bf50 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -2282,6 +2282,7 @@ F:
> Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml
> > F: arch/arm/boot/dts/mstar-*
> > F: arch/arm/mach-mstar/
> > F: drivers/clk/mstar/
> > +F: drivers/clocksource/timer-msc313e.c
> > F: drivers/gpio/gpio-msc313.c
> > F: drivers/rtc/rtc-msc313.c
> > F: drivers/watchdog/msc313e_wdt.c
> > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> > index f65e31bab9ae..822e711da284 100644
> > --- a/drivers/clocksource/Kconfig
> > +++ b/drivers/clocksource/Kconfig
> > @@ -671,6 +671,16 @@ config MILBEAUT_TIMER
> > help
> > Enables the support for Milbeaut timer driver.
> >
> > +config MSC313E_TIMER
> > + bool "MSC313E timer driver"
>
> Silent option please and platform config option enables it.
>
>
> What do you mean ? no short description at all ?
We try to let the platform Kconfig option to select silently the timer
in order to prevent selecting it manually.
If the timer is mandatory on your platform it should be a silent option,
except for COMPILE_TEST
That leads to:
bool "MSC313E timer driver" if COMPILE_TEST
and you should be able to compile it on x86, ...
If the timer is optional because there is another one on the platform,
it could be unselected manually. That is the configuration you've done here.
So if there is no other broadcast timer, this timer should selected for
the platform and the option should be silent (except in case of
COMPILE_TEST).
> > + depends on ARCH_MSTARV7 || COMPILE_TEST
> > + select TIMER_OF
> > + select CLKSRC_MMIO
> > + help
> > + Enables support for the MStar MSC313E timer driver.
> > + This provides access to multiple interrupt generating
> > + programmable 32-bit free running incrementing counters.
> > +
> > config INGENIC_TIMER
[ ... ]
> > +
> > +struct msc313e_delay {
> > + void __iomem *base;
> > + struct delay_timer delay;
> > +};
> > +
> > +static void __iomem *msc313e_clksrc;
> > +static struct msc313e_delay msc313e_delay;
>
> I'm not sure that compiles on other platform than mstarv7
>
>
> It is armv7-based, and its size is known at build-time, no ?
> Everything builds with WERROR here.
I should have say "arch" instead of "platform".
The COMPILE_TEST option is set above, that means the driver can be
compiled on a x86 (for compilation test coverage, stubs already exists
except for delay AFAIR).
[ ... ]
> > + msc313e_delay.base = timer_of_base(&to);
> > + msc313e_delay.delay.read_current_timer =
> msc313e_read_delay_timer_read;
> > + msc313e_delay.delay.freq = timer_of_rate(&to);
> > +
> > + msc313e_clksrc = timer_of_base(&to);
> > + reg = readw(msc313e_clksrc + MSC313E_REG_CTRL);
> > + reg |= MSC313E_REG_CTRL_TIMER_EN;
> > + writew(reg, msc313e_clksrc + MSC313E_REG_CTRL);
> > +
> > + register_current_timer_delay(&msc313e_delay.delay);
> > +
> > + sched_clock_register(msc313e_timer_sched_clock_read, 32,
> timer_of_rate(&to));
> > + return clocksource_mmio_init(timer_of_base(&to), TIMER_NAME,
> timer_of_rate(&to), 300, 32,
> > + msc313e_timer_clksrc_read);
>
> format 80char max please, run checkpatch.pl <http://checkpatch.pl>
> before submitting
>
>
> max_line_lenght is set to "100" in checkpatch.pl <http://checkpatch.pl>
> since a while now :) .
> I have passed it with "--strict" before sending the series, however, if
> you prefer 80 chars
> max just ask, I can limit to 80 chars.
Oh, indeed. Fair enough, limit to 80 chars is now deprecated and
suggested length is 100.
In this case, at your convenience.
Thanks
-- Daniel
--
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On Fri, Nov 26, 2021 at 09:21:42PM +0100, Romain Perier wrote:
> This adds the documentation for the devicetree bindings of the Mstar
> MSC313e timer driver, found from MSC313e SoCs and newer.
>
> Signed-off-by: Romain Perier <[email protected]>
> ---
> .../bindings/timer/mstar,msc313e-timer.yaml | 48 +++++++++++++++++++
> 1 file changed, 48 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/mstar,msc313e-timer.yaml
>
> diff --git a/Documentation/devicetree/bindings/timer/mstar,msc313e-timer.yaml b/Documentation/devicetree/bindings/timer/mstar,msc313e-timer.yaml
> new file mode 100644
> index 000000000000..f4d43e141dd0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/mstar,msc313e-timer.yaml
> @@ -0,0 +1,48 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/timer/mstar,msc313e-timer.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mstar MSC313e Timer Device Tree Bindings
> +
> +maintainers:
> + - Daniel Palmer <[email protected]>
> + - Romain Perier <[email protected]>
> +
> +properties:
> + compatible:
> + enum:
> + - mstar,msc313e-timer
> + - mstar,ssd20xd-timer
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + start-year: true
This is an rtc property. You would need to $ref rtc.yaml, but then that
also says the node name is 'rtc'. But why do you need a start year for a
clocksource?
> +
> + clocks:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + timer@6040 {
> + compatible = "mstar,msc313e-timer";
> + reg = <0x6040 0x40>;
> + clocks = <&xtal_div2>;
> + interrupts-extended = <&intc_fiq GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +...
> --
> 2.33.0
>
>
Hi Romain,
On Mon, 13 Dec 2021 at 01:10, Romain Perier <[email protected]> wrote:
>> I just noticed this during testing. I think we should put this in
>> mstar-infinity2m.dts. All of the infinity2m chips use the same die
>> from what I can tell so if the ssd201/ssd202d needs this then anything
>> else that includes mstar-infinity2m.dtsi will too.
>
>
> Mhhh, makes sense.
> Do we keep the compatible "sstar,ssd20xd-timer" in this case ?
> Because this is true for either the SSR621D or the SSD201 or the SSD202D,
> so... what about "sstar,ssxd-timer", or something like this ?
I think for anything infinity2m specific we use "sstar,ssd20xd-timer"
as the SSD201 and SSD202D are the first chips we found this in.
The SSR621D might get some specific compatibles for things that only
it has broken out like the SATA.
Cheers,
Daniel