The PHYTEC PEV-EVAL-01 expansion board adds support for additional
gpio-triggered user-leds and gpio-key support.
Signed-off-by: Yunus Bas <[email protected]>
---
Changes in v2:
- Changed node-name and lable of a gpio-key to fit the key binding
---
.../boot/dts/imx6dl-phytec-mira-rdk-nand.dts | 1 +
.../boot/dts/imx6q-phytec-mira-rdk-emmc.dts | 1 +
.../boot/dts/imx6q-phytec-mira-rdk-nand.dts | 1 +
.../dts/imx6qdl-phytec-mira-peb-eval-01.dtsi | 71 +++++++++++++++++++
.../boot/dts/imx6qp-phytec-mira-rdk-nand.dts | 1 +
5 files changed, 75 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi
diff --git a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
index 9f7f9f98139d..b057fa664a6b 100644
--- a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
@@ -8,6 +8,7 @@
#include "imx6dl.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
#include "imx6qdl-phytec-mira.dtsi"
+#include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
/ {
model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND";
diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
index 2e70ea5623c6..db6e2cc36759 100644
--- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
+++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
@@ -8,6 +8,7 @@
#include "imx6q.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
#include "imx6qdl-phytec-mira.dtsi"
+#include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
/ {
model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC";
diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
index 65d2e483c136..51ff601b1aec 100644
--- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
@@ -8,6 +8,7 @@
#include "imx6q.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
#include "imx6qdl-phytec-mira.dtsi"
+#include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
/ {
model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND";
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi
new file mode 100644
index 000000000000..037b60197598
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 PHYTEC Messtechnik
+ * Author: Christian Hemp <[email protected]>
+ */
+
+#include <dt-bindings/input/input.h>
+
+/ {
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+ status = "disabled";
+
+ power {
+ label = "Power Button";
+ gpios = <&gpio5 28 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WAKEUP>;
+ wakeup-source;
+ };
+
+ sleep {
+ label = "Sleep Button";
+ gpios = <&gpio6 18 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_SLEEP>;
+ };
+ };
+
+ user_leds: user-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_user_leds>;
+ status = "disabled";
+
+ user-led1 {
+ gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "gpio";
+ default-state = "on";
+ };
+
+ user-led2 {
+ gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "gpio";
+ default-state = "on";
+ };
+
+ user-led3 {
+ gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "gpio";
+ default-state = "on";
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl_gpio_keys: gpiokeysgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b0
+ >;
+ };
+
+ pinctrl_user_leds: userledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
index f27d7ab42626..06fe0c5315fc 100644
--- a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
@@ -8,6 +8,7 @@
#include "imx6qp.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
#include "imx6qdl-phytec-mira.dtsi"
+#include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
/ {
model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND";
--
2.25.1
The PEB-AV-02 expansion adapter extends the phyBOARD-Mira boards to
connect parallel LCD displays, either with capacitive or resistive
touch.
Signed-off-by: Yunus Bas <[email protected]>
---
Changes in v2:
- Corrected confusing display node name
- Updated edt_ft5406 compatible to fit dt-binding scheme
- Removed some newlines
---
.../boot/dts/imx6dl-phytec-mira-rdk-nand.dts | 1 +
.../boot/dts/imx6q-phytec-mira-rdk-emmc.dts | 1 +
.../boot/dts/imx6q-phytec-mira-rdk-nand.dts | 1 +
.../dts/imx6qdl-phytec-mira-peb-av-02.dtsi | 119 ++++++++++++++++++
.../boot/dts/imx6qp-phytec-mira-rdk-nand.dts | 1 +
5 files changed, 123 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi
diff --git a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
index b057fa664a6b..8165fae2b1d1 100644
--- a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
@@ -9,6 +9,7 @@
#include "imx6qdl-phytec-phycore-som.dtsi"
#include "imx6qdl-phytec-mira.dtsi"
#include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
+#include "imx6qdl-phytec-mira-peb-av-02.dtsi"
/ {
model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND";
diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
index db6e2cc36759..bbf5097ca974 100644
--- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
+++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
@@ -9,6 +9,7 @@
#include "imx6qdl-phytec-phycore-som.dtsi"
#include "imx6qdl-phytec-mira.dtsi"
#include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
+#include "imx6qdl-phytec-mira-peb-av-02.dtsi"
/ {
model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC";
diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
index 51ff601b1aec..95051e18324f 100644
--- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
@@ -9,6 +9,7 @@
#include "imx6qdl-phytec-phycore-som.dtsi"
#include "imx6qdl-phytec-mira.dtsi"
#include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
+#include "imx6qdl-phytec-mira-peb-av-02.dtsi"
/ {
model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND";
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi
new file mode 100644
index 000000000000..9fa1de1fcace
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 PHYTEC Messtechnik
+ * Author: Christian Hemp <[email protected]>
+ */
+
+/ {
+ display: disp0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx-parallel-display";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_disp0>;
+ interface-pix-fmt = "rgb24";
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ display0_in: endpoint {
+ remote-endpoint = <&ipu1_di0_disp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ display0_out: endpoint {
+ remote-endpoint = <&peb_panel_lcd_in>;
+ };
+ };
+ };
+
+ panel-lcd {
+ compatible = "edt,etm0700g0edh6";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_disp0_pwr>;
+ power-supply = <®_display>;
+ enable-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+ backlight = <&backlight>;
+ status = "disabled";
+
+ port {
+ peb_panel_lcd_in: endpoint {
+ remote-endpoint = <&display0_out>;
+ };
+ };
+ };
+
+ reg_display: regulator-peb-display {
+ compatible = "regulator-fixed";
+ regulator-name = "peb-display";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&i2c1 {
+ edt_ft5x06: touchscreen@38 {
+ compatible = "edt,edt-ft5406";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_edt_ft5x06>;
+ reg = <0x38>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <2 IRQ_TYPE_NONE>;
+ status = "disabled";
+ };
+};
+
+&ipu1_di0_disp0 {
+ remote-endpoint = <&display0_in>;
+};
+
+&iomuxc {
+ pinctrl_disp0: disp0grp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
+ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
+ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
+ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x1b080
+ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
+ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
+ MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
+ MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
+ MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
+ MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
+ MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
+ MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
+ >;
+ };
+
+ pinctrl_disp0_pwr: disp0pwrgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
+ >;
+ };
+
+ pinctrl_edt_ft5x06: edtft5x06grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0xb0b1
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
index 06fe0c5315fc..343639cb035c 100644
--- a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
@@ -9,6 +9,7 @@
#include "imx6qdl-phytec-phycore-som.dtsi"
#include "imx6qdl-phytec-mira.dtsi"
#include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
+#include "imx6qdl-phytec-mira-peb-av-02.dtsi"
/ {
model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND";
--
2.25.1
The PEB-WLBT-05 is equipped with a Sterling-LWB radio module, which is
capable of Wi-Fi 802.11 b/g/n and Bluetooth 4.2.
Signed-off-by: Yunus Bas <[email protected]>
---
Changes in v2:
- Changed node-name underscores to hyphens
---
.../boot/dts/imx6dl-phytec-mira-rdk-nand.dts | 1 +
.../boot/dts/imx6q-phytec-mira-rdk-emmc.dts | 1 +
.../boot/dts/imx6q-phytec-mira-rdk-nand.dts | 1 +
.../dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi | 82 +++++++++++++++++
.../boot/dts/imx6qp-phytec-mira-rdk-nand.dts | 1 +
.../dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 1 +
.../dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi | 87 +++++++++++++++++++
.../dts/imx6ull-phytec-segin-ff-rdk-nand.dts | 1 +
.../dts/imx6ull-phytec-segin-lc-rdk-nand.dts | 1 +
.../dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi | 19 ++++
10 files changed, 195 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi
create mode 100644 arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi
diff --git a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
index 8165fae2b1d1..d906a7f05aaa 100644
--- a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
@@ -10,6 +10,7 @@
#include "imx6qdl-phytec-mira.dtsi"
#include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
#include "imx6qdl-phytec-mira-peb-av-02.dtsi"
+#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi"
/ {
model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND";
diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
index bbf5097ca974..322f071d972f 100644
--- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
+++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
@@ -10,6 +10,7 @@
#include "imx6qdl-phytec-mira.dtsi"
#include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
#include "imx6qdl-phytec-mira-peb-av-02.dtsi"
+#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi"
/ {
model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC";
diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
index 95051e18324f..3f13726c8058 100644
--- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
@@ -10,6 +10,7 @@
#include "imx6qdl-phytec-mira.dtsi"
#include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
#include "imx6qdl-phytec-mira-peb-av-02.dtsi"
+#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi"
/ {
model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND";
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi
new file mode 100644
index 000000000000..0abf3e1e1f62
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 PHYTEC Messtechnik GmbH
+ * Author: Yunus Bas <[email protected]>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ reg_wl_en: regulator-wl-en {
+ compatible = "regulator-fixed";
+ regulator-name = "wlan_en";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wl>;
+ gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100>;
+ status = "disabled";
+ };
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3_bt>;
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ shutdown-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
+ device-wakeup-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3_wl>;
+ vmmc-supply = <®_wl_en>;
+ bus-width = <4>;
+ non-removable;
+ no-1-8-v;
+ status = "disabled";
+
+ brmcf: wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+&iomuxc {
+ pinctrl_uart3_bt: uart3grp-bt {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0xb0b1 /* BT ENABLE */
+ MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0xb0b1 /* DEV WAKEUP */
+ MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0xb0b1 /* HOST WAKEUP */
+ >;
+ };
+
+ pinctrl_usdhc3_wl: usdhc3grp-wl {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_wl: wlgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0xb0b1 /* WLAN ENABLE */
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
index 343639cb035c..a18266598d39 100644
--- a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
@@ -10,6 +10,7 @@
#include "imx6qdl-phytec-mira.dtsi"
#include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
#include "imx6qdl-phytec-mira-peb-av-02.dtsi"
+#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi"
/ {
model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND";
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
index bff98e676980..607eddc5030f 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
@@ -10,6 +10,7 @@
#include "imx6ul-phytec-segin.dtsi"
#include "imx6ul-phytec-segin-peb-eval-01.dtsi"
#include "imx6ul-phytec-segin-peb-av-02.dtsi"
+#include "imx6ul-phytec-segin-peb-wlbt-05.dtsi"
/ {
model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND";
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi
new file mode 100644
index 000000000000..4a75745d6030
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 PHYTEC Messtechnik GmbH
+ * Author: Yunus Bas <[email protected]>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ reg_wl_en: regulator-wl-en {
+ compatible = "regulator-fixed";
+ regulator-name = "wlan_en";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wl>;
+ gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100>;
+ status = "disabled";
+ };
+};
+
+&iomuxc {
+ pinctrl_bt: btgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3031 /* BT ENABLE */
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x3031 /* HOST WAKEUP */
+ MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x3031 /* DEV WAKEUP */
+ >;
+ };
+
+ pinctrl_uart2_bt: uart2grp-bt {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x17059
+ MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x17059
+ MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x17059
+ MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2_wl: usdhc2grp-wl {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x10051
+ MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x10061
+ MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x10051
+ MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x10051
+ MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x10051
+ MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x10051
+ >;
+ };
+
+ pinctrl_wl: wlgrp {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3031 /* WLAN ENABLE */
+ >;
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_bt &pinctrl_bt>;
+ uart-has-rtscts;
+ status = "disabled";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ device-wakeup-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2_wl>;
+ vmmc-supply = <®_wl_en>;
+ bus-width = <4>;
+ non-removable;
+ no-1-8-v;
+ status = "disabled";
+
+ brmcf: wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
index c8d3eff9ed4b..1d7362b5ac91 100644
--- a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
@@ -10,6 +10,7 @@
#include "imx6ull-phytec-segin.dtsi"
#include "imx6ull-phytec-segin-peb-eval-01.dtsi"
#include "imx6ull-phytec-segin-peb-av-02.dtsi"
+#include "imx6ull-phytec-segin-peb-wlbt-05.dtsi"
/ {
model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with NAND";
diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts
index e168494e0a6d..4bcbae024d8d 100644
--- a/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts
@@ -9,6 +9,7 @@
#include "imx6ull-phytec-phycore-som.dtsi"
#include "imx6ull-phytec-segin.dtsi"
#include "imx6ull-phytec-segin-peb-eval-01.dtsi"
+#include "imx6ull-phytec-segin-peb-wlbt-05.dtsi"
/ {
model = "PHYTEC phyBOARD-Segin i.MX6 ULL Low Cost with NAND";
diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi
new file mode 100644
index 000000000000..df25814a3371
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 PHYTEC Messtechnik GmbH
+ * Author: Yunus Bas <[email protected]>
+ */
+
+#include "imx6ul-phytec-segin-peb-wlbt-05.dtsi"
+
+&iomuxc {
+ /delete-node/ wlgrp;
+};
+
+&iomuxc_snvs {
+ pinctrl_wl: wlgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3031
+ >;
+ };
+};
--
2.25.1
On Mon, Dec 13, 2021 at 01:38:32PM +0100, Yunus Bas wrote:
> The PEB-AV-02 expansion adapter extends the phyBOARD-Mira boards to
> connect parallel LCD displays, either with capacitive or resistive
> touch.
>
> Signed-off-by: Yunus Bas <[email protected]>
> ---
> Changes in v2:
> - Corrected confusing display node name
> - Updated edt_ft5406 compatible to fit dt-binding scheme
> - Removed some newlines
> ---
> .../boot/dts/imx6dl-phytec-mira-rdk-nand.dts | 1 +
> .../boot/dts/imx6q-phytec-mira-rdk-emmc.dts | 1 +
> .../boot/dts/imx6q-phytec-mira-rdk-nand.dts | 1 +
> .../dts/imx6qdl-phytec-mira-peb-av-02.dtsi | 119 ++++++++++++++++++
> .../boot/dts/imx6qp-phytec-mira-rdk-nand.dts | 1 +
> 5 files changed, 123 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi
>
> diff --git a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
> index b057fa664a6b..8165fae2b1d1 100644
> --- a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
> +++ b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
> @@ -9,6 +9,7 @@
> #include "imx6qdl-phytec-phycore-som.dtsi"
> #include "imx6qdl-phytec-mira.dtsi"
> #include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
> +#include "imx6qdl-phytec-mira-peb-av-02.dtsi"
>
> / {
> model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND";
> diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
> index db6e2cc36759..bbf5097ca974 100644
> --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
> +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
> @@ -9,6 +9,7 @@
> #include "imx6qdl-phytec-phycore-som.dtsi"
> #include "imx6qdl-phytec-mira.dtsi"
> #include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
> +#include "imx6qdl-phytec-mira-peb-av-02.dtsi"
>
> / {
> model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC";
> diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
> index 51ff601b1aec..95051e18324f 100644
> --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
> +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
> @@ -9,6 +9,7 @@
> #include "imx6qdl-phytec-phycore-som.dtsi"
> #include "imx6qdl-phytec-mira.dtsi"
> #include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
> +#include "imx6qdl-phytec-mira-peb-av-02.dtsi"
>
> / {
> model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND";
> diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi
> new file mode 100644
> index 000000000000..9fa1de1fcace
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi
> @@ -0,0 +1,119 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2018 PHYTEC Messtechnik
> + * Author: Christian Hemp <[email protected]>
> + */
> +
> +/ {
> + display: disp0 {
display0 for node name.
Shawn
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx-parallel-display";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_disp0>;
> + interface-pix-fmt = "rgb24";
> + status = "disabled";
> +
> + port@0 {
> + reg = <0>;
> +
> + display0_in: endpoint {
> + remote-endpoint = <&ipu1_di0_disp0>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + display0_out: endpoint {
> + remote-endpoint = <&peb_panel_lcd_in>;
> + };
> + };
> + };
> +
> + panel-lcd {
> + compatible = "edt,etm0700g0edh6";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_disp0_pwr>;
> + power-supply = <®_display>;
> + enable-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
> + backlight = <&backlight>;
> + status = "disabled";
> +
> + port {
> + peb_panel_lcd_in: endpoint {
> + remote-endpoint = <&display0_out>;
> + };
> + };
> + };
> +
> + reg_display: regulator-peb-display {
> + compatible = "regulator-fixed";
> + regulator-name = "peb-display";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +};
> +
> +&i2c1 {
> + edt_ft5x06: touchscreen@38 {
> + compatible = "edt,edt-ft5406";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_edt_ft5x06>;
> + reg = <0x38>;
> + interrupt-parent = <&gpio3>;
> + interrupts = <2 IRQ_TYPE_NONE>;
> + status = "disabled";
> + };
> +};
> +
> +&ipu1_di0_disp0 {
> + remote-endpoint = <&display0_in>;
> +};
> +
> +&iomuxc {
> + pinctrl_disp0: disp0grp {
> + fsl,pins = <
> + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
> + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
> + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
> + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x1b080
> + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
> + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
> + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
> + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
> + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
> + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
> + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
> + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
> + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
> + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
> + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
> + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
> + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
> + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
> + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
> + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
> + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
> + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
> + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
> + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
> + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
> + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
> + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
> + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
> + >;
> + };
> +
> + pinctrl_disp0_pwr: disp0pwrgrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
> + >;
> + };
> +
> + pinctrl_edt_ft5x06: edtft5x06grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0xb0b1
> + >;
> + };
> +};
> diff --git a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
> index 06fe0c5315fc..343639cb035c 100644
> --- a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
> +++ b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
> @@ -9,6 +9,7 @@
> #include "imx6qdl-phytec-phycore-som.dtsi"
> #include "imx6qdl-phytec-mira.dtsi"
> #include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
> +#include "imx6qdl-phytec-mira-peb-av-02.dtsi"
>
> / {
> model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND";
> --
> 2.25.1
>
On Mon, Dec 13, 2021 at 01:38:33PM +0100, Yunus Bas wrote:
> The PEB-WLBT-05 is equipped with a Sterling-LWB radio module, which is
> capable of Wi-Fi 802.11 b/g/n and Bluetooth 4.2.
>
> Signed-off-by: Yunus Bas <[email protected]>
> ---
> Changes in v2:
> - Changed node-name underscores to hyphens
> ---
> .../boot/dts/imx6dl-phytec-mira-rdk-nand.dts | 1 +
> .../boot/dts/imx6q-phytec-mira-rdk-emmc.dts | 1 +
> .../boot/dts/imx6q-phytec-mira-rdk-nand.dts | 1 +
> .../dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi | 82 +++++++++++++++++
> .../boot/dts/imx6qp-phytec-mira-rdk-nand.dts | 1 +
> .../dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 1 +
> .../dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi | 87 +++++++++++++++++++
> .../dts/imx6ull-phytec-segin-ff-rdk-nand.dts | 1 +
> .../dts/imx6ull-phytec-segin-lc-rdk-nand.dts | 1 +
> .../dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi | 19 ++++
> 10 files changed, 195 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi
> create mode 100644 arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi
> create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi
>
> diff --git a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
> index 8165fae2b1d1..d906a7f05aaa 100644
> --- a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
> +++ b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
> @@ -10,6 +10,7 @@
> #include "imx6qdl-phytec-mira.dtsi"
> #include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
> #include "imx6qdl-phytec-mira-peb-av-02.dtsi"
> +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi"
>
> / {
> model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND";
> diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
> index bbf5097ca974..322f071d972f 100644
> --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
> +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
> @@ -10,6 +10,7 @@
> #include "imx6qdl-phytec-mira.dtsi"
> #include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
> #include "imx6qdl-phytec-mira-peb-av-02.dtsi"
> +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi"
>
> / {
> model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC";
> diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
> index 95051e18324f..3f13726c8058 100644
> --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
> +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
> @@ -10,6 +10,7 @@
> #include "imx6qdl-phytec-mira.dtsi"
> #include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
> #include "imx6qdl-phytec-mira-peb-av-02.dtsi"
> +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi"
>
> / {
> model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND";
> diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi
> new file mode 100644
> index 000000000000..0abf3e1e1f62
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi
> @@ -0,0 +1,82 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2021 PHYTEC Messtechnik GmbH
> + * Author: Yunus Bas <[email protected]>
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + reg_wl_en: regulator-wl-en {
> + compatible = "regulator-fixed";
> + regulator-name = "wlan_en";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wl>;
> + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + startup-delay-us = <100>;
> + status = "disabled";
> + };
> +};
> +
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3_bt>;
> + uart-has-rtscts;
> +
> + bluetooth {
> + compatible = "brcm,bcm43438-bt";
> + shutdown-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
> + device-wakeup-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
> + host-wakeup-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>;
> + status = "disabled";
> + };
> +};
> +
> +&usdhc3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc3_wl>;
> + vmmc-supply = <®_wl_en>;
> + bus-width = <4>;
> + non-removable;
> + no-1-8-v;
> + status = "disabled";
> +
> + brmcf: wifi@1 {
> + compatible = "brcm,bcm4329-fmac";
Shouldn't we have a 'reg' property matching the unit-address in the node
name?
Shawn
> + };
> +};
> +
> +&iomuxc {
> + pinctrl_uart3_bt: uart3grp-bt {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
> + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
> + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
> + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0xb0b1 /* BT ENABLE */
> + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0xb0b1 /* DEV WAKEUP */
> + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0xb0b1 /* HOST WAKEUP */
> + >;
> + };
> +
> + pinctrl_usdhc3_wl: usdhc3grp-wl {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
> + >;
> + };
> +
> + pinctrl_wl: wlgrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0xb0b1 /* WLAN ENABLE */
> + >;
> + };
> +};
> diff --git a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
> index 343639cb035c..a18266598d39 100644
> --- a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
> +++ b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
> @@ -10,6 +10,7 @@
> #include "imx6qdl-phytec-mira.dtsi"
> #include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
> #include "imx6qdl-phytec-mira-peb-av-02.dtsi"
> +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi"
>
> / {
> model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND";
> diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
> index bff98e676980..607eddc5030f 100644
> --- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
> +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
> @@ -10,6 +10,7 @@
> #include "imx6ul-phytec-segin.dtsi"
> #include "imx6ul-phytec-segin-peb-eval-01.dtsi"
> #include "imx6ul-phytec-segin-peb-av-02.dtsi"
> +#include "imx6ul-phytec-segin-peb-wlbt-05.dtsi"
>
> / {
> model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND";
> diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi
> new file mode 100644
> index 000000000000..4a75745d6030
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi
> @@ -0,0 +1,87 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2021 PHYTEC Messtechnik GmbH
> + * Author: Yunus Bas <[email protected]>
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + reg_wl_en: regulator-wl-en {
> + compatible = "regulator-fixed";
> + regulator-name = "wlan_en";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wl>;
> + gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + startup-delay-us = <100>;
> + status = "disabled";
> + };
> +};
> +
> +&iomuxc {
> + pinctrl_bt: btgrp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3031 /* BT ENABLE */
> + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x3031 /* HOST WAKEUP */
> + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x3031 /* DEV WAKEUP */
> + >;
> + };
> +
> + pinctrl_uart2_bt: uart2grp-bt {
> + fsl,pins = <
> + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x17059
> + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x17059
> + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x17059
> + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x17059
> + >;
> + };
> +
> + pinctrl_usdhc2_wl: usdhc2grp-wl {
> + fsl,pins = <
> + MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x10051
> + MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x10061
> + MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x10051
> + MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x10051
> + MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x10051
> + MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x10051
> + >;
> + };
> +
> + pinctrl_wl: wlgrp {
> + fsl,pins = <
> + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3031 /* WLAN ENABLE */
> + >;
> + };
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2_bt &pinctrl_bt>;
> + uart-has-rtscts;
> + status = "disabled";
> +
> + bluetooth {
> + compatible = "brcm,bcm43438-bt";
> + shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
> + device-wakeup-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
> + host-wakeup-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
> + };
> +};
> +
> +&usdhc2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc2_wl>;
> + vmmc-supply = <®_wl_en>;
> + bus-width = <4>;
> + non-removable;
> + no-1-8-v;
> + status = "disabled";
> +
> + brmcf: wifi@1 {
> + compatible = "brcm,bcm4329-fmac";
> + };
> +};
> diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
> index c8d3eff9ed4b..1d7362b5ac91 100644
> --- a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
> +++ b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
> @@ -10,6 +10,7 @@
> #include "imx6ull-phytec-segin.dtsi"
> #include "imx6ull-phytec-segin-peb-eval-01.dtsi"
> #include "imx6ull-phytec-segin-peb-av-02.dtsi"
> +#include "imx6ull-phytec-segin-peb-wlbt-05.dtsi"
>
> / {
> model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with NAND";
> diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts
> index e168494e0a6d..4bcbae024d8d 100644
> --- a/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts
> +++ b/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts
> @@ -9,6 +9,7 @@
> #include "imx6ull-phytec-phycore-som.dtsi"
> #include "imx6ull-phytec-segin.dtsi"
> #include "imx6ull-phytec-segin-peb-eval-01.dtsi"
> +#include "imx6ull-phytec-segin-peb-wlbt-05.dtsi"
>
> / {
> model = "PHYTEC phyBOARD-Segin i.MX6 ULL Low Cost with NAND";
> diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi
> new file mode 100644
> index 000000000000..df25814a3371
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi
> @@ -0,0 +1,19 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2021 PHYTEC Messtechnik GmbH
> + * Author: Yunus Bas <[email protected]>
> + */
> +
> +#include "imx6ul-phytec-segin-peb-wlbt-05.dtsi"
> +
> +&iomuxc {
> + /delete-node/ wlgrp;
> +};
> +
> +&iomuxc_snvs {
> + pinctrl_wl: wlgrp {
> + fsl,pins = <
> + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3031
> + >;
> + };
> +};
> --
> 2.25.1
>